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14#include "qemu/osdep.h"
15#include "qemu-common.h"
16#include "cpu.h"
17#include "s390-pci-inst.h"
18#include "s390-pci-bus.h"
19#include "exec/memory-internal.h"
20#include "qemu/error-report.h"
21#include "sysemu/hw_accel.h"
22#include "hw/s390x/tod.h"
23
24#ifndef DEBUG_S390PCI_INST
25#define DEBUG_S390PCI_INST 0
26#endif
27
28#define DPRINTF(fmt, ...) \
29 do { \
30 if (DEBUG_S390PCI_INST) { \
31 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
32 } \
33 } while (0)
34
35static void s390_set_status_code(CPUS390XState *env,
36 uint8_t r, uint64_t status_code)
37{
38 env->regs[r] &= ~0xff000000ULL;
39 env->regs[r] |= (status_code & 0xff) << 24;
40}
41
42static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)
43{
44 S390PCIBusDevice *pbdev = NULL;
45 S390pciState *s = s390_get_phb();
46 uint32_t res_code, initial_l2, g_l2;
47 int rc, i;
48 uint64_t resume_token;
49
50 rc = 0;
51 if (lduw_p(&rrb->request.hdr.len) != 32) {
52 res_code = CLP_RC_LEN;
53 rc = -EINVAL;
54 goto out;
55 }
56
57 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {
58 res_code = CLP_RC_FMT;
59 rc = -EINVAL;
60 goto out;
61 }
62
63 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||
64 ldq_p(&rrb->request.reserved1) != 0) {
65 res_code = CLP_RC_RESNOT0;
66 rc = -EINVAL;
67 goto out;
68 }
69
70 resume_token = ldq_p(&rrb->request.resume_token);
71
72 if (resume_token) {
73 pbdev = s390_pci_find_dev_by_idx(s, resume_token);
74 if (!pbdev) {
75 res_code = CLP_RC_LISTPCI_BADRT;
76 rc = -EINVAL;
77 goto out;
78 }
79 } else {
80 pbdev = s390_pci_find_next_avail_dev(s, NULL);
81 }
82
83 if (lduw_p(&rrb->response.hdr.len) < 48) {
84 res_code = CLP_RC_8K;
85 rc = -EINVAL;
86 goto out;
87 }
88
89 initial_l2 = lduw_p(&rrb->response.hdr.len);
90 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)
91 != 0) {
92 res_code = CLP_RC_LEN;
93 rc = -EINVAL;
94 *cc = 3;
95 goto out;
96 }
97
98 stl_p(&rrb->response.fmt, 0);
99 stq_p(&rrb->response.reserved1, 0);
100 stl_p(&rrb->response.mdd, FH_MASK_SHM);
101 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);
102 rrb->response.flags = UID_CHECKING_ENABLED;
103 rrb->response.entry_size = sizeof(ClpFhListEntry);
104
105 i = 0;
106 g_l2 = LIST_PCI_HDR_LEN;
107 while (g_l2 < initial_l2 && pbdev) {
108 stw_p(&rrb->response.fh_list[i].device_id,
109 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));
110 stw_p(&rrb->response.fh_list[i].vendor_id,
111 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));
112
113 stl_p(&rrb->response.fh_list[i].config,
114 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31);
115 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid);
116 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh);
117
118 g_l2 += sizeof(ClpFhListEntry);
119
120 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
121 g_l2,
122 lduw_p(&rrb->response.fh_list[i].vendor_id),
123 lduw_p(&rrb->response.fh_list[i].device_id),
124 ldl_p(&rrb->response.fh_list[i].fid),
125 ldl_p(&rrb->response.fh_list[i].fh));
126 pbdev = s390_pci_find_next_avail_dev(s, pbdev);
127 i++;
128 }
129
130 if (!pbdev) {
131 resume_token = 0;
132 } else {
133 resume_token = pbdev->fh & FH_MASK_INDEX;
134 }
135 stq_p(&rrb->response.resume_token, resume_token);
136 stw_p(&rrb->response.hdr.len, g_l2);
137 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);
138out:
139 if (rc) {
140 DPRINTF("list pci failed rc 0x%x\n", rc);
141 stw_p(&rrb->response.hdr.rsp, res_code);
142 }
143 return rc;
144}
145
146int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)
147{
148 ClpReqHdr *reqh;
149 ClpRspHdr *resh;
150 S390PCIBusDevice *pbdev;
151 uint32_t req_len;
152 uint32_t res_len;
153 uint8_t buffer[4096 * 2];
154 uint8_t cc = 0;
155 CPUS390XState *env = &cpu->env;
156 S390pciState *s = s390_get_phb();
157 int i;
158
159 if (env->psw.mask & PSW_MASK_PSTATE) {
160 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
161 return 0;
162 }
163
164 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) {
165 s390_cpu_virt_mem_handle_exc(cpu, ra);
166 return 0;
167 }
168 reqh = (ClpReqHdr *)buffer;
169 req_len = lduw_p(&reqh->len);
170 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {
171 s390_program_interrupt(env, PGM_OPERAND, 4, ra);
172 return 0;
173 }
174
175 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
176 req_len + sizeof(*resh))) {
177 s390_cpu_virt_mem_handle_exc(cpu, ra);
178 return 0;
179 }
180 resh = (ClpRspHdr *)(buffer + req_len);
181 res_len = lduw_p(&resh->len);
182 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {
183 s390_program_interrupt(env, PGM_OPERAND, 4, ra);
184 return 0;
185 }
186 if ((req_len + res_len) > 8192) {
187 s390_program_interrupt(env, PGM_OPERAND, 4, ra);
188 return 0;
189 }
190
191 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
192 req_len + res_len)) {
193 s390_cpu_virt_mem_handle_exc(cpu, ra);
194 return 0;
195 }
196
197 if (req_len != 32) {
198 stw_p(&resh->rsp, CLP_RC_LEN);
199 goto out;
200 }
201
202 switch (lduw_p(&reqh->cmd)) {
203 case CLP_LIST_PCI: {
204 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;
205 list_pci(rrb, &cc);
206 break;
207 }
208 case CLP_SET_PCI_FN: {
209 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;
210 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;
211
212 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh));
213 if (!pbdev) {
214 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);
215 goto out;
216 }
217
218 switch (reqsetpci->oc) {
219 case CLP_SET_ENABLE_PCI_FN:
220 switch (reqsetpci->ndas) {
221 case 0:
222 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS);
223 goto out;
224 case 1:
225 break;
226 default:
227 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES);
228 goto out;
229 }
230
231 if (pbdev->fh & FH_MASK_ENABLE) {
232 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
233 goto out;
234 }
235
236 pbdev->fh |= FH_MASK_ENABLE;
237 pbdev->state = ZPCI_FS_ENABLED;
238 stl_p(&ressetpci->fh, pbdev->fh);
239 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
240 break;
241 case CLP_SET_DISABLE_PCI_FN:
242 if (!(pbdev->fh & FH_MASK_ENABLE)) {
243 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
244 goto out;
245 }
246 device_reset(DEVICE(pbdev));
247 pbdev->fh &= ~FH_MASK_ENABLE;
248 pbdev->state = ZPCI_FS_DISABLED;
249 stl_p(&ressetpci->fh, pbdev->fh);
250 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
251 break;
252 default:
253 DPRINTF("unknown set pci command\n");
254 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
255 break;
256 }
257 break;
258 }
259 case CLP_QUERY_PCI_FN: {
260 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;
261 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;
262
263 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh));
264 if (!pbdev) {
265 DPRINTF("query pci no pci dev\n");
266 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);
267 goto out;
268 }
269
270 for (i = 0; i < PCI_BAR_COUNT; i++) {
271 uint32_t data = pci_get_long(pbdev->pdev->config +
272 PCI_BASE_ADDRESS_0 + (i * 4));
273
274 stl_p(&resquery->bar[i], data);
275 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?
276 ctz64(pbdev->pdev->io_regions[i].size) : 0;
277 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i,
278 ldl_p(&resquery->bar[i]),
279 pbdev->pdev->io_regions[i].size,
280 resquery->bar_size[i]);
281 }
282
283 stq_p(&resquery->sdma, ZPCI_SDMA_ADDR);
284 stq_p(&resquery->edma, ZPCI_EDMA_ADDR);
285 stl_p(&resquery->fid, pbdev->fid);
286 stw_p(&resquery->pchid, 0);
287 stw_p(&resquery->ug, 1);
288 stl_p(&resquery->uid, pbdev->uid);
289 stw_p(&resquery->hdr.rsp, CLP_RC_OK);
290 break;
291 }
292 case CLP_QUERY_PCI_FNGRP: {
293 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh;
294 resgrp->fr = 1;
295 stq_p(&resgrp->dasm, 0);
296 stq_p(&resgrp->msia, ZPCI_MSI_ADDR);
297 stw_p(&resgrp->mui, DEFAULT_MUI);
298 stw_p(&resgrp->i, 128);
299 stw_p(&resgrp->maxstbl, 128);
300 resgrp->version = 0;
301
302 stw_p(&resgrp->hdr.rsp, CLP_RC_OK);
303 break;
304 }
305 default:
306 DPRINTF("unknown clp command\n");
307 stw_p(&resh->rsp, CLP_RC_CMD);
308 break;
309 }
310
311out:
312 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer,
313 req_len + res_len)) {
314 s390_cpu_virt_mem_handle_exc(cpu, ra);
315 return 0;
316 }
317 setcc(cpu, cc);
318 return 0;
319}
320
321
322
323
324
325
326
327
328static int zpci_endian_swap(uint64_t *ptr, uint8_t len)
329{
330 uint64_t data = *ptr;
331
332 switch (len) {
333 case 1:
334 break;
335 case 2:
336 data = bswap16(data);
337 break;
338 case 4:
339 data = bswap32(data);
340 break;
341 case 8:
342 data = bswap64(data);
343 break;
344 default:
345 return -EINVAL;
346 }
347 *ptr = data;
348 return 0;
349}
350
351static MemoryRegion *s390_get_subregion(MemoryRegion *mr, uint64_t offset,
352 uint8_t len)
353{
354 MemoryRegion *subregion;
355 uint64_t subregion_size;
356
357 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
358 subregion_size = int128_get64(subregion->size);
359 if ((offset >= subregion->addr) &&
360 (offset + len) <= (subregion->addr + subregion_size)) {
361 mr = subregion;
362 break;
363 }
364 }
365 return mr;
366}
367
368static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
369 uint64_t offset, uint64_t *data, uint8_t len)
370{
371 MemoryRegion *mr;
372
373 mr = pbdev->pdev->io_regions[pcias].memory;
374 mr = s390_get_subregion(mr, offset, len);
375 offset -= mr->addr;
376 return memory_region_dispatch_read(mr, offset, data, len,
377 MEMTXATTRS_UNSPECIFIED);
378}
379
380int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
381{
382 CPUS390XState *env = &cpu->env;
383 S390PCIBusDevice *pbdev;
384 uint64_t offset;
385 uint64_t data;
386 MemTxResult result;
387 uint8_t len;
388 uint32_t fh;
389 uint8_t pcias;
390
391 if (env->psw.mask & PSW_MASK_PSTATE) {
392 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
393 return 0;
394 }
395
396 if (r2 & 0x1) {
397 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
398 return 0;
399 }
400
401 fh = env->regs[r2] >> 32;
402 pcias = (env->regs[r2] >> 16) & 0xf;
403 len = env->regs[r2] & 0xf;
404 offset = env->regs[r2 + 1];
405
406 if (!(fh & FH_MASK_ENABLE)) {
407 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
408 return 0;
409 }
410
411 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
412 if (!pbdev) {
413 DPRINTF("pcilg no pci dev\n");
414 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
415 return 0;
416 }
417
418 switch (pbdev->state) {
419 case ZPCI_FS_PERMANENT_ERROR:
420 case ZPCI_FS_ERROR:
421 setcc(cpu, ZPCI_PCI_LS_ERR);
422 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
423 return 0;
424 default:
425 break;
426 }
427
428 switch (pcias) {
429 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
430 if (!len || (len > (8 - (offset & 0x7)))) {
431 s390_program_interrupt(env, PGM_OPERAND, 4, ra);
432 return 0;
433 }
434 result = zpci_read_bar(pbdev, pcias, offset, &data, len);
435 if (result != MEMTX_OK) {
436 s390_program_interrupt(env, PGM_OPERAND, 4, ra);
437 return 0;
438 }
439 break;
440 case ZPCI_CONFIG_BAR:
441 if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
442 s390_program_interrupt(env, PGM_OPERAND, 4, ra);
443 return 0;
444 }
445 data = pci_host_config_read_common(
446 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len);
447
448 if (zpci_endian_swap(&data, len)) {
449 s390_program_interrupt(env, PGM_OPERAND, 4, ra);
450 return 0;
451 }
452 break;
453 default:
454 DPRINTF("pcilg invalid space\n");
455 setcc(cpu, ZPCI_PCI_LS_ERR);
456 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
457 return 0;
458 }
459
460 pbdev->fmb.counter[ZPCI_FMB_CNT_LD]++;
461
462 env->regs[r1] = data;
463 setcc(cpu, ZPCI_PCI_LS_OK);
464 return 0;
465}
466
467static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
468 uint64_t offset, uint64_t data, uint8_t len)
469{
470 MemoryRegion *mr;
471
472 mr = pbdev->pdev->io_regions[pcias].memory;
473 mr = s390_get_subregion(mr, offset, len);
474 offset -= mr->addr;
475 return memory_region_dispatch_write(mr, offset, data, len,
476 MEMTXATTRS_UNSPECIFIED);
477}
478
479int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
480{
481 CPUS390XState *env = &cpu->env;
482 uint64_t offset, data;
483 S390PCIBusDevice *pbdev;
484 MemTxResult result;
485 uint8_t len;
486 uint32_t fh;
487 uint8_t pcias;
488
489 if (env->psw.mask & PSW_MASK_PSTATE) {
490 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
491 return 0;
492 }
493
494 if (r2 & 0x1) {
495 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
496 return 0;
497 }
498
499 fh = env->regs[r2] >> 32;
500 pcias = (env->regs[r2] >> 16) & 0xf;
501 len = env->regs[r2] & 0xf;
502 offset = env->regs[r2 + 1];
503 data = env->regs[r1];
504
505 if (!(fh & FH_MASK_ENABLE)) {
506 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
507 return 0;
508 }
509
510 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
511 if (!pbdev) {
512 DPRINTF("pcistg no pci dev\n");
513 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
514 return 0;
515 }
516
517 switch (pbdev->state) {
518
519
520
521 case ZPCI_FS_PERMANENT_ERROR:
522 case ZPCI_FS_ERROR:
523 setcc(cpu, ZPCI_PCI_LS_ERR);
524 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
525 return 0;
526 default:
527 break;
528 }
529
530 switch (pcias) {
531
532 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
533
534
535
536 if (!len || (len > (8 - (offset & 0x7)))) {
537 s390_program_interrupt(env, PGM_OPERAND, 4, ra);
538 return 0;
539 }
540
541 result = zpci_write_bar(pbdev, pcias, offset, data, len);
542 if (result != MEMTX_OK) {
543 s390_program_interrupt(env, PGM_OPERAND, 4, ra);
544 return 0;
545 }
546 break;
547 case ZPCI_CONFIG_BAR:
548
549
550 if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
551 s390_program_interrupt(env, PGM_OPERAND, 4, ra);
552 return 0;
553 }
554
555 zpci_endian_swap(&data, len);
556 pci_host_config_write_common(pbdev->pdev, offset,
557 pci_config_size(pbdev->pdev),
558 data, len);
559 break;
560 default:
561 DPRINTF("pcistg invalid space\n");
562 setcc(cpu, ZPCI_PCI_LS_ERR);
563 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
564 return 0;
565 }
566
567 pbdev->fmb.counter[ZPCI_FMB_CNT_ST]++;
568
569 setcc(cpu, ZPCI_PCI_LS_OK);
570 return 0;
571}
572
573static void s390_pci_update_iotlb(S390PCIIOMMU *iommu, S390IOTLBEntry *entry)
574{
575 S390IOTLBEntry *cache = g_hash_table_lookup(iommu->iotlb, &entry->iova);
576 IOMMUTLBEntry notify = {
577 .target_as = &address_space_memory,
578 .iova = entry->iova,
579 .translated_addr = entry->translated_addr,
580 .perm = entry->perm,
581 .addr_mask = ~PAGE_MASK,
582 };
583
584 if (entry->perm == IOMMU_NONE) {
585 if (!cache) {
586 return;
587 }
588 g_hash_table_remove(iommu->iotlb, &entry->iova);
589 } else {
590 if (cache) {
591 if (cache->perm == entry->perm &&
592 cache->translated_addr == entry->translated_addr) {
593 return;
594 }
595
596 notify.perm = IOMMU_NONE;
597 memory_region_notify_iommu(&iommu->iommu_mr, 0, notify);
598 notify.perm = entry->perm;
599 }
600
601 cache = g_new(S390IOTLBEntry, 1);
602 cache->iova = entry->iova;
603 cache->translated_addr = entry->translated_addr;
604 cache->len = PAGE_SIZE;
605 cache->perm = entry->perm;
606 g_hash_table_replace(iommu->iotlb, &cache->iova, cache);
607 }
608
609 memory_region_notify_iommu(&iommu->iommu_mr, 0, notify);
610}
611
612int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
613{
614 CPUS390XState *env = &cpu->env;
615 uint32_t fh;
616 uint16_t error = 0;
617 S390PCIBusDevice *pbdev;
618 S390PCIIOMMU *iommu;
619 S390IOTLBEntry entry;
620 hwaddr start, end;
621
622 if (env->psw.mask & PSW_MASK_PSTATE) {
623 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
624 return 0;
625 }
626
627 if (r2 & 0x1) {
628 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
629 return 0;
630 }
631
632 fh = env->regs[r1] >> 32;
633 start = env->regs[r2];
634 end = start + env->regs[r2 + 1];
635
636 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
637 if (!pbdev) {
638 DPRINTF("rpcit no pci dev\n");
639 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
640 return 0;
641 }
642
643 switch (pbdev->state) {
644 case ZPCI_FS_RESERVED:
645 case ZPCI_FS_STANDBY:
646 case ZPCI_FS_DISABLED:
647 case ZPCI_FS_PERMANENT_ERROR:
648 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
649 return 0;
650 case ZPCI_FS_ERROR:
651 setcc(cpu, ZPCI_PCI_LS_ERR);
652 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER);
653 return 0;
654 default:
655 break;
656 }
657
658 iommu = pbdev->iommu;
659 if (!iommu->g_iota) {
660 error = ERR_EVENT_INVALAS;
661 goto err;
662 }
663
664 if (end < iommu->pba || start > iommu->pal) {
665 error = ERR_EVENT_OORANGE;
666 goto err;
667 }
668
669 while (start < end) {
670 error = s390_guest_io_table_walk(iommu->g_iota, start, &entry);
671 if (error) {
672 break;
673 }
674
675 start += entry.len;
676 while (entry.iova < start && entry.iova < end) {
677 s390_pci_update_iotlb(iommu, &entry);
678 entry.iova += PAGE_SIZE;
679 entry.translated_addr += PAGE_SIZE;
680 }
681 }
682err:
683 if (error) {
684 pbdev->state = ZPCI_FS_ERROR;
685 setcc(cpu, ZPCI_PCI_LS_ERR);
686 s390_set_status_code(env, r1, ZPCI_PCI_ST_FUNC_IN_ERR);
687 s390_pci_generate_error_event(error, pbdev->fh, pbdev->fid, start, 0);
688 } else {
689 pbdev->fmb.counter[ZPCI_FMB_CNT_RPCIT]++;
690 setcc(cpu, ZPCI_PCI_LS_OK);
691 }
692 return 0;
693}
694
695int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
696 uint8_t ar, uintptr_t ra)
697{
698 CPUS390XState *env = &cpu->env;
699 S390PCIBusDevice *pbdev;
700 MemoryRegion *mr;
701 MemTxResult result;
702 uint64_t offset;
703 int i;
704 uint32_t fh;
705 uint8_t pcias;
706 uint8_t len;
707 uint8_t buffer[128];
708
709 if (env->psw.mask & PSW_MASK_PSTATE) {
710 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
711 return 0;
712 }
713
714 fh = env->regs[r1] >> 32;
715 pcias = (env->regs[r1] >> 16) & 0xf;
716 len = env->regs[r1] & 0xff;
717 offset = env->regs[r3];
718
719 if (!(fh & FH_MASK_ENABLE)) {
720 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
721 return 0;
722 }
723
724 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
725 if (!pbdev) {
726 DPRINTF("pcistb no pci dev fh 0x%x\n", fh);
727 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
728 return 0;
729 }
730
731 switch (pbdev->state) {
732 case ZPCI_FS_PERMANENT_ERROR:
733 case ZPCI_FS_ERROR:
734 setcc(cpu, ZPCI_PCI_LS_ERR);
735 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED);
736 return 0;
737 default:
738 break;
739 }
740
741 if (pcias > ZPCI_IO_BAR_MAX) {
742 DPRINTF("pcistb invalid space\n");
743 setcc(cpu, ZPCI_PCI_LS_ERR);
744 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS);
745 return 0;
746 }
747
748
749
750 if (offset % 8) {
751 goto specification_error;
752 }
753
754
755 if ((len <= 8) || (len % 8) || (len > pbdev->maxstbl)) {
756 goto specification_error;
757 }
758
759 if (((offset & 0xfff) + len) > 0x1000) {
760 goto specification_error;
761 }
762
763 if (gaddr & 0x07UL) {
764 goto specification_error;
765 }
766
767 mr = pbdev->pdev->io_regions[pcias].memory;
768 mr = s390_get_subregion(mr, offset, len);
769 offset -= mr->addr;
770
771 if (!memory_region_access_valid(mr, offset, len, true,
772 MEMTXATTRS_UNSPECIFIED)) {
773 s390_program_interrupt(env, PGM_OPERAND, 6, ra);
774 return 0;
775 }
776
777 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) {
778 s390_cpu_virt_mem_handle_exc(cpu, ra);
779 return 0;
780 }
781
782 for (i = 0; i < len / 8; i++) {
783 result = memory_region_dispatch_write(mr, offset + i * 8,
784 ldq_p(buffer + i * 8), 8,
785 MEMTXATTRS_UNSPECIFIED);
786 if (result != MEMTX_OK) {
787 s390_program_interrupt(env, PGM_OPERAND, 6, ra);
788 return 0;
789 }
790 }
791
792 pbdev->fmb.counter[ZPCI_FMB_CNT_STB]++;
793
794 setcc(cpu, ZPCI_PCI_LS_OK);
795 return 0;
796
797specification_error:
798 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
799 return 0;
800}
801
802static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
803{
804 int ret, len;
805 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data));
806
807 pbdev->routes.adapter.adapter_id = css_get_adapter_id(
808 CSS_IO_ADAPTER_PCI, isc);
809 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t));
810 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long);
811 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len);
812
813 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
814 if (ret) {
815 goto out;
816 }
817
818 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator);
819 if (ret) {
820 goto out;
821 }
822
823 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);
824 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));
825 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);
826 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));
827 pbdev->isc = isc;
828 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));
829 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));
830
831 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
832 return 0;
833out:
834 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
835 release_indicator(&pbdev->routes.adapter, pbdev->indicator);
836 pbdev->summary_ind = NULL;
837 pbdev->indicator = NULL;
838 return ret;
839}
840
841int pci_dereg_irqs(S390PCIBusDevice *pbdev)
842{
843 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
844 release_indicator(&pbdev->routes.adapter, pbdev->indicator);
845
846 pbdev->summary_ind = NULL;
847 pbdev->indicator = NULL;
848 pbdev->routes.adapter.summary_addr = 0;
849 pbdev->routes.adapter.summary_offset = 0;
850 pbdev->routes.adapter.ind_addr = 0;
851 pbdev->routes.adapter.ind_offset = 0;
852 pbdev->isc = 0;
853 pbdev->noi = 0;
854 pbdev->sum = 0;
855
856 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
857 return 0;
858}
859
860static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib,
861 uintptr_t ra)
862{
863 uint64_t pba = ldq_p(&fib.pba);
864 uint64_t pal = ldq_p(&fib.pal);
865 uint64_t g_iota = ldq_p(&fib.iota);
866 uint8_t dt = (g_iota >> 2) & 0x7;
867 uint8_t t = (g_iota >> 11) & 0x1;
868
869 pba &= ~0xfff;
870 pal |= 0xfff;
871 if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
872 s390_program_interrupt(env, PGM_OPERAND, 6, ra);
873 return -EINVAL;
874 }
875
876
877 if (!(dt == ZPCI_IOTA_RTTO && t)) {
878 error_report("unsupported ioat dt %d t %d", dt, t);
879 s390_program_interrupt(env, PGM_OPERAND, 6, ra);
880 return -EINVAL;
881 }
882
883 iommu->pba = pba;
884 iommu->pal = pal;
885 iommu->g_iota = g_iota;
886
887 s390_pci_iommu_enable(iommu);
888
889 return 0;
890}
891
892void pci_dereg_ioat(S390PCIIOMMU *iommu)
893{
894 s390_pci_iommu_disable(iommu);
895 iommu->pba = 0;
896 iommu->pal = 0;
897 iommu->g_iota = 0;
898}
899
900void fmb_timer_free(S390PCIBusDevice *pbdev)
901{
902 if (pbdev->fmb_timer) {
903 timer_del(pbdev->fmb_timer);
904 timer_free(pbdev->fmb_timer);
905 pbdev->fmb_timer = NULL;
906 }
907 pbdev->fmb_addr = 0;
908 memset(&pbdev->fmb, 0, sizeof(ZpciFmb));
909}
910
911static int fmb_do_update(S390PCIBusDevice *pbdev, int offset, uint64_t val,
912 int len)
913{
914 MemTxResult ret;
915 uint64_t dst = pbdev->fmb_addr + offset;
916
917 switch (len) {
918 case 8:
919 address_space_stq_be(&address_space_memory, dst, val,
920 MEMTXATTRS_UNSPECIFIED,
921 &ret);
922 break;
923 case 4:
924 address_space_stl_be(&address_space_memory, dst, val,
925 MEMTXATTRS_UNSPECIFIED,
926 &ret);
927 break;
928 case 2:
929 address_space_stw_be(&address_space_memory, dst, val,
930 MEMTXATTRS_UNSPECIFIED,
931 &ret);
932 break;
933 case 1:
934 address_space_stb(&address_space_memory, dst, val,
935 MEMTXATTRS_UNSPECIFIED,
936 &ret);
937 break;
938 default:
939 ret = MEMTX_ERROR;
940 break;
941 }
942 if (ret != MEMTX_OK) {
943 s390_pci_generate_error_event(ERR_EVENT_FMBA, pbdev->fh, pbdev->fid,
944 pbdev->fmb_addr, 0);
945 fmb_timer_free(pbdev);
946 }
947
948 return ret;
949}
950
951static void fmb_update(void *opaque)
952{
953 S390PCIBusDevice *pbdev = opaque;
954 int64_t t = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
955 int i;
956
957
958 pbdev->fmb.last_update *= 2;
959 pbdev->fmb.last_update |= UPDATE_U_BIT;
960 if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update),
961 pbdev->fmb.last_update,
962 sizeof(pbdev->fmb.last_update))) {
963 return;
964 }
965
966
967 if (fmb_do_update(pbdev, offsetof(ZpciFmb, sample),
968 pbdev->fmb.sample++,
969 sizeof(pbdev->fmb.sample))) {
970 return;
971 }
972
973
974 for (i = 0; i < ZPCI_FMB_CNT_MAX; i++) {
975 if (fmb_do_update(pbdev, offsetof(ZpciFmb, counter[i]),
976 pbdev->fmb.counter[i],
977 sizeof(pbdev->fmb.counter[0]))) {
978 return;
979 }
980 }
981
982
983 pbdev->fmb.last_update = time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
984 pbdev->fmb.last_update *= 2;
985 if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update),
986 pbdev->fmb.last_update,
987 sizeof(pbdev->fmb.last_update))) {
988 return;
989 }
990 timer_mod(pbdev->fmb_timer, t + DEFAULT_MUI);
991}
992
993int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
994 uintptr_t ra)
995{
996 CPUS390XState *env = &cpu->env;
997 uint8_t oc, dmaas;
998 uint32_t fh;
999 ZpciFib fib;
1000 S390PCIBusDevice *pbdev;
1001 uint64_t cc = ZPCI_PCI_LS_OK;
1002
1003 if (env->psw.mask & PSW_MASK_PSTATE) {
1004 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
1005 return 0;
1006 }
1007
1008 oc = env->regs[r1] & 0xff;
1009 dmaas = (env->regs[r1] >> 16) & 0xff;
1010 fh = env->regs[r1] >> 32;
1011
1012 if (fiba & 0x7) {
1013 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
1014 return 0;
1015 }
1016
1017 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
1018 if (!pbdev) {
1019 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh);
1020 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1021 return 0;
1022 }
1023
1024 switch (pbdev->state) {
1025 case ZPCI_FS_RESERVED:
1026 case ZPCI_FS_STANDBY:
1027 case ZPCI_FS_DISABLED:
1028 case ZPCI_FS_PERMANENT_ERROR:
1029 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1030 return 0;
1031 default:
1032 break;
1033 }
1034
1035 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
1036 s390_cpu_virt_mem_handle_exc(cpu, ra);
1037 return 0;
1038 }
1039
1040 if (fib.fmt != 0) {
1041 s390_program_interrupt(env, PGM_OPERAND, 6, ra);
1042 return 0;
1043 }
1044
1045 switch (oc) {
1046 case ZPCI_MOD_FC_REG_INT:
1047 if (pbdev->summary_ind) {
1048 cc = ZPCI_PCI_LS_ERR;
1049 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1050 } else if (reg_irqs(env, pbdev, fib)) {
1051 cc = ZPCI_PCI_LS_ERR;
1052 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL);
1053 }
1054 break;
1055 case ZPCI_MOD_FC_DEREG_INT:
1056 if (!pbdev->summary_ind) {
1057 cc = ZPCI_PCI_LS_ERR;
1058 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1059 } else {
1060 pci_dereg_irqs(pbdev);
1061 }
1062 break;
1063 case ZPCI_MOD_FC_REG_IOAT:
1064 if (dmaas != 0) {
1065 cc = ZPCI_PCI_LS_ERR;
1066 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
1067 } else if (pbdev->iommu->enabled) {
1068 cc = ZPCI_PCI_LS_ERR;
1069 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1070 } else if (reg_ioat(env, pbdev->iommu, fib, ra)) {
1071 cc = ZPCI_PCI_LS_ERR;
1072 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
1073 }
1074 break;
1075 case ZPCI_MOD_FC_DEREG_IOAT:
1076 if (dmaas != 0) {
1077 cc = ZPCI_PCI_LS_ERR;
1078 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
1079 } else if (!pbdev->iommu->enabled) {
1080 cc = ZPCI_PCI_LS_ERR;
1081 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1082 } else {
1083 pci_dereg_ioat(pbdev->iommu);
1084 }
1085 break;
1086 case ZPCI_MOD_FC_REREG_IOAT:
1087 if (dmaas != 0) {
1088 cc = ZPCI_PCI_LS_ERR;
1089 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
1090 } else if (!pbdev->iommu->enabled) {
1091 cc = ZPCI_PCI_LS_ERR;
1092 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1093 } else {
1094 pci_dereg_ioat(pbdev->iommu);
1095 if (reg_ioat(env, pbdev->iommu, fib, ra)) {
1096 cc = ZPCI_PCI_LS_ERR;
1097 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
1098 }
1099 }
1100 break;
1101 case ZPCI_MOD_FC_RESET_ERROR:
1102 switch (pbdev->state) {
1103 case ZPCI_FS_BLOCKED:
1104 case ZPCI_FS_ERROR:
1105 pbdev->state = ZPCI_FS_ENABLED;
1106 break;
1107 default:
1108 cc = ZPCI_PCI_LS_ERR;
1109 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1110 }
1111 break;
1112 case ZPCI_MOD_FC_RESET_BLOCK:
1113 switch (pbdev->state) {
1114 case ZPCI_FS_ERROR:
1115 pbdev->state = ZPCI_FS_BLOCKED;
1116 break;
1117 default:
1118 cc = ZPCI_PCI_LS_ERR;
1119 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1120 }
1121 break;
1122 case ZPCI_MOD_FC_SET_MEASURE: {
1123 uint64_t fmb_addr = ldq_p(&fib.fmb_addr);
1124
1125 if (fmb_addr & FMBK_MASK) {
1126 cc = ZPCI_PCI_LS_ERR;
1127 s390_pci_generate_error_event(ERR_EVENT_FMBPRO, pbdev->fh,
1128 pbdev->fid, fmb_addr, 0);
1129 fmb_timer_free(pbdev);
1130 break;
1131 }
1132
1133 if (!fmb_addr) {
1134
1135 fmb_timer_free(pbdev);
1136 break;
1137 }
1138
1139 if (!pbdev->fmb_timer) {
1140 pbdev->fmb_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
1141 fmb_update, pbdev);
1142 } else if (timer_pending(pbdev->fmb_timer)) {
1143
1144 timer_del(pbdev->fmb_timer);
1145 }
1146 pbdev->fmb_addr = fmb_addr;
1147 timer_mod(pbdev->fmb_timer,
1148 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + DEFAULT_MUI);
1149 break;
1150 }
1151 default:
1152 s390_program_interrupt(&cpu->env, PGM_OPERAND, 6, ra);
1153 cc = ZPCI_PCI_LS_ERR;
1154 }
1155
1156 setcc(cpu, cc);
1157 return 0;
1158}
1159
1160int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
1161 uintptr_t ra)
1162{
1163 CPUS390XState *env = &cpu->env;
1164 uint8_t dmaas;
1165 uint32_t fh;
1166 ZpciFib fib;
1167 S390PCIBusDevice *pbdev;
1168 uint32_t data;
1169 uint64_t cc = ZPCI_PCI_LS_OK;
1170
1171 if (env->psw.mask & PSW_MASK_PSTATE) {
1172 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
1173 return 0;
1174 }
1175
1176 fh = env->regs[r1] >> 32;
1177 dmaas = (env->regs[r1] >> 16) & 0xff;
1178
1179 if (dmaas) {
1180 setcc(cpu, ZPCI_PCI_LS_ERR);
1181 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS);
1182 return 0;
1183 }
1184
1185 if (fiba & 0x7) {
1186 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
1187 return 0;
1188 }
1189
1190 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX);
1191 if (!pbdev) {
1192 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1193 return 0;
1194 }
1195
1196 memset(&fib, 0, sizeof(fib));
1197
1198 switch (pbdev->state) {
1199 case ZPCI_FS_RESERVED:
1200 case ZPCI_FS_STANDBY:
1201 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1202 return 0;
1203 case ZPCI_FS_DISABLED:
1204 if (fh & FH_MASK_ENABLE) {
1205 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1206 return 0;
1207 }
1208 goto out;
1209
1210
1211 case ZPCI_FS_ERROR:
1212 fib.fc |= 0x20;
1213 case ZPCI_FS_BLOCKED:
1214 fib.fc |= 0x40;
1215 case ZPCI_FS_ENABLED:
1216 fib.fc |= 0x80;
1217 if (pbdev->iommu->enabled) {
1218 fib.fc |= 0x10;
1219 }
1220 if (!(fh & FH_MASK_ENABLE)) {
1221 env->regs[r1] |= 1ULL << 63;
1222 }
1223 break;
1224 case ZPCI_FS_PERMANENT_ERROR:
1225 setcc(cpu, ZPCI_PCI_LS_ERR);
1226 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR);
1227 return 0;
1228 }
1229
1230 stq_p(&fib.pba, pbdev->iommu->pba);
1231 stq_p(&fib.pal, pbdev->iommu->pal);
1232 stq_p(&fib.iota, pbdev->iommu->g_iota);
1233 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
1234 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
1235 stq_p(&fib.fmb_addr, pbdev->fmb_addr);
1236
1237 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
1238 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
1239 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
1240 stl_p(&fib.data, data);
1241
1242out:
1243 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
1244 s390_cpu_virt_mem_handle_exc(cpu, ra);
1245 return 0;
1246 }
1247
1248 setcc(cpu, cc);
1249 return 0;
1250}
1251
