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24#include "qemu/osdep.h"
25#include "qemu/log.h"
26#include "hw/hw.h"
27#include "hw/sysbus.h"
28#include "sysemu/sysemu.h"
29#include "trace.h"
30#include "qapi/error.h"
31#include "sysemu/block-backend.h"
32#include "sysemu/blockdev.h"
33#include "hw/sd/sd.h"
34
35enum {
36 ENABLE_CMD_TX = (1<<0),
37 ENABLE_CMD_RX = (1<<1),
38 ENABLE_DAT_TX = (1<<2),
39 ENABLE_DAT_RX = (1<<3),
40};
41
42enum {
43 PENDING_CMD_TX = (1<<0),
44 PENDING_CMD_RX = (1<<1),
45 PENDING_DAT_TX = (1<<2),
46 PENDING_DAT_RX = (1<<3),
47};
48
49enum {
50 START_CMD_TX = (1<<0),
51 START_DAT_RX = (1<<1),
52};
53
54enum {
55 R_CLK2XDIV = 0,
56 R_ENABLE,
57 R_PENDING,
58 R_START,
59 R_CMD,
60 R_DAT,
61 R_MAX
62};
63
64#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
65#define MILKYMIST_MEMCARD(obj) \
66 OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
67
68struct MilkymistMemcardState {
69 SysBusDevice parent_obj;
70
71 MemoryRegion regs_region;
72 SDBus sdbus;
73
74 int command_write_ptr;
75 int response_read_ptr;
76 int response_len;
77 int ignore_next_cmd;
78 int enabled;
79 uint8_t command[6];
80 uint8_t response[17];
81 uint32_t regs[R_MAX];
82};
83typedef struct MilkymistMemcardState MilkymistMemcardState;
84
85static void update_pending_bits(MilkymistMemcardState *s)
86{
87
88 s->regs[R_PENDING] = 0;
89
90 if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
91 s->regs[R_PENDING] |= PENDING_CMD_RX;
92 }
93 if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
94 s->regs[R_PENDING] |= PENDING_DAT_RX;
95 }
96}
97
98static void memcard_sd_command(MilkymistMemcardState *s)
99{
100 SDRequest req;
101
102 req.cmd = s->command[0] & 0x3f;
103 req.arg = ldl_be_p(s->command + 1);
104 req.crc = s->command[5];
105
106 s->response[0] = req.cmd;
107 s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
108 s->response_read_ptr = 0;
109
110 if (s->response_len == 16) {
111
112 s->response[0] = 0x3f;
113 s->response_len += 1;
114 } else if (s->response_len == 4) {
115
116 s->response[5] = 0;
117 s->response_len += 2;
118 }
119
120 if (req.cmd == 0) {
121
122
123 s->ignore_next_cmd = 1;
124 }
125}
126
127static uint64_t memcard_read(void *opaque, hwaddr addr,
128 unsigned size)
129{
130 MilkymistMemcardState *s = opaque;
131 uint32_t r = 0;
132
133 addr >>= 2;
134 switch (addr) {
135 case R_CMD:
136 if (!s->enabled) {
137 r = 0xff;
138 } else {
139 r = s->response[s->response_read_ptr++];
140 if (s->response_read_ptr > s->response_len) {
141 qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
142 "read more cmd bytes than available: clipping\n");
143 s->response_read_ptr = 0;
144 }
145 }
146 break;
147 case R_DAT:
148 if (!s->enabled) {
149 r = 0xffffffff;
150 } else {
151 r = 0;
152 r |= sdbus_read_data(&s->sdbus) << 24;
153 r |= sdbus_read_data(&s->sdbus) << 16;
154 r |= sdbus_read_data(&s->sdbus) << 8;
155 r |= sdbus_read_data(&s->sdbus);
156 }
157 break;
158 case R_CLK2XDIV:
159 case R_ENABLE:
160 case R_PENDING:
161 case R_START:
162 r = s->regs[addr];
163 break;
164
165 default:
166 qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
167 "read access to unknown register 0x%" HWADDR_PRIx "\n",
168 addr << 2);
169 break;
170 }
171
172 trace_milkymist_memcard_memory_read(addr << 2, r);
173
174 return r;
175}
176
177static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
178 unsigned size)
179{
180 MilkymistMemcardState *s = opaque;
181
182 trace_milkymist_memcard_memory_write(addr, value);
183
184 addr >>= 2;
185 switch (addr) {
186 case R_PENDING:
187
188 s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
189 update_pending_bits(s);
190 break;
191 case R_CMD:
192 if (!s->enabled) {
193 break;
194 }
195 if (s->ignore_next_cmd) {
196 s->ignore_next_cmd = 0;
197 break;
198 }
199 s->command[s->command_write_ptr] = value & 0xff;
200 s->command_write_ptr = (s->command_write_ptr + 1) % 6;
201 if (s->command_write_ptr == 0) {
202 memcard_sd_command(s);
203 }
204 break;
205 case R_DAT:
206 if (!s->enabled) {
207 break;
208 }
209 sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
210 sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
211 sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
212 sdbus_write_data(&s->sdbus, value & 0xff);
213 break;
214 case R_ENABLE:
215 s->regs[addr] = value;
216 update_pending_bits(s);
217 break;
218 case R_CLK2XDIV:
219 case R_START:
220 s->regs[addr] = value;
221 break;
222
223 default:
224 qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
225 "write access to unknown register 0x%" HWADDR_PRIx " "
226 "(value 0x%" PRIx64 ")\n", addr << 2, value);
227 break;
228 }
229}
230
231static const MemoryRegionOps memcard_mmio_ops = {
232 .read = memcard_read,
233 .write = memcard_write,
234 .valid = {
235 .min_access_size = 4,
236 .max_access_size = 4,
237 },
238 .endianness = DEVICE_NATIVE_ENDIAN,
239};
240
241static void milkymist_memcard_reset(DeviceState *d)
242{
243 MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
244 int i;
245
246 s->command_write_ptr = 0;
247 s->response_read_ptr = 0;
248 s->response_len = 0;
249
250 for (i = 0; i < R_MAX; i++) {
251 s->regs[i] = 0;
252 }
253}
254
255static void milkymist_memcard_init(Object *obj)
256{
257 MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
258 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
259
260 memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
261 "milkymist-memcard", R_MAX * 4);
262 sysbus_init_mmio(dev, &s->regs_region);
263}
264
265static void milkymist_memcard_realize(DeviceState *dev, Error **errp)
266{
267 MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
268 DeviceState *carddev;
269 BlockBackend *blk;
270 DriveInfo *dinfo;
271 Error *err = NULL;
272
273 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
274 dev, "sd-bus");
275
276
277
278 dinfo = drive_get_next(IF_SD);
279 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
280 carddev = qdev_create(&s->sdbus.qbus, TYPE_SD_CARD);
281 qdev_prop_set_drive(carddev, "drive", blk, &err);
282 object_property_set_bool(OBJECT(carddev), true, "realized", &err);
283 if (err) {
284 error_setg(errp, "failed to init SD card: %s", error_get_pretty(err));
285 return;
286 }
287 s->enabled = blk && blk_is_inserted(blk);
288}
289
290static const VMStateDescription vmstate_milkymist_memcard = {
291 .name = "milkymist-memcard",
292 .version_id = 1,
293 .minimum_version_id = 1,
294 .fields = (VMStateField[]) {
295 VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
296 VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
297 VMSTATE_INT32(response_len, MilkymistMemcardState),
298 VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
299 VMSTATE_INT32(enabled, MilkymistMemcardState),
300 VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
301 VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
302 VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
303 VMSTATE_END_OF_LIST()
304 }
305};
306
307static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
308{
309 DeviceClass *dc = DEVICE_CLASS(klass);
310
311 dc->realize = milkymist_memcard_realize;
312 dc->reset = milkymist_memcard_reset;
313 dc->vmsd = &vmstate_milkymist_memcard;
314
315 dc->user_creatable = false;
316}
317
318static const TypeInfo milkymist_memcard_info = {
319 .name = TYPE_MILKYMIST_MEMCARD,
320 .parent = TYPE_SYS_BUS_DEVICE,
321 .instance_size = sizeof(MilkymistMemcardState),
322 .instance_init = milkymist_memcard_init,
323 .class_init = milkymist_memcard_class_init,
324};
325
326static void milkymist_memcard_register_types(void)
327{
328 type_register_static(&milkymist_memcard_info);
329}
330
331type_init(milkymist_memcard_register_types)
332
