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14#include "qemu/osdep.h"
15#include "hw/timer/pl031.h"
16#include "hw/sysbus.h"
17#include "qemu/timer.h"
18#include "sysemu/sysemu.h"
19#include "qemu/cutils.h"
20#include "qemu/log.h"
21#include "trace.h"
22
23#define RTC_DR 0x00
24#define RTC_MR 0x04
25#define RTC_LR 0x08
26#define RTC_CR 0x0c
27#define RTC_IMSC 0x10
28#define RTC_RIS 0x14
29#define RTC_MIS 0x18
30#define RTC_ICR 0x1c
31
32static const unsigned char pl031_id[] = {
33 0x31, 0x10, 0x14, 0x00,
34 0x0d, 0xf0, 0x05, 0xb1
35};
36
37static void pl031_update(PL031State *s)
38{
39 uint32_t flags = s->is & s->im;
40
41 trace_pl031_irq_state(flags);
42 qemu_set_irq(s->irq, flags);
43}
44
45static void pl031_interrupt(void * opaque)
46{
47 PL031State *s = (PL031State *)opaque;
48
49 s->is = 1;
50 trace_pl031_alarm_raised();
51 pl031_update(s);
52}
53
54static uint32_t pl031_get_count(PL031State *s)
55{
56 int64_t now = qemu_clock_get_ns(rtc_clock);
57 return s->tick_offset + now / NANOSECONDS_PER_SECOND;
58}
59
60static void pl031_set_alarm(PL031State *s)
61{
62 uint32_t ticks;
63
64
65
66 ticks = s->mr - pl031_get_count(s);
67 trace_pl031_set_alarm(ticks);
68 if (ticks == 0) {
69 timer_del(s->timer);
70 pl031_interrupt(s);
71 } else {
72 int64_t now = qemu_clock_get_ns(rtc_clock);
73 timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
74 }
75}
76
77static uint64_t pl031_read(void *opaque, hwaddr offset,
78 unsigned size)
79{
80 PL031State *s = (PL031State *)opaque;
81 uint64_t r;
82
83 switch (offset) {
84 case RTC_DR:
85 r = pl031_get_count(s);
86 break;
87 case RTC_MR:
88 r = s->mr;
89 break;
90 case RTC_IMSC:
91 r = s->im;
92 break;
93 case RTC_RIS:
94 r = s->is;
95 break;
96 case RTC_LR:
97 r = s->lr;
98 break;
99 case RTC_CR:
100
101 r = 1;
102 break;
103 case RTC_MIS:
104 r = s->is & s->im;
105 break;
106 case 0xfe0 ... 0xfff:
107 r = pl031_id[(offset - 0xfe0) >> 2];
108 break;
109 case RTC_ICR:
110 qemu_log_mask(LOG_GUEST_ERROR,
111 "pl031: read of write-only register at offset 0x%x\n",
112 (int)offset);
113 r = 0;
114 break;
115 default:
116 qemu_log_mask(LOG_GUEST_ERROR,
117 "pl031_read: Bad offset 0x%x\n", (int)offset);
118 r = 0;
119 break;
120 }
121
122 trace_pl031_read(offset, r);
123 return r;
124}
125
126static void pl031_write(void * opaque, hwaddr offset,
127 uint64_t value, unsigned size)
128{
129 PL031State *s = (PL031State *)opaque;
130
131 trace_pl031_write(offset, value);
132
133 switch (offset) {
134 case RTC_LR:
135 s->tick_offset += value - pl031_get_count(s);
136 pl031_set_alarm(s);
137 break;
138 case RTC_MR:
139 s->mr = value;
140 pl031_set_alarm(s);
141 break;
142 case RTC_IMSC:
143 s->im = value & 1;
144 pl031_update(s);
145 break;
146 case RTC_ICR:
147
148
149
150
151 s->is = 0;
152 pl031_update(s);
153 break;
154 case RTC_CR:
155
156 break;
157
158 case RTC_DR:
159 case RTC_MIS:
160 case RTC_RIS:
161 qemu_log_mask(LOG_GUEST_ERROR,
162 "pl031: write to read-only register at offset 0x%x\n",
163 (int)offset);
164 break;
165
166 default:
167 qemu_log_mask(LOG_GUEST_ERROR,
168 "pl031_write: Bad offset 0x%x\n", (int)offset);
169 break;
170 }
171}
172
173static const MemoryRegionOps pl031_ops = {
174 .read = pl031_read,
175 .write = pl031_write,
176 .endianness = DEVICE_NATIVE_ENDIAN,
177};
178
179static void pl031_init(Object *obj)
180{
181 PL031State *s = PL031(obj);
182 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
183 struct tm tm;
184
185 memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
186 sysbus_init_mmio(dev, &s->iomem);
187
188 sysbus_init_irq(dev, &s->irq);
189 qemu_get_timedate(&tm, 0);
190 s->tick_offset = mktimegm(&tm) -
191 qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
192
193 s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
194}
195
196static int pl031_pre_save(void *opaque)
197{
198 PL031State *s = opaque;
199
200
201
202 int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
203 s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
204
205 return 0;
206}
207
208static int pl031_post_load(void *opaque, int version_id)
209{
210 PL031State *s = opaque;
211
212 int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
213 s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND;
214 pl031_set_alarm(s);
215 return 0;
216}
217
218static const VMStateDescription vmstate_pl031 = {
219 .name = "pl031",
220 .version_id = 1,
221 .minimum_version_id = 1,
222 .pre_save = pl031_pre_save,
223 .post_load = pl031_post_load,
224 .fields = (VMStateField[]) {
225 VMSTATE_UINT32(tick_offset_vmstate, PL031State),
226 VMSTATE_UINT32(mr, PL031State),
227 VMSTATE_UINT32(lr, PL031State),
228 VMSTATE_UINT32(cr, PL031State),
229 VMSTATE_UINT32(im, PL031State),
230 VMSTATE_UINT32(is, PL031State),
231 VMSTATE_END_OF_LIST()
232 }
233};
234
235static void pl031_class_init(ObjectClass *klass, void *data)
236{
237 DeviceClass *dc = DEVICE_CLASS(klass);
238
239 dc->vmsd = &vmstate_pl031;
240}
241
242static const TypeInfo pl031_info = {
243 .name = TYPE_PL031,
244 .parent = TYPE_SYS_BUS_DEVICE,
245 .instance_size = sizeof(PL031State),
246 .instance_init = pl031_init,
247 .class_init = pl031_class_init,
248};
249
250static void pl031_register_types(void)
251{
252 type_register_static(&pl031_info);
253}
254
255type_init(pl031_register_types)
256