LXR qemu/hw/usb/hcd-ehci.h

   1/*
   2 * QEMU USB EHCI Emulation
   3 *
   4 * This library is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU Lesser General Public
   6 * License as published by the Free Software Foundation; either
   7 * version 2.1 of the License, or (at your option) any later version.
   8 *
   9 * This library is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12 * Lesser General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU Lesser General Public License
  15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#ifndef HW_USB_HCD_EHCI_H
  19#define HW_USB_HCD_EHCI_H
  20
  21#include "hw/hw.h"
  22#include "qemu/timer.h"
  23#include "hw/usb.h"
  24#include "sysemu/dma.h"
  25#include "sysemu/sysemu.h"
  26#include "hw/pci/pci.h"
  27#include "hw/sysbus.h"
  28
  29#ifndef EHCI_DEBUG
  30#define EHCI_DEBUG   0
  31#endif
  32
  33#if EHCI_DEBUG
  34#define DPRINTF printf
  35#else
  36#define DPRINTF(...)
  37#endif
  38
  39#define MMIO_SIZE        0x1000
  40#define CAPA_SIZE        0x10
  41
  42#define NB_PORTS         6        /* Max. Number of downstream ports */
  43
  44typedef struct EHCIPacket EHCIPacket;
  45typedef struct EHCIQueue EHCIQueue;
  46typedef struct EHCIState EHCIState;
  47
  48/*  EHCI spec version 1.0 Section 3.3
  49 */
  50typedef struct EHCIitd {
  51    uint32_t next;
  52
  53    uint32_t transact[8];
  54#define ITD_XACT_ACTIVE          (1 << 31)
  55#define ITD_XACT_DBERROR         (1 << 30)
  56#define ITD_XACT_BABBLE          (1 << 29)
  57#define ITD_XACT_XACTERR         (1 << 28)
  58#define ITD_XACT_LENGTH_MASK     0x0fff0000
  59#define ITD_XACT_LENGTH_SH       16
  60#define ITD_XACT_IOC             (1 << 15)
  61#define ITD_XACT_PGSEL_MASK      0x00007000
  62#define ITD_XACT_PGSEL_SH        12
  63#define ITD_XACT_OFFSET_MASK     0x00000fff
  64
  65    uint32_t bufptr[7];
  66#define ITD_BUFPTR_MASK          0xfffff000
  67#define ITD_BUFPTR_SH            12
  68#define ITD_BUFPTR_EP_MASK       0x00000f00
  69#define ITD_BUFPTR_EP_SH         8
  70#define ITD_BUFPTR_DEVADDR_MASK  0x0000007f
  71#define ITD_BUFPTR_DEVADDR_SH    0
  72#define ITD_BUFPTR_DIRECTION     (1 << 11)
  73#define ITD_BUFPTR_MAXPKT_MASK   0x000007ff
  74#define ITD_BUFPTR_MAXPKT_SH     0
  75#define ITD_BUFPTR_MULT_MASK     0x00000003
  76#define ITD_BUFPTR_MULT_SH       0
  77} EHCIitd;
  78
  79/*  EHCI spec version 1.0 Section 3.4
  80 */
  81typedef struct EHCIsitd {
  82    uint32_t next;                  /* Standard next link pointer */
  83    uint32_t epchar;
  84#define SITD_EPCHAR_IO              (1 << 31)
  85#define SITD_EPCHAR_PORTNUM_MASK    0x7f000000
  86#define SITD_EPCHAR_PORTNUM_SH      24
  87#define SITD_EPCHAR_HUBADD_MASK     0x007f0000
  88#define SITD_EPCHAR_HUBADDR_SH      16
  89#define SITD_EPCHAR_EPNUM_MASK      0x00000f00
  90#define SITD_EPCHAR_EPNUM_SH        8
  91#define SITD_EPCHAR_DEVADDR_MASK    0x0000007f
  92
  93    uint32_t uframe;
  94#define SITD_UFRAME_CMASK_MASK      0x0000ff00
  95#define SITD_UFRAME_CMASK_SH        8
  96#define SITD_UFRAME_SMASK_MASK      0x000000ff
  97
  98    uint32_t results;
  99#define SITD_RESULTS_IOC              (1 << 31)
 100#define SITD_RESULTS_PGSEL            (1 << 30)
 101#define SITD_RESULTS_TBYTES_MASK      0x03ff0000
 102#define SITD_RESULTS_TYBYTES_SH       16
 103#define SITD_RESULTS_CPROGMASK_MASK   0x0000ff00
 104#define SITD_RESULTS_CPROGMASK_SH     8
 105#define SITD_RESULTS_ACTIVE           (1 << 7)
 106#define SITD_RESULTS_ERR              (1 << 6)
 107#define SITD_RESULTS_DBERR            (1 << 5)
 108#define SITD_RESULTS_BABBLE           (1 << 4)
 109#define SITD_RESULTS_XACTERR          (1 << 3)
 110#define SITD_RESULTS_MISSEDUF         (1 << 2)
 111#define SITD_RESULTS_SPLITXSTATE      (1 << 1)
 112
 113    uint32_t bufptr[2];
 114#define SITD_BUFPTR_MASK              0xfffff000
 115#define SITD_BUFPTR_CURROFF_MASK      0x00000fff
 116#define SITD_BUFPTR_TPOS_MASK         0x00000018
 117#define SITD_BUFPTR_TPOS_SH           3
 118#define SITD_BUFPTR_TCNT_MASK         0x00000007
 119
 120    uint32_t backptr;                 /* Standard next link pointer */
 121} EHCIsitd;
 122
 123/*  EHCI spec version 1.0 Section 3.5
 124 */
 125typedef struct EHCIqtd {
 126    uint32_t next;                    /* Standard next link pointer */
 127    uint32_t altnext;                 /* Standard next link pointer */
 128    uint32_t token;
 129#define QTD_TOKEN_DTOGGLE             (1 << 31)
 130#define QTD_TOKEN_TBYTES_MASK         0x7fff0000
 131#define QTD_TOKEN_TBYTES_SH           16
 132#define QTD_TOKEN_IOC                 (1 << 15)
 133#define QTD_TOKEN_CPAGE_MASK          0x00007000
 134#define QTD_TOKEN_CPAGE_SH            12
 135#define QTD_TOKEN_CERR_MASK           0x00000c00
 136#define QTD_TOKEN_CERR_SH             10
 137#define QTD_TOKEN_PID_MASK            0x00000300
 138#define QTD_TOKEN_PID_SH              8
 139#define QTD_TOKEN_ACTIVE              (1 << 7)
 140#define QTD_TOKEN_HALT                (1 << 6)
 141#define QTD_TOKEN_DBERR               (1 << 5)
 142#define QTD_TOKEN_BABBLE              (1 << 4)
 143#define QTD_TOKEN_XACTERR             (1 << 3)
 144#define QTD_TOKEN_MISSEDUF            (1 << 2)
 145#define QTD_TOKEN_SPLITXSTATE         (1 << 1)
 146#define QTD_TOKEN_PING                (1 << 0)
 147
 148    uint32_t bufptr[5];               /* Standard buffer pointer */
 149#define QTD_BUFPTR_MASK               0xfffff000
 150#define QTD_BUFPTR_SH                 12
 151} EHCIqtd;
 152
 153/*  EHCI spec version 1.0 Section 3.6
 154 */
 155typedef struct EHCIqh {
 156    uint32_t next;                    /* Standard next link pointer */
 157
 158    /* endpoint characteristics */
 159    uint32_t epchar;
 160#define QH_EPCHAR_RL_MASK             0xf0000000
 161#define QH_EPCHAR_RL_SH               28
 162#define QH_EPCHAR_C                   (1 << 27)
 163#define QH_EPCHAR_MPLEN_MASK          0x07FF0000
 164#define QH_EPCHAR_MPLEN_SH            16
 165#define QH_EPCHAR_H                   (1 << 15)
 166#define QH_EPCHAR_DTC                 (1 << 14)
 167#define QH_EPCHAR_EPS_MASK            0x00003000
 168#define QH_EPCHAR_EPS_SH              12
 169#define EHCI_QH_EPS_FULL              0
 170#define EHCI_QH_EPS_LOW               1
 171#define EHCI_QH_EPS_HIGH              2
 172#define EHCI_QH_EPS_RESERVED          3
 173
 174#define QH_EPCHAR_EP_MASK             0x00000f00
 175#define QH_EPCHAR_EP_SH               8
 176#define QH_EPCHAR_I                   (1 << 7)
 177#define QH_EPCHAR_DEVADDR_MASK        0x0000007f
 178#define QH_EPCHAR_DEVADDR_SH          0
 179
 180    /* endpoint capabilities */
 181    uint32_t epcap;
 182#define QH_EPCAP_MULT_MASK            0xc0000000
 183#define QH_EPCAP_MULT_SH              30
 184#define QH_EPCAP_PORTNUM_MASK         0x3f800000
 185#define QH_EPCAP_PORTNUM_SH           23
 186#define QH_EPCAP_HUBADDR_MASK         0x007f0000
 187#define QH_EPCAP_HUBADDR_SH           16
 188#define QH_EPCAP_CMASK_MASK           0x0000ff00
 189#define QH_EPCAP_CMASK_SH             8
 190#define QH_EPCAP_SMASK_MASK           0x000000ff
 191#define QH_EPCAP_SMASK_SH             0
 192
 193    uint32_t current_qtd;             /* Standard next link pointer */
 194    uint32_t next_qtd;                /* Standard next link pointer */
 195    uint32_t altnext_qtd;
 196#define QH_ALTNEXT_NAKCNT_MASK        0x0000001e
 197#define QH_ALTNEXT_NAKCNT_SH          1
 198
 199    uint32_t token;                   /* Same as QTD token */
 200    uint32_t bufptr[5];               /* Standard buffer pointer */
 201#define BUFPTR_CPROGMASK_MASK         0x000000ff
 202#define BUFPTR_FRAMETAG_MASK          0x0000001f
 203#define BUFPTR_SBYTES_MASK            0x00000fe0
 204#define BUFPTR_SBYTES_SH              5
 205} EHCIqh;
 206
 207/*  EHCI spec version 1.0 Section 3.7
 208 */
 209typedef struct EHCIfstn {
 210    uint32_t next;                    /* Standard next link pointer */
 211    uint32_t backptr;                 /* Standard next link pointer */
 212} EHCIfstn;
 213
 214enum async_state {
 215    EHCI_ASYNC_NONE = 0,
 216    EHCI_ASYNC_INITIALIZED,
 217    EHCI_ASYNC_INFLIGHT,
 218    EHCI_ASYNC_FINISHED,
 219};
 220
 221struct EHCIPacket {
 222    EHCIQueue *queue;
 223    QTAILQ_ENTRY(EHCIPacket) next;
 224
 225    EHCIqtd qtd;           /* copy of current QTD (being worked on) */
 226    uint32_t qtdaddr;      /* address QTD read from                 */
 227
 228    USBPacket packet;
 229    QEMUSGList sgl;
 230    int pid;
 231    enum async_state async;
 232};
 233
 234struct EHCIQueue {
 235    EHCIState *ehci;
 236    QTAILQ_ENTRY(EHCIQueue) next;
 237    uint32_t seen;
 238    uint64_t ts;
 239    int async;
 240    int transact_ctr;
 241
 242    /* cached data from guest - needs to be flushed
 243     * when guest removes an entry (doorbell, handshake sequence)
 244     */
 245    EHCIqh qh;             /* copy of current QH (being worked on) */
 246    uint32_t qhaddr;       /* address QH read from                 */
 247    uint32_t qtdaddr;      /* address QTD read from                */
 248    int last_pid;          /* pid of last packet executed          */
 249    USBDevice *dev;
 250    QTAILQ_HEAD(, EHCIPacket) packets;
 251};
 252
 253typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
 254
 255struct EHCIState {
 256    USBBus bus;
 257    DeviceState *device;
 258    qemu_irq irq;
 259    MemoryRegion mem;
 260    AddressSpace *as;
 261    MemoryRegion mem_caps;
 262    MemoryRegion mem_opreg;
 263    MemoryRegion mem_ports;
 264    int companion_count;
 265    bool companion_enable;
 266    uint16_t capsbase;
 267    uint16_t opregbase;
 268    uint16_t portscbase;
 269    uint16_t portnr;
 270
 271    /* properties */
 272    uint32_t maxframes;
 273
 274    /*
 275     *  EHCI spec version 1.0 Section 2.3
 276     *  Host Controller Operational Registers
 277     */
 278    uint8_t caps[CAPA_SIZE];
 279    union {
 280        uint32_t opreg[0x44/sizeof(uint32_t)];
 281        struct {
 282            uint32_t usbcmd;
 283            uint32_t usbsts;
 284            uint32_t usbintr;
 285            uint32_t frindex;
 286            uint32_t ctrldssegment;
 287            uint32_t periodiclistbase;
 288            uint32_t asynclistaddr;
 289            uint32_t notused[9];
 290            uint32_t configflag;
 291        };
 292    };
 293    uint32_t portsc[NB_PORTS];
 294
 295    /*
 296     *  Internal states, shadow registers, etc
 297     */
 298    QEMUTimer *frame_timer;
 299    QEMUBH *async_bh;
 300    bool working;
 301    uint32_t astate;         /* Current state in asynchronous schedule */
 302    uint32_t pstate;         /* Current state in periodic schedule     */
 303    USBPort ports[NB_PORTS];
 304    USBPort *companion_ports[NB_PORTS];
 305    uint32_t usbsts_pending;
 306    uint32_t usbsts_frindex;
 307    EHCIQueueHead aqueues;
 308    EHCIQueueHead pqueues;
 309
 310    /* which address to look at next */
 311    uint32_t a_fetch_addr;
 312    uint32_t p_fetch_addr;
 313
 314    USBPacket ipacket;
 315    QEMUSGList isgl;
 316
 317    uint64_t last_run_ns;
 318    uint32_t async_stepdown;
 319    uint32_t periodic_sched_active;
 320    bool int_req_by_async;
 321    VMChangeStateEntry *vmstate;
 322};
 323
 324extern const VMStateDescription vmstate_ehci;
 325
 326void usb_ehci_init(EHCIState *s, DeviceState *dev);
 327void usb_ehci_finalize(EHCIState *s);
 328void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp);
 329void usb_ehci_unrealize(EHCIState *s, DeviceState *dev, Error **errp);
 330void ehci_reset(void *opaque);
 331
 332#define TYPE_PCI_EHCI "pci-ehci-usb"
 333#define PCI_EHCI(obj) OBJECT_CHECK(EHCIPCIState, (obj), TYPE_PCI_EHCI)
 334
 335typedef struct EHCIPCIState {
 336    /*< private >*/
 337    PCIDevice pcidev;
 338    /*< public >*/
 339
 340    EHCIState ehci;
 341} EHCIPCIState;
 342
 343
 344#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
 345#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
 346#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
 347#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
 348#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
 349#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
 350
 351#define SYS_BUS_EHCI(obj) \
 352    OBJECT_CHECK(EHCISysBusState, (obj), TYPE_SYS_BUS_EHCI)
 353#define SYS_BUS_EHCI_CLASS(class) \
 354    OBJECT_CLASS_CHECK(SysBusEHCIClass, (class), TYPE_SYS_BUS_EHCI)
 355#define SYS_BUS_EHCI_GET_CLASS(obj) \
 356    OBJECT_GET_CLASS(SysBusEHCIClass, (obj), TYPE_SYS_BUS_EHCI)
 357
 358typedef struct EHCISysBusState {
 359    /*< private >*/
 360    SysBusDevice parent_obj;
 361    /*< public >*/
 362
 363    EHCIState ehci;
 364} EHCISysBusState;
 365
 366typedef struct SysBusEHCIClass {
 367    /*< private >*/
 368    SysBusDeviceClass parent_class;
 369    /*< public >*/
 370
 371    uint16_t capsbase;
 372    uint16_t opregbase;
 373    uint16_t portscbase;
 374    uint16_t portnr;
 375} SysBusEHCIClass;
 376
 377#define FUSBH200_EHCI(obj) \
 378    OBJECT_CHECK(FUSBH200EHCIState, (obj), TYPE_FUSBH200_EHCI)
 379
 380typedef struct FUSBH200EHCIState {
 381    /*< private >*/
 382    EHCISysBusState parent_obj;
 383    /*< public >*/
 384
 385    MemoryRegion mem_vendor;
 386} FUSBH200EHCIState;
 387
 388#endif
 389