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15#ifndef HW_PL011_H
16#define HW_PL011_H
17
18#include "hw/sysbus.h"
19#include "chardev/char-fe.h"
20
21#define TYPE_PL011 "pl011"
22#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)
23
24
25#define TYPE_PL011_LUMINARY "pl011_luminary"
26
27typedef struct PL011State {
28 SysBusDevice parent_obj;
29
30 MemoryRegion iomem;
31 uint32_t readbuff;
32 uint32_t flags;
33 uint32_t lcr;
34 uint32_t rsr;
35 uint32_t cr;
36 uint32_t dmacr;
37 uint32_t int_enabled;
38 uint32_t int_level;
39 uint32_t read_fifo[16];
40 uint32_t ilpr;
41 uint32_t ibrd;
42 uint32_t fbrd;
43 uint32_t ifl;
44 int read_pos;
45 int read_count;
46 int read_trigger;
47 CharBackend chr;
48 qemu_irq irq[6];
49 const unsigned char *id;
50} PL011State;
51
52static inline DeviceState *pl011_create(hwaddr addr,
53 qemu_irq irq,
54 Chardev *chr)
55{
56 DeviceState *dev;
57 SysBusDevice *s;
58
59 dev = qdev_create(NULL, "pl011");
60 s = SYS_BUS_DEVICE(dev);
61 qdev_prop_set_chr(dev, "chardev", chr);
62 qdev_init_nofail(dev);
63 sysbus_mmio_map(s, 0, addr);
64 sysbus_connect_irq(s, 0, irq);
65
66 return dev;
67}
68
69static inline DeviceState *pl011_luminary_create(hwaddr addr,
70 qemu_irq irq,
71 Chardev *chr)
72{
73 DeviceState *dev;
74 SysBusDevice *s;
75
76 dev = qdev_create(NULL, "pl011_luminary");
77 s = SYS_BUS_DEVICE(dev);
78 qdev_prop_set_chr(dev, "chardev", chr);
79 qdev_init_nofail(dev);
80 sysbus_mmio_map(s, 0, addr);
81 sysbus_connect_irq(s, 0, irq);
82
83 return dev;
84}
85
86#endif
87