LXR qemu/include/hw/i386/pc.h

   1#ifndef HW_PC_H
   2#define HW_PC_H
   3
   4#include "qemu-common.h"
   5#include "exec/memory.h"
   6#include "hw/boards.h"
   7#include "hw/isa/isa.h"
   8#include "hw/block/fdc.h"
   9#include "hw/block/flash.h"
  10#include "net/net.h"
  11#include "hw/i386/ioapic.h"
  12
  13#include "qemu/range.h"
  14#include "qemu/bitmap.h"
  15#include "sysemu/sysemu.h"
  16#include "hw/pci/pci.h"
  17#include "hw/mem/pc-dimm.h"
  18#include "hw/mem/nvdimm.h"
  19#include "hw/acpi/acpi_dev_interface.h"
  20
  21#define HPET_INTCAP "hpet-intcap"
  22
  23/**
  24 * PCMachineState:
  25 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
  26 * @boot_cpus: number of present VCPUs
  27 */
  28struct PCMachineState {
  29    /*< private >*/
  30    MachineState parent_obj;
  31
  32    /* <public> */
  33
  34    /* State for other subsystems/APIs: */
  35    Notifier machine_done;
  36
  37    /* Pointers to devices and objects: */
  38    HotplugHandler *acpi_dev;
  39    ISADevice *rtc;
  40    PCIBus *bus;
  41    FWCfgState *fw_cfg;
  42    qemu_irq *gsi;
  43    PFlashCFI01 *flash[2];
  44
  45    /* Configuration options: */
  46    uint64_t max_ram_below_4g;
  47    OnOffAuto vmport;
  48    OnOffAuto smm;
  49
  50    bool acpi_build_enabled;
  51    bool smbus_enabled;
  52    bool sata_enabled;
  53    bool pit_enabled;
  54
  55    /* RAM information (sizes, addresses, configuration): */
  56    ram_addr_t below_4g_mem_size, above_4g_mem_size;
  57
  58    /* CPU and apic information: */
  59    bool apic_xrupt_override;
  60    unsigned apic_id_limit;
  61    uint16_t boot_cpus;
  62
  63    /* NUMA information: */
  64    uint64_t numa_nodes;
  65    uint64_t *node_mem;
  66
  67    /* Address space used by IOAPIC device. All IOAPIC interrupts
  68     * will be translated to MSI messages in the address space. */
  69    AddressSpace *ioapic_as;
  70};
  71
  72#define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
  73#define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
  74#define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
  75#define PC_MACHINE_VMPORT           "vmport"
  76#define PC_MACHINE_SMM              "smm"
  77#define PC_MACHINE_SMBUS            "smbus"
  78#define PC_MACHINE_SATA             "sata"
  79#define PC_MACHINE_PIT              "pit"
  80
  81/**
  82 * PCMachineClass:
  83 *
  84 * Compat fields:
  85 *
  86 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
  87 *                        backend's alignment value if provided
  88 * @acpi_data_size: Size of the chunk of memory at the top of RAM
  89 *                  for the BIOS ACPI tables and other BIOS
  90 *                  datastructures.
  91 * @gigabyte_align: Make sure that guest addresses aligned at
  92 *                  1Gbyte boundaries get mapped to host
  93 *                  addresses aligned at 1Gbyte boundaries. This
  94 *                  way we can use 1GByte pages in the host.
  95 *
  96 */
  97typedef struct PCMachineClass {
  98    /*< private >*/
  99    MachineClass parent_class;
 100
 101    /*< public >*/
 102
 103    /* Device configuration: */
 104    bool pci_enabled;
 105    bool kvmclock_enabled;
 106    const char *default_nic_model;
 107
 108    /* Compat options: */
 109
 110    /* ACPI compat: */
 111    bool has_acpi_build;
 112    bool rsdp_in_ram;
 113    int legacy_acpi_table_size;
 114    unsigned acpi_data_size;
 115
 116    /* SMBIOS compat: */
 117    bool smbios_defaults;
 118    bool smbios_legacy_mode;
 119    bool smbios_uuid_encoded;
 120
 121    /* RAM / address space compat: */
 122    bool gigabyte_align;
 123    bool has_reserved_memory;
 124    bool enforce_aligned_dimm;
 125    bool broken_reserved_end;
 126
 127    /* TSC rate migration: */
 128    bool save_tsc_khz;
 129    /* generate legacy CPU hotplug AML */
 130    bool legacy_cpu_hotplug;
 131
 132    /* use DMA capable linuxboot option rom */
 133    bool linuxboot_dma_enabled;
 134
 135    /* use PVH to load kernels that support this feature */
 136    bool pvh_enabled;
 137} PCMachineClass;
 138
 139#define TYPE_PC_MACHINE "generic-pc-machine"
 140#define PC_MACHINE(obj) \
 141    OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
 142#define PC_MACHINE_GET_CLASS(obj) \
 143    OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
 144#define PC_MACHINE_CLASS(klass) \
 145    OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
 146
 147/* i8259.c */
 148
 149extern DeviceState *isa_pic;
 150qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
 151qemu_irq *kvm_i8259_init(ISABus *bus);
 152int pic_read_irq(DeviceState *d);
 153int pic_get_output(DeviceState *d);
 154
 155/* ioapic.c */
 156
 157/* Global System Interrupts */
 158
 159#define GSI_NUM_PINS IOAPIC_NUM_PINS
 160
 161typedef struct GSIState {
 162    qemu_irq i8259_irq[ISA_NUM_IRQS];
 163    qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 164} GSIState;
 165
 166void gsi_handler(void *opaque, int n, int level);
 167
 168/* vmport.c */
 169#define TYPE_VMPORT "vmport"
 170typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
 171
 172static inline void vmport_init(ISABus *bus)
 173{
 174    isa_create_simple(bus, TYPE_VMPORT);
 175}
 176
 177void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
 178void vmmouse_get_data(uint32_t *data);
 179void vmmouse_set_data(const uint32_t *data);
 180
 181/* pc.c */
 182extern int fd_bootchk;
 183
 184bool pc_machine_is_smm_enabled(PCMachineState *pcms);
 185void pc_register_ferr_irq(qemu_irq irq);
 186void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
 187
 188void pc_cpus_init(PCMachineState *pcms);
 189void pc_hot_add_cpu(const int64_t id, Error **errp);
 190
 191void pc_guest_info_init(PCMachineState *pcms);
 192
 193#define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
 194#define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
 195#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
 196#define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
 197#define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
 198#define PCI_HOST_BELOW_4G_MEM_SIZE     "below-4g-mem-size"
 199#define PCI_HOST_ABOVE_4G_MEM_SIZE     "above-4g-mem-size"
 200
 201
 202void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
 203                            MemoryRegion *pci_address_space);
 204
 205void xen_load_linux(PCMachineState *pcms);
 206void pc_memory_init(PCMachineState *pcms,
 207                    MemoryRegion *system_memory,
 208                    MemoryRegion *rom_memory,
 209                    MemoryRegion **ram_memory);
 210uint64_t pc_pci_hole64_start(void);
 211qemu_irq pc_allocate_cpu_irq(void);
 212DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
 213void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
 214                          ISADevice **rtc_state,
 215                          bool create_fdctrl,
 216                          bool no_vmport,
 217                          bool has_pit,
 218                          uint32_t hpet_irqs);
 219void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
 220void pc_cmos_init(PCMachineState *pcms,
 221                  BusState *ide0, BusState *ide1,
 222                  ISADevice *s);
 223void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
 224void pc_pci_device_init(PCIBus *pci_bus);
 225
 226typedef void (*cpu_set_smm_t)(int smm, void *arg);
 227
 228void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 229
 230ISADevice *pc_find_fdc0(void);
 231int cmos_get_fd_drive_type(FloppyDriveType fd0);
 232
 233#define FW_CFG_IO_BASE     0x510
 234
 235#define PORT92_A20_LINE "a20"
 236
 237/* acpi_piix.c */
 238
 239I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 240                      qemu_irq sci_irq, qemu_irq smi_irq,
 241                      int smm_enabled, DeviceState **piix4_pm);
 242
 243/* hpet.c */
 244extern int no_hpet;
 245
 246/* piix_pci.c */
 247struct PCII440FXState;
 248typedef struct PCII440FXState PCII440FXState;
 249
 250#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
 251#define TYPE_I440FX_PCI_DEVICE "i440FX"
 252
 253#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 254
 255/*
 256 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
 257 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
 258 */
 259#define RCR_IOPORT 0xcf9
 260
 261PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 262                    PCII440FXState **pi440fx_state, int *piix_devfn,
 263                    ISABus **isa_bus, qemu_irq *pic,
 264                    MemoryRegion *address_space_mem,
 265                    MemoryRegion *address_space_io,
 266                    ram_addr_t ram_size,
 267                    ram_addr_t below_4g_mem_size,
 268                    ram_addr_t above_4g_mem_size,
 269                    MemoryRegion *pci_memory,
 270                    MemoryRegion *ram_memory);
 271
 272PCIBus *find_i440fx(void);
 273/* piix4.c */
 274extern PCIDevice *piix4_dev;
 275int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 276
 277/* pc_sysfw.c */
 278void pc_system_flash_create(PCMachineState *pcms);
 279void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
 280
 281/* acpi-build.c */
 282void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
 283                       const CPUArchIdList *apic_ids, GArray *entry);
 284
 285/* e820 types */
 286#define E820_RAM        1
 287#define E820_RESERVED   2
 288#define E820_ACPI       3
 289#define E820_NVS        4
 290#define E820_UNUSABLE   5
 291
 292int e820_add_entry(uint64_t, uint64_t, uint32_t);
 293int e820_get_num_entries(void);
 294bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
 295
 296extern GlobalProperty pc_compat_3_1[];
 297extern const size_t pc_compat_3_1_len;
 298
 299extern GlobalProperty pc_compat_3_0[];
 300extern const size_t pc_compat_3_0_len;
 301
 302extern GlobalProperty pc_compat_2_12[];
 303extern const size_t pc_compat_2_12_len;
 304
 305extern GlobalProperty pc_compat_2_11[];
 306extern const size_t pc_compat_2_11_len;
 307
 308extern GlobalProperty pc_compat_2_10[];
 309extern const size_t pc_compat_2_10_len;
 310
 311extern GlobalProperty pc_compat_2_9[];
 312extern const size_t pc_compat_2_9_len;
 313
 314extern GlobalProperty pc_compat_2_8[];
 315extern const size_t pc_compat_2_8_len;
 316
 317extern GlobalProperty pc_compat_2_7[];
 318extern const size_t pc_compat_2_7_len;
 319
 320extern GlobalProperty pc_compat_2_6[];
 321extern const size_t pc_compat_2_6_len;
 322
 323extern GlobalProperty pc_compat_2_5[];
 324extern const size_t pc_compat_2_5_len;
 325
 326extern GlobalProperty pc_compat_2_4[];
 327extern const size_t pc_compat_2_4_len;
 328
 329extern GlobalProperty pc_compat_2_3[];
 330extern const size_t pc_compat_2_3_len;
 331
 332extern GlobalProperty pc_compat_2_2[];
 333extern const size_t pc_compat_2_2_len;
 334
 335extern GlobalProperty pc_compat_2_1[];
 336extern const size_t pc_compat_2_1_len;
 337
 338extern GlobalProperty pc_compat_2_0[];
 339extern const size_t pc_compat_2_0_len;
 340
 341extern GlobalProperty pc_compat_1_7[];
 342extern const size_t pc_compat_1_7_len;
 343
 344extern GlobalProperty pc_compat_1_6[];
 345extern const size_t pc_compat_1_6_len;
 346
 347extern GlobalProperty pc_compat_1_5[];
 348extern const size_t pc_compat_1_5_len;
 349
 350extern GlobalProperty pc_compat_1_4[];
 351extern const size_t pc_compat_1_4_len;
 352
 353/* Helper for setting model-id for CPU models that changed model-id
 354 * depending on QEMU versions up to QEMU 2.4.
 355 */
 356#define PC_CPU_MODEL_IDS(v) \
 357    { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
 358    { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
 359    { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
 360
 361#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
 362    static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
 363    { \
 364        MachineClass *mc = MACHINE_CLASS(oc); \
 365        optsfn(mc); \
 366        mc->init = initfn; \
 367    } \
 368    static const TypeInfo pc_machine_type_##suffix = { \
 369        .name       = namestr TYPE_MACHINE_SUFFIX, \
 370        .parent     = TYPE_PC_MACHINE, \
 371        .class_init = pc_machine_##suffix##_class_init, \
 372    }; \
 373    static void pc_machine_init_##suffix(void) \
 374    { \
 375        type_register(&pc_machine_type_##suffix); \
 376    } \
 377    type_init(pc_machine_init_##suffix)
 378
 379extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
 380#endif
 381