1#ifndef HW_SPAPR_H
2#define HW_SPAPR_H
3
4#include "qemu/units.h"
5#include "sysemu/dma.h"
6#include "hw/boards.h"
7#include "hw/ppc/spapr_drc.h"
8#include "hw/mem/pc-dimm.h"
9#include "hw/ppc/spapr_ovec.h"
10#include "hw/ppc/spapr_irq.h"
11#include "hw/ppc/spapr_xive.h"
12#include "hw/ppc/xics.h"
13
14struct SpaprVioBus;
15struct SpaprPhbState;
16struct SpaprNvram;
17
18typedef struct SpaprEventLogEntry SpaprEventLogEntry;
19typedef struct SpaprEventSource SpaprEventSource;
20typedef struct SpaprPendingHpt SpaprPendingHpt;
21
22#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
23#define SPAPR_ENTRY_POINT 0x100
24
25#define SPAPR_TIMEBASE_FREQ 512000000ULL
26
27#define TYPE_SPAPR_RTC "spapr-rtc"
28
29#define SPAPR_RTC(obj) \
30 OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC)
31
32typedef struct SpaprRtcState SpaprRtcState;
33struct SpaprRtcState {
34
35 DeviceState parent_obj;
36 int64_t ns_offset;
37};
38
39typedef struct SpaprDimmState SpaprDimmState;
40typedef struct SpaprMachineClass SpaprMachineClass;
41
42#define TYPE_SPAPR_MACHINE "spapr-machine"
43#define SPAPR_MACHINE(obj) \
44 OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE)
45#define SPAPR_MACHINE_GET_CLASS(obj) \
46 OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE)
47#define SPAPR_MACHINE_CLASS(klass) \
48 OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE)
49
50typedef enum {
51 SPAPR_RESIZE_HPT_DEFAULT = 0,
52 SPAPR_RESIZE_HPT_DISABLED,
53 SPAPR_RESIZE_HPT_ENABLED,
54 SPAPR_RESIZE_HPT_REQUIRED,
55} SpaprResizeHpt;
56
57
58
59
60
61
62#define SPAPR_CAP_HTM 0x00
63
64#define SPAPR_CAP_VSX 0x01
65
66#define SPAPR_CAP_DFP 0x02
67
68#define SPAPR_CAP_CFPC 0x03
69
70#define SPAPR_CAP_SBBC 0x04
71
72#define SPAPR_CAP_IBS 0x05
73
74#define SPAPR_CAP_HPT_MAXPAGESIZE 0x06
75
76#define SPAPR_CAP_NESTED_KVM_HV 0x07
77
78#define SPAPR_CAP_LARGE_DECREMENTER 0x08
79
80#define SPAPR_CAP_CCF_ASSIST 0x09
81
82#define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1)
83
84
85
86
87
88#define SPAPR_CAP_OFF 0x00
89#define SPAPR_CAP_ON 0x01
90
91
92
93
94#define SPAPR_CAP_BROKEN 0x00
95#define SPAPR_CAP_WORKAROUND 0x01
96#define SPAPR_CAP_FIXED 0x02
97
98#define SPAPR_CAP_FIXED_IBS 0x02
99#define SPAPR_CAP_FIXED_CCD 0x03
100#define SPAPR_CAP_FIXED_NA 0x10
101
102typedef struct SpaprCapabilities SpaprCapabilities;
103struct SpaprCapabilities {
104 uint8_t caps[SPAPR_CAP_NUM];
105};
106
107
108
109
110struct SpaprMachineClass {
111
112 MachineClass parent_class;
113
114
115 bool dr_lmb_enabled;
116 bool dr_phb_enabled;
117 bool update_dt_enabled;
118 bool use_ohci_by_default;
119 bool pre_2_10_has_unused_icps;
120 bool legacy_irq_allocation;
121 bool broken_host_serial_model;
122
123 void (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
124 uint64_t *buid, hwaddr *pio,
125 hwaddr *mmio32, hwaddr *mmio64,
126 unsigned n_dma, uint32_t *liobns, Error **errp);
127 SpaprResizeHpt resize_hpt_default;
128 SpaprCapabilities default_caps;
129 SpaprIrq *irq;
130};
131
132
133
134
135struct SpaprMachineState {
136
137 MachineState parent_obj;
138
139 struct SpaprVioBus *vio_bus;
140 QLIST_HEAD(, SpaprPhbState) phbs;
141 struct SpaprNvram *nvram;
142 ICSState *ics;
143 SpaprRtcState rtc;
144
145 SpaprResizeHpt resize_hpt;
146 void *htab;
147 uint32_t htab_shift;
148 uint64_t patb_entry;
149 SpaprPendingHpt *pending_hpt;
150
151 hwaddr rma_size;
152 int vrma_adjust;
153 ssize_t rtas_size;
154 void *rtas_blob;
155 uint32_t fdt_size;
156 uint32_t fdt_initial_size;
157 void *fdt_blob;
158 long kernel_size;
159 bool kernel_le;
160 uint32_t initrd_base;
161 long initrd_size;
162 uint64_t rtc_offset;
163 struct PPCTimebase tb;
164 bool has_graphics;
165 uint32_t vsmt;
166
167 Notifier epow_notifier;
168 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
169 bool use_hotplug_event_source;
170 SpaprEventSource *event_sources;
171
172
173 bool cas_reboot;
174 bool cas_legacy_guest_workaround;
175 SpaprOptionVector *ov5;
176 SpaprOptionVector *ov5_cas;
177 uint32_t max_compat_pvr;
178
179
180 int htab_save_index;
181 bool htab_first_pass;
182 int htab_fd;
183
184
185
186
187 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
188
189
190 char *kvm_type;
191 char *host_model;
192 char *host_serial;
193
194 int32_t irq_map_nr;
195 unsigned long *irq_map;
196 SpaprXive *xive;
197 SpaprIrq *irq;
198 qemu_irq *qirqs;
199
200 bool cmd_line_caps[SPAPR_CAP_NUM];
201 SpaprCapabilities def, eff, mig;
202};
203
204#define H_SUCCESS 0
205#define H_BUSY 1
206#define H_CLOSED 2
207#define H_NOT_AVAILABLE 3
208#define H_CONSTRAINED 4
209#define H_PARTIAL 5
210#define H_IN_PROGRESS 14
211#define H_PAGE_REGISTERED 15
212#define H_PARTIAL_STORE 16
213#define H_PENDING 17
214#define H_CONTINUE 18
215#define H_LONG_BUSY_START_RANGE 9900
216#define H_LONG_BUSY_ORDER_1_MSEC 9900
217
218#define H_LONG_BUSY_ORDER_10_MSEC 9901
219
220#define H_LONG_BUSY_ORDER_100_MSEC 9902
221
222#define H_LONG_BUSY_ORDER_1_SEC 9903
223
224#define H_LONG_BUSY_ORDER_10_SEC 9904
225
226#define H_LONG_BUSY_ORDER_100_SEC 9905
227
228#define H_LONG_BUSY_END_RANGE 9905
229#define H_HARDWARE -1
230#define H_FUNCTION -2
231#define H_PRIVILEGE -3
232#define H_PARAMETER -4
233#define H_BAD_MODE -5
234#define H_PTEG_FULL -6
235#define H_NOT_FOUND -7
236#define H_RESERVED_DABR -8
237#define H_NO_MEM -9
238#define H_AUTHORITY -10
239#define H_PERMISSION -11
240#define H_DROPPED -12
241#define H_SOURCE_PARM -13
242#define H_DEST_PARM -14
243#define H_REMOTE_PARM -15
244#define H_RESOURCE -16
245#define H_ADAPTER_PARM -17
246#define H_RH_PARM -18
247#define H_RCQ_PARM -19
248#define H_SCQ_PARM -20
249#define H_EQ_PARM -21
250#define H_RT_PARM -22
251#define H_ST_PARM -23
252#define H_SIGT_PARM -24
253#define H_TOKEN_PARM -25
254#define H_MLENGTH_PARM -27
255#define H_MEM_PARM -28
256#define H_MEM_ACCESS_PARM -29
257#define H_ATTR_PARM -30
258#define H_PORT_PARM -31
259#define H_MCG_PARM -32
260#define H_VL_PARM -33
261#define H_TSIZE_PARM -34
262#define H_TRACE_PARM -35
263
264#define H_MASK_PARM -37
265#define H_MCG_FULL -38
266#define H_ALIAS_EXIST -39
267#define H_P_COUNTER -40
268#define H_TABLE_FULL -41
269#define H_ALT_TABLE -42
270#define H_MR_CONDITION -43
271#define H_NOT_ENOUGH_RESOURCES -44
272#define H_R_STATE -45
273#define H_RESCINDEND -46
274#define H_P2 -55
275#define H_P3 -56
276#define H_P4 -57
277#define H_P5 -58
278#define H_P6 -59
279#define H_P7 -60
280#define H_P8 -61
281#define H_P9 -62
282#define H_UNSUPPORTED_FLAG -256
283#define H_MULTI_THREADS_ACTIVE -9005
284
285
286
287
288
289
290
291
292
293
294#define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
295 && (x <= H_LONG_BUSY_END_RANGE))
296
297
298#define H_LARGE_PAGE (1ULL<<(63-16))
299#define H_EXACT (1ULL<<(63-24))
300#define H_R_XLATE (1ULL<<(63-25))
301#define H_READ_4 (1ULL<<(63-26))
302#define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
303#define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
304#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
305#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
306#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
307#define H_AVPN (1ULL<<(63-32))
308#define H_ANDCOND (1ULL<<(63-33))
309#define H_ICACHE_INVALIDATE (1ULL<<(63-40))
310#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))
311#define H_ZERO_PAGE (1ULL<<(63-48))
312#define H_COPY_PAGE (1ULL<<(63-49))
313#define H_N (1ULL<<(63-61))
314#define H_PP1 (1ULL<<(63-62))
315#define H_PP2 (1ULL<<(63-63))
316
317
318#define H_SET_MODE_RESOURCE_SET_CIABR 1
319#define H_SET_MODE_RESOURCE_SET_DAWR 2
320#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
321#define H_SET_MODE_RESOURCE_LE 4
322
323
324#define H_SET_MODE_ENDIAN_BIG 0
325#define H_SET_MODE_ENDIAN_LITTLE 1
326
327
328#define H_VASI_INVALID 0
329#define H_VASI_ENABLED 1
330#define H_VASI_ABORTED 2
331#define H_VASI_SUSPENDING 3
332#define H_VASI_SUSPENDED 4
333#define H_VASI_RESUMED 5
334#define H_VASI_COMPLETED 6
335
336
337#define H_DABRX_HYPERVISOR (1ULL<<(63-61))
338#define H_DABRX_KERNEL (1ULL<<(63-62))
339#define H_DABRX_USER (1ULL<<(63-63))
340
341
342#define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
343#define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
344#define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
345#define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
346#define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
347#define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
348#define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
349#define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
350#define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
351#define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
352#define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
353#define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
354#define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5)
355
356
357#define H_CB_ALIGNMENT 4096
358
359
360#define H_REMOVE 0x04
361#define H_ENTER 0x08
362#define H_READ 0x0c
363#define H_CLEAR_MOD 0x10
364#define H_CLEAR_REF 0x14
365#define H_PROTECT 0x18
366#define H_GET_TCE 0x1c
367#define H_PUT_TCE 0x20
368#define H_SET_SPRG0 0x24
369#define H_SET_DABR 0x28
370#define H_PAGE_INIT 0x2c
371#define H_SET_ASR 0x30
372#define H_ASR_ON 0x34
373#define H_ASR_OFF 0x38
374#define H_LOGICAL_CI_LOAD 0x3c
375#define H_LOGICAL_CI_STORE 0x40
376#define H_LOGICAL_CACHE_LOAD 0x44
377#define H_LOGICAL_CACHE_STORE 0x48
378#define H_LOGICAL_ICBI 0x4c
379#define H_LOGICAL_DCBF 0x50
380#define H_GET_TERM_CHAR 0x54
381#define H_PUT_TERM_CHAR 0x58
382#define H_REAL_TO_LOGICAL 0x5c
383#define H_HYPERVISOR_DATA 0x60
384#define H_EOI 0x64
385#define H_CPPR 0x68
386#define H_IPI 0x6c
387#define H_IPOLL 0x70
388#define H_XIRR 0x74
389#define H_PERFMON 0x7c
390#define H_MIGRATE_DMA 0x78
391#define H_REGISTER_VPA 0xDC
392#define H_CEDE 0xE0
393#define H_CONFER 0xE4
394#define H_PROD 0xE8
395#define H_GET_PPP 0xEC
396#define H_SET_PPP 0xF0
397#define H_PURR 0xF4
398#define H_PIC 0xF8
399#define H_REG_CRQ 0xFC
400#define H_FREE_CRQ 0x100
401#define H_VIO_SIGNAL 0x104
402#define H_SEND_CRQ 0x108
403#define H_COPY_RDMA 0x110
404#define H_REGISTER_LOGICAL_LAN 0x114
405#define H_FREE_LOGICAL_LAN 0x118
406#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
407#define H_SEND_LOGICAL_LAN 0x120
408#define H_BULK_REMOVE 0x124
409#define H_MULTICAST_CTRL 0x130
410#define H_SET_XDABR 0x134
411#define H_STUFF_TCE 0x138
412#define H_PUT_TCE_INDIRECT 0x13C
413#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
414#define H_VTERM_PARTNER_INFO 0x150
415#define H_REGISTER_VTERM 0x154
416#define H_FREE_VTERM 0x158
417#define H_RESET_EVENTS 0x15C
418#define H_ALLOC_RESOURCE 0x160
419#define H_FREE_RESOURCE 0x164
420#define H_MODIFY_QP 0x168
421#define H_QUERY_QP 0x16C
422#define H_REREGISTER_PMR 0x170
423#define H_REGISTER_SMR 0x174
424#define H_QUERY_MR 0x178
425#define H_QUERY_MW 0x17C
426#define H_QUERY_HCA 0x180
427#define H_QUERY_PORT 0x184
428#define H_MODIFY_PORT 0x188
429#define H_DEFINE_AQP1 0x18C
430#define H_GET_TRACE_BUFFER 0x190
431#define H_DEFINE_AQP0 0x194
432#define H_RESIZE_MR 0x198
433#define H_ATTACH_MCQP 0x19C
434#define H_DETACH_MCQP 0x1A0
435#define H_CREATE_RPT 0x1A4
436#define H_REMOVE_RPT 0x1A8
437#define H_REGISTER_RPAGES 0x1AC
438#define H_DISABLE_AND_GETC 0x1B0
439#define H_ERROR_DATA 0x1B4
440#define H_GET_HCA_INFO 0x1B8
441#define H_GET_PERF_COUNT 0x1BC
442#define H_MANAGE_TRACE 0x1C0
443#define H_GET_CPU_CHARACTERISTICS 0x1C8
444#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
445#define H_QUERY_INT_STATE 0x1E4
446#define H_POLL_PENDING 0x1D8
447#define H_ILLAN_ATTRIBUTES 0x244
448#define H_MODIFY_HEA_QP 0x250
449#define H_QUERY_HEA_QP 0x254
450#define H_QUERY_HEA 0x258
451#define H_QUERY_HEA_PORT 0x25C
452#define H_MODIFY_HEA_PORT 0x260
453#define H_REG_BCMC 0x264
454#define H_DEREG_BCMC 0x268
455#define H_REGISTER_HEA_RPAGES 0x26C
456#define H_DISABLE_AND_GET_HEA 0x270
457#define H_GET_HEA_INFO 0x274
458#define H_ALLOC_HEA_RESOURCE 0x278
459#define H_ADD_CONN 0x284
460#define H_DEL_CONN 0x288
461#define H_JOIN 0x298
462#define H_VASI_STATE 0x2A4
463#define H_ENABLE_CRQ 0x2B0
464#define H_GET_EM_PARMS 0x2B8
465#define H_SET_MPP 0x2D0
466#define H_GET_MPP 0x2D4
467#define H_HOME_NODE_ASSOCIATIVITY 0x2EC
468#define H_XIRR_X 0x2FC
469#define H_RANDOM 0x300
470#define H_SET_MODE 0x31C
471#define H_RESIZE_HPT_PREPARE 0x36C
472#define H_RESIZE_HPT_COMMIT 0x370
473#define H_CLEAN_SLB 0x374
474#define H_INVALIDATE_PID 0x378
475#define H_REGISTER_PROC_TBL 0x37C
476#define H_SIGNAL_SYS_RESET 0x380
477
478#define H_INT_GET_SOURCE_INFO 0x3A8
479#define H_INT_SET_SOURCE_CONFIG 0x3AC
480#define H_INT_GET_SOURCE_CONFIG 0x3B0
481#define H_INT_GET_QUEUE_INFO 0x3B4
482#define H_INT_SET_QUEUE_CONFIG 0x3B8
483#define H_INT_GET_QUEUE_CONFIG 0x3BC
484#define H_INT_SET_OS_REPORTING_LINE 0x3C0
485#define H_INT_GET_OS_REPORTING_LINE 0x3C4
486#define H_INT_ESB 0x3C8
487#define H_INT_SYNC 0x3CC
488#define H_INT_RESET 0x3D0
489
490#define MAX_HCALL_OPCODE H_INT_RESET
491
492
493
494
495
496
497
498
499#define KVMPPC_HCALL_BASE 0xf000
500#define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
501#define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
502
503#define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
504#define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3)
505#define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT
506
507typedef struct SpaprDeviceTreeUpdateHeader {
508 uint32_t version_id;
509} SpaprDeviceTreeUpdateHeader;
510
511#define hcall_dprintf(fmt, ...) \
512 do { \
513 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
514 } while (0)
515
516typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
517 target_ulong opcode,
518 target_ulong *args);
519
520void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
521target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
522 target_ulong *args);
523
524
525#define RTAS_EEH_DISABLE 0
526#define RTAS_EEH_ENABLE 1
527#define RTAS_EEH_THAW_IO 2
528#define RTAS_EEH_THAW_DMA 3
529
530
531#define RTAS_GET_PE_ADDR 0
532#define RTAS_GET_PE_MODE 1
533#define RTAS_PE_MODE_NONE 0
534#define RTAS_PE_MODE_NOT_SHARED 1
535#define RTAS_PE_MODE_SHARED 2
536
537
538#define RTAS_EEH_PE_STATE_NORMAL 0
539#define RTAS_EEH_PE_STATE_RESET 1
540#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
541#define RTAS_EEH_PE_STATE_STOPPED_DMA 4
542#define RTAS_EEH_PE_STATE_UNAVAIL 5
543#define RTAS_EEH_NOT_SUPPORT 0
544#define RTAS_EEH_SUPPORT 1
545#define RTAS_EEH_PE_UNAVAIL_INFO 1000
546#define RTAS_EEH_PE_RECOVER_INFO 0
547
548
549#define RTAS_SLOT_RESET_DEACTIVATE 0
550#define RTAS_SLOT_RESET_HOT 1
551#define RTAS_SLOT_RESET_FUNDAMENTAL 3
552
553
554#define RTAS_SLOT_TEMP_ERR_LOG 1
555#define RTAS_SLOT_PERM_ERR_LOG 2
556
557
558#define RTAS_OUT_SUCCESS 0
559#define RTAS_OUT_NO_ERRORS_FOUND 1
560#define RTAS_OUT_HW_ERROR -1
561#define RTAS_OUT_BUSY -2
562#define RTAS_OUT_PARAM_ERROR -3
563#define RTAS_OUT_NOT_SUPPORTED -3
564#define RTAS_OUT_NO_SUCH_INDICATOR -3
565#define RTAS_OUT_NOT_AUTHORIZED -9002
566#define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
567
568
569#define RTAS_DDW_PGSIZE_4K 0x01
570#define RTAS_DDW_PGSIZE_64K 0x02
571#define RTAS_DDW_PGSIZE_16M 0x04
572#define RTAS_DDW_PGSIZE_32M 0x08
573#define RTAS_DDW_PGSIZE_64M 0x10
574#define RTAS_DDW_PGSIZE_128M 0x20
575#define RTAS_DDW_PGSIZE_256M 0x40
576#define RTAS_DDW_PGSIZE_16G 0x80
577
578
579#define RTAS_TOKEN_BASE 0x2000
580
581#define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
582#define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
583#define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
584#define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
585#define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
586#define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
587#define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
588#define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
589#define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
590#define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
591#define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
592#define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
593#define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
594#define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
595#define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
596#define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
597#define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
598#define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
599#define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
600#define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
601#define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
602#define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
603#define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
604#define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
605#define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
606#define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
607#define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
608#define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
609#define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
610#define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
611#define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
612#define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
613#define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
614#define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
615#define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
616#define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
617#define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
618#define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
619#define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
620#define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
621#define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
622#define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
623
624#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A)
625
626
627#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
628#define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
629#define RTAS_SYSPARM_UUID 48
630
631
632
633
634
635
636
637#define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
638#define RTAS_SENSOR_TYPE_DR 9002
639#define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
640#define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
641
642
643
644
645#define DIAGNOSTICS_RUN_MODE_DISABLED 0
646#define DIAGNOSTICS_RUN_MODE_STAGGERED 1
647#define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
648#define DIAGNOSTICS_RUN_MODE_PERIODIC 3
649
650static inline uint64_t ppc64_phys_to_real(uint64_t addr)
651{
652 return addr & ~0xF000000000000000ULL;
653}
654
655static inline uint32_t rtas_ld(target_ulong phys, int n)
656{
657 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
658}
659
660static inline uint64_t rtas_ldq(target_ulong phys, int n)
661{
662 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
663}
664
665static inline void rtas_st(target_ulong phys, int n, uint32_t val)
666{
667 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
668}
669
670typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
671 uint32_t token,
672 uint32_t nargs, target_ulong args,
673 uint32_t nret, target_ulong rets);
674void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
675target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm,
676 uint32_t token, uint32_t nargs, target_ulong args,
677 uint32_t nret, target_ulong rets);
678void spapr_dt_rtas_tokens(void *fdt, int rtas);
679void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr);
680
681#define SPAPR_TCE_PAGE_SHIFT 12
682#define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
683#define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
684
685#define SPAPR_VIO_BASE_LIOBN 0x00000000
686#define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
687#define SPAPR_PCI_LIOBN(phb_index, window_num) \
688 (0x80000000 | ((phb_index) << 8) | (window_num))
689#define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
690#define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
691
692#define RTAS_ERROR_LOG_MAX 2048
693
694#define RTAS_EVENT_SCAN_RATE 1
695
696
697
698
699
700static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi)
701{
702 intspec[0] = cpu_to_be32(irq);
703 intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
704}
705
706typedef struct SpaprTceTable SpaprTceTable;
707
708#define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
709#define SPAPR_TCE_TABLE(obj) \
710 OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE)
711
712#define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
713#define SPAPR_IOMMU_MEMORY_REGION(obj) \
714 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
715
716struct SpaprTceTable {
717 DeviceState parent;
718 uint32_t liobn;
719 uint32_t nb_table;
720 uint64_t bus_offset;
721 uint32_t page_shift;
722 uint64_t *table;
723 uint32_t mig_nb_table;
724 uint64_t *mig_table;
725 bool bypass;
726 bool need_vfio;
727 bool skipping_replay;
728 int fd;
729 MemoryRegion root;
730 IOMMUMemoryRegion iommu;
731 struct SpaprVioDevice *vdev;
732 QLIST_ENTRY(SpaprTceTable) list;
733};
734
735SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn);
736
737struct SpaprEventLogEntry {
738 uint32_t summary;
739 uint32_t extended_length;
740 void *extended_log;
741 QTAILQ_ENTRY(SpaprEventLogEntry) next;
742};
743
744void spapr_events_init(SpaprMachineState *sm);
745void spapr_dt_events(SpaprMachineState *sm, void *fdt);
746int spapr_h_cas_compose_response(SpaprMachineState *sm,
747 target_ulong addr, target_ulong size,
748 SpaprOptionVector *ov5_updates);
749void close_htab_fd(SpaprMachineState *spapr);
750void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr);
751void spapr_free_hpt(SpaprMachineState *spapr);
752SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
753void spapr_tce_table_enable(SpaprTceTable *tcet,
754 uint32_t page_shift, uint64_t bus_offset,
755 uint32_t nb_table);
756void spapr_tce_table_disable(SpaprTceTable *tcet);
757void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio);
758
759MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet);
760int spapr_dma_dt(void *fdt, int node_off, const char *propname,
761 uint32_t liobn, uint64_t window, uint32_t size);
762int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
763 SpaprTceTable *tcet);
764void spapr_pci_switch_vga(bool big_endian);
765void spapr_hotplug_req_add_by_index(SpaprDrc *drc);
766void spapr_hotplug_req_remove_by_index(SpaprDrc *drc);
767void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type,
768 uint32_t count);
769void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type,
770 uint32_t count);
771void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type,
772 uint32_t count, uint32_t index);
773void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
774 uint32_t count, uint32_t index);
775int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
776void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
777 Error **errp);
778void spapr_clear_pending_events(SpaprMachineState *spapr);
779int spapr_max_server_number(SpaprMachineState *spapr);
780
781
782void spapr_core_release(DeviceState *dev);
783int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
784 void *fdt, int *fdt_start_offset, Error **errp);
785void spapr_lmb_release(DeviceState *dev);
786int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
787 void *fdt, int *fdt_start_offset, Error **errp);
788void spapr_phb_release(DeviceState *dev);
789int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
790 void *fdt, int *fdt_start_offset, Error **errp);
791
792void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns);
793int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset);
794
795#define TYPE_SPAPR_RNG "spapr-rng"
796
797#define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28)
798
799
800
801
802
803
804#define SPAPR_MAX_RAM_SLOTS 32
805
806
807#define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
808
809
810
811
812
813#define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
814
815
816
817
818
819#define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
820#define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
821#define SPAPR_LMB_FLAGS_RESERVED 0x00000080
822
823void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
824
825#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
826
827int spapr_get_vcpu_id(PowerPCCPU *cpu);
828void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
829PowerPCCPU *spapr_find_cpu(int vcpu_id);
830
831int spapr_caps_pre_load(void *opaque);
832int spapr_caps_pre_save(void *opaque);
833
834
835
836
837extern const VMStateDescription vmstate_spapr_cap_htm;
838extern const VMStateDescription vmstate_spapr_cap_vsx;
839extern const VMStateDescription vmstate_spapr_cap_dfp;
840extern const VMStateDescription vmstate_spapr_cap_cfpc;
841extern const VMStateDescription vmstate_spapr_cap_sbbc;
842extern const VMStateDescription vmstate_spapr_cap_ibs;
843extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
844extern const VMStateDescription vmstate_spapr_cap_large_decr;
845extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
846
847static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap)
848{
849 return spapr->eff.caps[cap];
850}
851
852void spapr_caps_init(SpaprMachineState *spapr);
853void spapr_caps_apply(SpaprMachineState *spapr);
854void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu);
855void spapr_caps_add_properties(SpaprMachineClass *smc, Error **errp);
856int spapr_caps_post_migration(SpaprMachineState *spapr);
857
858void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
859 Error **errp);
860
861
862
863#define SPAPR_OV5_XIVE_LEGACY 0x0
864#define SPAPR_OV5_XIVE_EXPLOIT 0x40
865#define SPAPR_OV5_XIVE_BOTH 0x80
866
867void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
868#endif
869