LXR qemu/include/hw/riscv/virt.h

   1/*
   2 * QEMU RISC-V VirtIO machine interface
   3 *
   4 * Copyright (c) 2017 SiFive, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2 or later, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along with
  16 * this program.  If not, see <http://www.gnu.org/licenses/>.
  17 */
  18
  19#ifndef HW_RISCV_VIRT_H
  20#define HW_RISCV_VIRT_H
  21
  22typedef struct {
  23    /*< private >*/
  24    SysBusDevice parent_obj;
  25
  26    /*< public >*/
  27    RISCVHartArrayState soc;
  28    DeviceState *plic;
  29    void *fdt;
  30    int fdt_size;
  31} RISCVVirtState;
  32
  33enum {
  34    VIRT_DEBUG,
  35    VIRT_MROM,
  36    VIRT_TEST,
  37    VIRT_CLINT,
  38    VIRT_PLIC,
  39    VIRT_UART0,
  40    VIRT_VIRTIO,
  41    VIRT_DRAM,
  42    VIRT_PCIE_MMIO,
  43    VIRT_PCIE_PIO,
  44    VIRT_PCIE_ECAM
  45};
  46
  47enum {
  48    UART0_IRQ = 10,
  49    VIRTIO_IRQ = 1, /* 1 to 8 */
  50    VIRTIO_COUNT = 8,
  51    PCIE_IRQ = 0x20, /* 32 to 35 */
  52    VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
  53};
  54
  55enum {
  56    VIRT_CLOCK_FREQ = 1000000000
  57};
  58
  59#define VIRT_PLIC_HART_CONFIG "MS"
  60#define VIRT_PLIC_NUM_SOURCES 127
  61#define VIRT_PLIC_NUM_PRIORITIES 7
  62#define VIRT_PLIC_PRIORITY_BASE 0x04
  63#define VIRT_PLIC_PENDING_BASE 0x1000
  64#define VIRT_PLIC_ENABLE_BASE 0x2000
  65#define VIRT_PLIC_ENABLE_STRIDE 0x80
  66#define VIRT_PLIC_CONTEXT_BASE 0x200000
  67#define VIRT_PLIC_CONTEXT_STRIDE 0x1000
  68
  69#define FDT_PCI_ADDR_CELLS    3
  70#define FDT_PCI_INT_CELLS     1
  71#define FDT_PLIC_ADDR_CELLS   0
  72#define FDT_PLIC_INT_CELLS    1
  73#define FDT_INT_MAP_WIDTH     (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
  74                               FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
  75
  76#if defined(TARGET_RISCV32)
  77#define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
  78#elif defined(TARGET_RISCV64)
  79#define VIRT_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
  80#endif
  81
  82#endif
  83