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25#ifndef GRLIB_H
26#define GRLIB_H
27
28#include "hw/qdev.h"
29#include "hw/sysbus.h"
30
31
32
33
34
35
36
37typedef void (*set_pil_in_fn) (void *opaque, uint32_t pil_in);
38
39void grlib_irqmp_set_irq(void *opaque, int irq, int level);
40
41void grlib_irqmp_ack(DeviceState *dev, int intno);
42
43static inline
44DeviceState *grlib_irqmp_create(hwaddr base,
45 CPUSPARCState *env,
46 qemu_irq **cpu_irqs,
47 uint32_t nr_irqs,
48 set_pil_in_fn set_pil_in)
49{
50 DeviceState *dev;
51
52 assert(cpu_irqs != NULL);
53
54 dev = qdev_create(NULL, "grlib,irqmp");
55 qdev_prop_set_ptr(dev, "set_pil_in", set_pil_in);
56 qdev_prop_set_ptr(dev, "set_pil_in_opaque", env);
57
58 qdev_init_nofail(dev);
59
60 env->irq_manager = dev;
61
62 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
63
64 *cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq,
65 dev,
66 nr_irqs);
67
68 return dev;
69}
70
71
72
73static inline
74DeviceState *grlib_gptimer_create(hwaddr base,
75 uint32_t nr_timers,
76 uint32_t freq,
77 qemu_irq *cpu_irqs,
78 int base_irq)
79{
80 DeviceState *dev;
81 int i;
82
83 dev = qdev_create(NULL, "grlib,gptimer");
84 qdev_prop_set_uint32(dev, "nr-timers", nr_timers);
85 qdev_prop_set_uint32(dev, "frequency", freq);
86 qdev_prop_set_uint32(dev, "irq-line", base_irq);
87
88 qdev_init_nofail(dev);
89
90 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
91
92 for (i = 0; i < nr_timers; i++) {
93 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, cpu_irqs[base_irq + i]);
94 }
95
96 return dev;
97}
98
99
100
101static inline
102DeviceState *grlib_apbuart_create(hwaddr base,
103 Chardev *serial,
104 qemu_irq irq)
105{
106 DeviceState *dev;
107
108 dev = qdev_create(NULL, "grlib,apbuart");
109 qdev_prop_set_chr(dev, "chrdev", serial);
110
111 qdev_init_nofail(dev);
112
113 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
114
115 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
116
117 return dev;
118}
119
120#endif
121