LXR qemu/linux-user/tilegx/cpu

   1/*
   2 *  qemu user cpu loop
   3 *
   4 *  Copyright (c) 2003-2008 Fabrice Bellard
   5 *
   6 *  This program is free software; you can redistribute it and/or modify
   7 *  it under the terms of the GNU General Public License as published by
   8 *  the Free Software Foundation; either version 2 of the License, or
   9 *  (at your option) any later version.
  10 *
  11 *  This program is distributed in the hope that it will be useful,
  12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 *  GNU General Public License for more details.
  15 *
  16 *  You should have received a copy of the GNU General Public License
  17 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include "qemu/osdep.h"
  21#include "qemu.h"
  22#include "cpu_loop-common.h"
  23
  24static void gen_sigill_reg(CPUTLGState *env)
  25{
  26    target_siginfo_t info;
  27
  28    info.si_signo = TARGET_SIGILL;
  29    info.si_errno = 0;
  30    info.si_code = TARGET_ILL_PRVREG;
  31    info._sifields._sigfault._addr = env->pc;
  32    queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
  33}
  34
  35static void do_signal(CPUTLGState *env, int signo, int sigcode)
  36{
  37    target_siginfo_t info;
  38
  39    info.si_signo = signo;
  40    info.si_errno = 0;
  41    info._sifields._sigfault._addr = env->pc;
  42
  43    if (signo == TARGET_SIGSEGV) {
  44        /* The passed in sigcode is a dummy; check for a page mapping
  45           and pass either MAPERR or ACCERR.  */
  46        target_ulong addr = env->excaddr;
  47        info._sifields._sigfault._addr = addr;
  48        if (page_check_range(addr, 1, PAGE_VALID) < 0) {
  49            sigcode = TARGET_SEGV_MAPERR;
  50        } else {
  51            sigcode = TARGET_SEGV_ACCERR;
  52        }
  53    }
  54    info.si_code = sigcode;
  55
  56    queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
  57}
  58
  59static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
  60{
  61    env->excaddr = addr;
  62    do_signal(env, TARGET_SIGSEGV, 0);
  63}
  64
  65static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
  66{
  67    if (unlikely(reg >= TILEGX_R_COUNT)) {
  68        switch (reg) {
  69        case TILEGX_R_SN:
  70        case TILEGX_R_ZERO:
  71            return;
  72        case TILEGX_R_IDN0:
  73        case TILEGX_R_IDN1:
  74        case TILEGX_R_UDN0:
  75        case TILEGX_R_UDN1:
  76        case TILEGX_R_UDN2:
  77        case TILEGX_R_UDN3:
  78            gen_sigill_reg(env);
  79            return;
  80        default:
  81            g_assert_not_reached();
  82        }
  83    }
  84    env->regs[reg] = val;
  85}
  86
  87/*
  88 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
  89 * memory at the address held in the first source register. If the values are
  90 * not equal, then no memory operation is performed. If the values are equal,
  91 * the 8-byte quantity from the second source register is written into memory
  92 * at the address held in the first source register. In either case, the result
  93 * of the instruction is the value read from memory. The compare and write to
  94 * memory are atomic and thus can be used for synchronization purposes. This
  95 * instruction only operates for addresses aligned to a 8-byte boundary.
  96 * Unaligned memory access causes an Unaligned Data Reference interrupt.
  97 *
  98 * Functional Description (64-bit)
  99 *       uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
 100 *       rf[Dest] = memVal;
 101 *       if (memVal == SPR[CmpValueSPR])
 102 *           memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
 103 *
 104 * Functional Description (32-bit)
 105 *       uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
 106 *       rf[Dest] = memVal;
 107 *       if (memVal == signExtend32 (SPR[CmpValueSPR]))
 108 *           memoryWriteWord (rf[SrcA], rf[SrcB]);
 109 *
 110 *
 111 * This function also processes exch and exch4 which need not process SPR.
 112 */
 113static void do_exch(CPUTLGState *env, bool quad, bool cmp)
 114{
 115    target_ulong addr;
 116    target_long val, sprval;
 117
 118    start_exclusive();
 119
 120    addr = env->atomic_srca;
 121    if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
 122        goto sigsegv_maperr;
 123    }
 124
 125    if (cmp) {
 126        if (quad) {
 127            sprval = env->spregs[TILEGX_SPR_CMPEXCH];
 128        } else {
 129            sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
 130        }
 131    }
 132
 133    if (!cmp || val == sprval) {
 134        target_long valb = env->atomic_srcb;
 135        if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
 136            goto sigsegv_maperr;
 137        }
 138    }
 139
 140    set_regval(env, env->atomic_dstr, val);
 141    end_exclusive();
 142    return;
 143
 144 sigsegv_maperr:
 145    end_exclusive();
 146    gen_sigsegv_maperr(env, addr);
 147}
 148
 149static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
 150{
 151    int8_t write = 1;
 152    target_ulong addr;
 153    target_long val, valb;
 154
 155    start_exclusive();
 156
 157    addr = env->atomic_srca;
 158    valb = env->atomic_srcb;
 159    if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
 160        goto sigsegv_maperr;
 161    }
 162
 163    switch (trapnr) {
 164    case TILEGX_EXCP_OPCODE_FETCHADD:
 165    case TILEGX_EXCP_OPCODE_FETCHADD4:
 166        valb += val;
 167        break;
 168    case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
 169        valb += val;
 170        if (valb < 0) {
 171            write = 0;
 172        }
 173        break;
 174    case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
 175        valb += val;
 176        if ((int32_t)valb < 0) {
 177            write = 0;
 178        }
 179        break;
 180    case TILEGX_EXCP_OPCODE_FETCHAND:
 181    case TILEGX_EXCP_OPCODE_FETCHAND4:
 182        valb &= val;
 183        break;
 184    case TILEGX_EXCP_OPCODE_FETCHOR:
 185    case TILEGX_EXCP_OPCODE_FETCHOR4:
 186        valb |= val;
 187        break;
 188    default:
 189        g_assert_not_reached();
 190    }
 191
 192    if (write) {
 193        if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
 194            goto sigsegv_maperr;
 195        }
 196    }
 197
 198    set_regval(env, env->atomic_dstr, val);
 199    end_exclusive();
 200    return;
 201
 202 sigsegv_maperr:
 203    end_exclusive();
 204    gen_sigsegv_maperr(env, addr);
 205}
 206
 207void cpu_loop(CPUTLGState *env)
 208{
 209    CPUState *cs = CPU(tilegx_env_get_cpu(env));
 210    int trapnr;
 211
 212    while (1) {
 213        cpu_exec_start(cs);
 214        trapnr = cpu_exec(cs);
 215        cpu_exec_end(cs);
 216        process_queued_cpu_work(cs);
 217
 218        switch (trapnr) {
 219        case TILEGX_EXCP_SYSCALL:
 220        {
 221            abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
 222                                       env->regs[0], env->regs[1],
 223                                       env->regs[2], env->regs[3],
 224                                       env->regs[4], env->regs[5],
 225                                       env->regs[6], env->regs[7]);
 226            if (ret == -TARGET_ERESTARTSYS) {
 227                env->pc -= 8;
 228            } else if (ret != -TARGET_QEMU_ESIGRETURN) {
 229                env->regs[TILEGX_R_RE] = ret;
 230                env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
 231            }
 232            break;
 233        }
 234        case TILEGX_EXCP_OPCODE_EXCH:
 235            do_exch(env, true, false);
 236            break;
 237        case TILEGX_EXCP_OPCODE_EXCH4:
 238            do_exch(env, false, false);
 239            break;
 240        case TILEGX_EXCP_OPCODE_CMPEXCH:
 241            do_exch(env, true, true);
 242            break;
 243        case TILEGX_EXCP_OPCODE_CMPEXCH4:
 244            do_exch(env, false, true);
 245            break;
 246        case TILEGX_EXCP_OPCODE_FETCHADD:
 247        case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
 248        case TILEGX_EXCP_OPCODE_FETCHAND:
 249        case TILEGX_EXCP_OPCODE_FETCHOR:
 250            do_fetch(env, trapnr, true);
 251            break;
 252        case TILEGX_EXCP_OPCODE_FETCHADD4:
 253        case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
 254        case TILEGX_EXCP_OPCODE_FETCHAND4:
 255        case TILEGX_EXCP_OPCODE_FETCHOR4:
 256            do_fetch(env, trapnr, false);
 257            break;
 258        case TILEGX_EXCP_SIGNAL:
 259            do_signal(env, env->signo, env->sigcode);
 260            break;
 261        case TILEGX_EXCP_REG_IDN_ACCESS:
 262        case TILEGX_EXCP_REG_UDN_ACCESS:
 263            gen_sigill_reg(env);
 264            break;
 265        case EXCP_ATOMIC:
 266            cpu_exec_step_atomic(cs);
 267            break;
 268        default:
 269            fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
 270            g_assert_not_reached();
 271        }
 272        process_pending_signals(env);
 273    }
 274}
 275
 276void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
 277{
 278    int i;
 279    for (i = 0; i < TILEGX_R_COUNT; i++) {
 280        env->regs[i] = regs->regs[i];
 281    }
 282    for (i = 0; i < TILEGX_SPR_COUNT; i++) {
 283        env->spregs[i] = 0;
 284    }
 285    env->pc = regs->pc;
 286}
 287