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20#ifndef ARM_CPU_H
21#define ARM_CPU_H
22
23#include "kvm-consts.h"
24#include "hw/registerfields.h"
25
26#if defined(TARGET_AARCH64)
27
28# define TARGET_LONG_BITS 64
29#else
30# define TARGET_LONG_BITS 32
31#endif
32
33
34#define TCG_GUEST_DEFAULT_MO (0)
35
36#define CPUArchState struct CPUARMState
37
38#include "qemu-common.h"
39#include "cpu-qom.h"
40#include "exec/cpu-defs.h"
41
42#define EXCP_UDEF 1
43#define EXCP_SWI 2
44#define EXCP_PREFETCH_ABORT 3
45#define EXCP_DATA_ABORT 4
46#define EXCP_IRQ 5
47#define EXCP_FIQ 6
48#define EXCP_BKPT 7
49#define EXCP_EXCEPTION_EXIT 8
50#define EXCP_KERNEL_TRAP 9
51#define EXCP_HVC 11
52#define EXCP_HYP_TRAP 12
53#define EXCP_SMC 13
54#define EXCP_VIRQ 14
55#define EXCP_VFIQ 15
56#define EXCP_SEMIHOST 16
57#define EXCP_NOCP 17
58#define EXCP_INVSTATE 18
59#define EXCP_STKOF 19
60
61
62#define ARMV7M_EXCP_RESET 1
63#define ARMV7M_EXCP_NMI 2
64#define ARMV7M_EXCP_HARD 3
65#define ARMV7M_EXCP_MEM 4
66#define ARMV7M_EXCP_BUS 5
67#define ARMV7M_EXCP_USAGE 6
68#define ARMV7M_EXCP_SECURE 7
69#define ARMV7M_EXCP_SVC 11
70#define ARMV7M_EXCP_DEBUG 12
71#define ARMV7M_EXCP_PENDSV 14
72#define ARMV7M_EXCP_SYSTICK 15
73
74
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80
81
82
83enum {
84 M_REG_NS = 0,
85 M_REG_S = 1,
86 M_REG_NUM_BANKS = 2,
87};
88
89
90#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
91#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
92#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
93
94
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98
99
100#ifdef HOST_WORDS_BIGENDIAN
101#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
102#define offsetofhigh32(S, M) offsetof(S, M)
103#else
104#define offsetoflow32(S, M) offsetof(S, M)
105#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
106#endif
107
108
109#define ARM_CPU_IRQ 0
110#define ARM_CPU_FIQ 1
111#define ARM_CPU_VIRQ 2
112#define ARM_CPU_VFIQ 3
113
114#define NB_MMU_MODES 8
115
116
117
118
119#define TARGET_INSN_START_EXTRA_WORDS 2
120
121
122
123
124
125
126#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
127#define ARM_INSN_START_WORD2_SHIFT 14
128
129
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142
143
144typedef struct DynamicGDBXMLInfo {
145 char *desc;
146 int num_cpregs;
147 uint32_t *cpregs_keys;
148} DynamicGDBXMLInfo;
149
150
151typedef struct ARMGenericTimer {
152 uint64_t cval;
153 uint64_t ctl;
154} ARMGenericTimer;
155
156#define GTIMER_PHYS 0
157#define GTIMER_VIRT 1
158#define GTIMER_HYP 2
159#define GTIMER_SEC 3
160#define NUM_GTIMERS 4
161
162typedef struct {
163 uint64_t raw_tcr;
164 uint32_t mask;
165 uint32_t base_mask;
166} TCR;
167
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193
194#ifdef TARGET_AARCH64
195# define ARM_MAX_VQ 16
196#else
197# define ARM_MAX_VQ 1
198#endif
199
200typedef struct ARMVectorReg {
201 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
202} ARMVectorReg;
203
204#ifdef TARGET_AARCH64
205
206typedef struct ARMPredicateReg {
207 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
208} ARMPredicateReg;
209
210
211typedef struct ARMPACKey {
212 uint64_t lo, hi;
213} ARMPACKey;
214#endif
215
216
217typedef struct CPUARMState {
218
219 uint32_t regs[16];
220
221
222
223
224
225
226 uint64_t xregs[32];
227 uint64_t pc;
228
229
230
231
232
233
234
235
236
237
238
239
240 uint32_t pstate;
241 uint32_t aarch64;
242
243
244
245
246 uint32_t uncached_cpsr;
247 uint32_t spsr;
248
249
250 uint64_t banked_spsr[8];
251 uint32_t banked_r13[8];
252 uint32_t banked_r14[8];
253
254
255 uint32_t usr_regs[5];
256 uint32_t fiq_regs[5];
257
258
259 uint32_t CF;
260 uint32_t VF;
261 uint32_t NF;
262 uint32_t ZF;
263 uint32_t QF;
264 uint32_t GE;
265 uint32_t thumb;
266 uint32_t condexec_bits;
267 uint32_t btype;
268 uint64_t daif;
269
270 uint64_t elr_el[4];
271 uint64_t sp_el[4];
272
273
274 struct {
275 uint32_t c0_cpuid;
276 union {
277 struct {
278 uint64_t _unused_csselr0;
279 uint64_t csselr_ns;
280 uint64_t _unused_csselr1;
281 uint64_t csselr_s;
282 };
283 uint64_t csselr_el[4];
284 };
285 union {
286 struct {
287 uint64_t _unused_sctlr;
288 uint64_t sctlr_ns;
289 uint64_t hsctlr;
290 uint64_t sctlr_s;
291 };
292 uint64_t sctlr_el[4];
293 };
294 uint64_t cpacr_el1;
295 uint64_t cptr_el[4];
296 uint32_t c1_xscaleauxcr;
297 uint64_t sder;
298 uint32_t nsacr;
299 union {
300 struct {
301 uint64_t _unused_ttbr0_0;
302 uint64_t ttbr0_ns;
303 uint64_t _unused_ttbr0_1;
304 uint64_t ttbr0_s;
305 };
306 uint64_t ttbr0_el[4];
307 };
308 union {
309 struct {
310 uint64_t _unused_ttbr1_0;
311 uint64_t ttbr1_ns;
312 uint64_t _unused_ttbr1_1;
313 uint64_t ttbr1_s;
314 };
315 uint64_t ttbr1_el[4];
316 };
317 uint64_t vttbr_el2;
318
319 TCR tcr_el[4];
320 TCR vtcr_el2;
321 uint32_t c2_data;
322 uint32_t c2_insn;
323 union {
324
325
326 struct {
327 uint64_t dacr_ns;
328 uint64_t dacr_s;
329 };
330 struct {
331 uint64_t dacr32_el2;
332 };
333 };
334 uint32_t pmsav5_data_ap;
335 uint32_t pmsav5_insn_ap;
336 uint64_t hcr_el2;
337 uint64_t scr_el3;
338 union {
339 struct {
340 uint64_t ifsr_ns;
341 uint64_t ifsr_s;
342 };
343 struct {
344 uint64_t ifsr32_el2;
345 };
346 };
347 union {
348 struct {
349 uint64_t _unused_dfsr;
350 uint64_t dfsr_ns;
351 uint64_t hsr;
352 uint64_t dfsr_s;
353 };
354 uint64_t esr_el[4];
355 };
356 uint32_t c6_region[8];
357 union {
358 struct {
359 uint64_t _unused_far0;
360#ifdef HOST_WORDS_BIGENDIAN
361 uint32_t ifar_ns;
362 uint32_t dfar_ns;
363 uint32_t ifar_s;
364 uint32_t dfar_s;
365#else
366 uint32_t dfar_ns;
367 uint32_t ifar_ns;
368 uint32_t dfar_s;
369 uint32_t ifar_s;
370#endif
371 uint64_t _unused_far3;
372 };
373 uint64_t far_el[4];
374 };
375 uint64_t hpfar_el2;
376 uint64_t hstr_el2;
377 union {
378 struct {
379 uint64_t _unused_par_0;
380 uint64_t par_ns;
381 uint64_t _unused_par_1;
382 uint64_t par_s;
383 };
384 uint64_t par_el[4];
385 };
386
387 uint32_t c9_insn;
388 uint32_t c9_data;
389 uint64_t c9_pmcr;
390 uint64_t c9_pmcnten;
391 uint64_t c9_pmovsr;
392 uint64_t c9_pmuserenr;
393 uint64_t c9_pmselr;
394 uint64_t c9_pminten;
395 union {
396 struct {
397#ifdef HOST_WORDS_BIGENDIAN
398 uint64_t _unused_mair_0;
399 uint32_t mair1_ns;
400 uint32_t mair0_ns;
401 uint64_t _unused_mair_1;
402 uint32_t mair1_s;
403 uint32_t mair0_s;
404#else
405 uint64_t _unused_mair_0;
406 uint32_t mair0_ns;
407 uint32_t mair1_ns;
408 uint64_t _unused_mair_1;
409 uint32_t mair0_s;
410 uint32_t mair1_s;
411#endif
412 };
413 uint64_t mair_el[4];
414 };
415 union {
416 struct {
417 uint64_t _unused_vbar;
418 uint64_t vbar_ns;
419 uint64_t hvbar;
420 uint64_t vbar_s;
421 };
422 uint64_t vbar_el[4];
423 };
424 uint32_t mvbar;
425 struct {
426 uint32_t fcseidr_ns;
427 uint32_t fcseidr_s;
428 };
429 union {
430 struct {
431 uint64_t _unused_contextidr_0;
432 uint64_t contextidr_ns;
433 uint64_t _unused_contextidr_1;
434 uint64_t contextidr_s;
435 };
436 uint64_t contextidr_el[4];
437 };
438 union {
439 struct {
440 uint64_t tpidrurw_ns;
441 uint64_t tpidrprw_ns;
442 uint64_t htpidr;
443 uint64_t _tpidr_el3;
444 };
445 uint64_t tpidr_el[4];
446 };
447
448 uint64_t tpidrurw_s;
449 uint64_t tpidrprw_s;
450 uint64_t tpidruro_s;
451
452 union {
453 uint64_t tpidruro_ns;
454 uint64_t tpidrro_el[1];
455 };
456 uint64_t c14_cntfrq;
457 uint64_t c14_cntkctl;
458 uint32_t cnthctl_el2;
459 uint64_t cntvoff_el2;
460 ARMGenericTimer c14_timer[NUM_GTIMERS];
461 uint32_t c15_cpar;
462 uint32_t c15_ticonfig;
463 uint32_t c15_i_max;
464 uint32_t c15_i_min;
465 uint32_t c15_threadid;
466 uint32_t c15_config_base_address;
467 uint32_t c15_diagnostic;
468 uint32_t c15_power_diagnostic;
469 uint32_t c15_power_control;
470 uint64_t dbgbvr[16];
471 uint64_t dbgbcr[16];
472 uint64_t dbgwvr[16];
473 uint64_t dbgwcr[16];
474 uint64_t mdscr_el1;
475 uint64_t oslsr_el1;
476 uint64_t mdcr_el2;
477 uint64_t mdcr_el3;
478
479
480
481
482
483 uint64_t c15_ccnt;
484
485
486
487
488
489
490
491 uint64_t c15_ccnt_delta;
492 uint64_t c14_pmevcntr[31];
493 uint64_t c14_pmevcntr_delta[31];
494 uint64_t c14_pmevtyper[31];
495 uint64_t pmccfiltr_el0;
496 uint64_t vpidr_el2;
497 uint64_t vmpidr_el2;
498 } cp15;
499
500 struct {
501
502
503
504
505
506
507
508
509
510
511
512 uint32_t other_sp;
513 uint32_t other_ss_msp;
514 uint32_t other_ss_psp;
515 uint32_t vecbase[M_REG_NUM_BANKS];
516 uint32_t basepri[M_REG_NUM_BANKS];
517 uint32_t control[M_REG_NUM_BANKS];
518 uint32_t ccr[M_REG_NUM_BANKS];
519 uint32_t cfsr[M_REG_NUM_BANKS];
520 uint32_t hfsr;
521 uint32_t dfsr;
522 uint32_t sfsr;
523 uint32_t mmfar[M_REG_NUM_BANKS];
524 uint32_t bfar;
525 uint32_t sfar;
526 unsigned mpu_ctrl[M_REG_NUM_BANKS];
527 int exception;
528 uint32_t primask[M_REG_NUM_BANKS];
529 uint32_t faultmask[M_REG_NUM_BANKS];
530 uint32_t aircr;
531 uint32_t secure;
532 uint32_t csselr[M_REG_NUM_BANKS];
533 uint32_t scr[M_REG_NUM_BANKS];
534 uint32_t msplim[M_REG_NUM_BANKS];
535 uint32_t psplim[M_REG_NUM_BANKS];
536 } v7m;
537
538
539
540
541
542
543
544 struct {
545 uint32_t syndrome;
546 uint32_t fsr;
547 uint64_t vaddress;
548 uint32_t target_el;
549
550
551
552 } exception;
553
554
555 struct {
556 uint8_t pending;
557 uint8_t has_esr;
558 uint64_t esr;
559 } serror;
560
561
562 uint32_t irq_line_state;
563
564
565 uint32_t teecr;
566 uint32_t teehbr;
567
568
569 struct {
570 ARMVectorReg zregs[32];
571
572#ifdef TARGET_AARCH64
573
574#define FFR_PRED_NUM 16
575 ARMPredicateReg pregs[17];
576
577 ARMPredicateReg preg_tmp;
578#endif
579
580
581 uint32_t qc[4] QEMU_ALIGNED(16);
582 int vec_len;
583 int vec_stride;
584
585 uint32_t xregs[16];
586
587
588 uint32_t scratch[8];
589
590
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610
611 float_status fp_status;
612 float_status fp_status_f16;
613 float_status standard_fp_status;
614
615
616 uint64_t zcr_el[4];
617 } vfp;
618 uint64_t exclusive_addr;
619 uint64_t exclusive_val;
620 uint64_t exclusive_high;
621
622
623 struct {
624 uint64_t regs[16];
625 uint64_t val;
626
627 uint32_t cregs[16];
628 } iwmmxt;
629
630#ifdef TARGET_AARCH64
631 ARMPACKey apia_key;
632 ARMPACKey apib_key;
633 ARMPACKey apda_key;
634 ARMPACKey apdb_key;
635 ARMPACKey apga_key;
636#endif
637
638#if defined(CONFIG_USER_ONLY)
639
640 int eabi;
641#endif
642
643 struct CPUBreakpoint *cpu_breakpoint[16];
644 struct CPUWatchpoint *cpu_watchpoint[16];
645
646
647 struct {} end_reset_fields;
648
649 CPU_COMMON
650
651
652
653
654 uint64_t features;
655
656
657 struct {
658 uint32_t *drbar;
659 uint32_t *drsr;
660 uint32_t *dracr;
661 uint32_t rnr[M_REG_NUM_BANKS];
662 } pmsav7;
663
664
665 struct {
666
667
668
669
670
671 uint32_t *rbar[M_REG_NUM_BANKS];
672 uint32_t *rlar[M_REG_NUM_BANKS];
673 uint32_t mair0[M_REG_NUM_BANKS];
674 uint32_t mair1[M_REG_NUM_BANKS];
675 } pmsav8;
676
677
678 struct {
679 uint32_t *rbar;
680 uint32_t *rlar;
681 uint32_t rnr;
682 uint32_t ctrl;
683 } sau;
684
685 void *nvic;
686 const struct arm_boot_info *boot_info;
687
688 void *gicv3state;
689} CPUARMState;
690
691
692
693
694
695
696typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
697typedef struct ARMELChangeHook ARMELChangeHook;
698struct ARMELChangeHook {
699 ARMELChangeHookFn *hook;
700 void *opaque;
701 QLIST_ENTRY(ARMELChangeHook) node;
702};
703
704
705
706typedef enum ARMPSCIState {
707 PSCI_ON = 0,
708 PSCI_OFF = 1,
709 PSCI_ON_PENDING = 2
710} ARMPSCIState;
711
712typedef struct ARMISARegisters ARMISARegisters;
713
714
715
716
717
718
719
720struct ARMCPU {
721
722 CPUState parent_obj;
723
724
725 CPUARMState env;
726
727
728 GHashTable *cp_regs;
729
730
731
732
733
734
735
736 uint64_t *cpreg_indexes;
737
738 uint64_t *cpreg_values;
739
740 int32_t cpreg_array_len;
741
742
743
744
745 uint64_t *cpreg_vmstate_indexes;
746 uint64_t *cpreg_vmstate_values;
747 int32_t cpreg_vmstate_array_len;
748
749 DynamicGDBXMLInfo dyn_xml;
750
751
752 QEMUTimer *gt_timer[NUM_GTIMERS];
753
754
755
756
757 QEMUTimer *pmu_timer;
758
759 qemu_irq gt_timer_outputs[NUM_GTIMERS];
760
761 qemu_irq gicv3_maintenance_interrupt;
762
763 qemu_irq pmu_interrupt;
764
765
766 MemoryRegion *secure_memory;
767
768
769 Object *idau;
770
771
772 const char *dtb_compatible;
773
774
775
776
777
778 uint32_t psci_version;
779
780
781 bool start_powered_off;
782
783
784 ARMPSCIState power_state;
785
786
787 bool has_el2;
788
789 bool has_el3;
790
791 bool has_pmu;
792
793
794 bool has_mpu;
795
796 uint32_t pmsav7_dregion;
797
798 uint32_t sau_sregion;
799
800
801
802
803 uint32_t psci_conduit;
804
805
806 uint32_t init_svtor;
807
808
809
810
811 uint32_t kvm_target;
812
813
814 uint32_t kvm_init_features[7];
815
816
817 bool mp_is_up;
818
819
820
821
822 bool host_cpu_probe_failed;
823
824
825
826
827 int32_t core_count;
828
829
830
831
832
833
834
835
836
837
838
839
840
841 struct ARMISARegisters {
842 uint32_t id_isar0;
843 uint32_t id_isar1;
844 uint32_t id_isar2;
845 uint32_t id_isar3;
846 uint32_t id_isar4;
847 uint32_t id_isar5;
848 uint32_t id_isar6;
849 uint32_t mvfr0;
850 uint32_t mvfr1;
851 uint32_t mvfr2;
852 uint64_t id_aa64isar0;
853 uint64_t id_aa64isar1;
854 uint64_t id_aa64pfr0;
855 uint64_t id_aa64pfr1;
856 uint64_t id_aa64mmfr0;
857 uint64_t id_aa64mmfr1;
858 } isar;
859 uint32_t midr;
860 uint32_t revidr;
861 uint32_t reset_fpsid;
862 uint32_t ctr;
863 uint32_t reset_sctlr;
864 uint32_t id_pfr0;
865 uint32_t id_pfr1;
866 uint32_t id_dfr0;
867 uint64_t pmceid0;
868 uint64_t pmceid1;
869 uint32_t id_afr0;
870 uint32_t id_mmfr0;
871 uint32_t id_mmfr1;
872 uint32_t id_mmfr2;
873 uint32_t id_mmfr3;
874 uint32_t id_mmfr4;
875 uint64_t id_aa64dfr0;
876 uint64_t id_aa64dfr1;
877 uint64_t id_aa64afr0;
878 uint64_t id_aa64afr1;
879 uint32_t dbgdidr;
880 uint32_t clidr;
881 uint64_t mp_affinity;
882
883
884
885 uint32_t ccsidr[16];
886 uint64_t reset_cbar;
887 uint32_t reset_auxcr;
888 bool reset_hivecs;
889
890 uint32_t dcz_blocksize;
891 uint64_t rvbar;
892
893
894 int gic_num_lrs;
895 int gic_vpribits;
896 int gic_vprebits;
897
898
899
900
901
902
903 bool cfgend;
904
905 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
906 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
907
908 int32_t node_id;
909
910
911 uint8_t device_irq_level;
912
913
914 uint32_t sve_max_vq;
915};
916
917static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
918{
919 return container_of(env, ARMCPU, env);
920}
921
922void arm_cpu_post_init(Object *obj);
923
924uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
925
926#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
927
928#define ENV_OFFSET offsetof(ARMCPU, env)
929
930#ifndef CONFIG_USER_ONLY
931extern const struct VMStateDescription vmstate_arm_cpu;
932#endif
933
934void arm_cpu_do_interrupt(CPUState *cpu);
935void arm_v7m_cpu_do_interrupt(CPUState *cpu);
936bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
937
938void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
939 int flags);
940
941hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
942 MemTxAttrs *attrs);
943
944int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
945int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
946
947
948
949
950int arm_gen_dynamic_xml(CPUState *cpu);
951
952
953
954
955
956const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
957
958int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
959 int cpuid, void *opaque);
960int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
961 int cpuid, void *opaque);
962
963#ifdef TARGET_AARCH64
964int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
965int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
966void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
967void aarch64_sve_change_el(CPUARMState *env, int old_el,
968 int new_el, bool el0_a64);
969#else
970static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
971static inline void aarch64_sve_change_el(CPUARMState *env, int o,
972 int n, bool a)
973{ }
974#endif
975
976target_ulong do_arm_semihosting(CPUARMState *env);
977void aarch64_sync_32_to_64(CPUARMState *env);
978void aarch64_sync_64_to_32(CPUARMState *env);
979
980int fp_exception_el(CPUARMState *env, int cur_el);
981int sve_exception_el(CPUARMState *env, int cur_el);
982uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
983
984static inline bool is_a64(CPUARMState *env)
985{
986 return env->aarch64;
987}
988
989
990
991
992int cpu_arm_signal_handler(int host_signum, void *pinfo,
993 void *puc);
994
995
996
997
998
999
1000
1001
1002
1003void pmu_op_start(CPUARMState *env);
1004void pmu_op_finish(CPUARMState *env);
1005
1006
1007
1008
1009void arm_pmu_timer_cb(void *opaque);
1010
1011
1012
1013
1014void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1015void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1016
1017
1018
1019
1020
1021
1022
1023
1024void pmu_init(ARMCPU *cpu);
1025
1026
1027
1028
1029
1030
1031
1032#define SCTLR_M (1U << 0)
1033#define SCTLR_A (1U << 1)
1034#define SCTLR_C (1U << 2)
1035#define SCTLR_W (1U << 3)
1036#define SCTLR_nTLSMD_32 (1U << 3)
1037#define SCTLR_SA (1U << 3)
1038#define SCTLR_P (1U << 4)
1039#define SCTLR_LSMAOE_32 (1U << 4)
1040#define SCTLR_SA0 (1U << 4)
1041#define SCTLR_D (1U << 5)
1042#define SCTLR_CP15BEN (1U << 5)
1043#define SCTLR_L (1U << 6)
1044#define SCTLR_nAA (1U << 6)
1045#define SCTLR_B (1U << 7)
1046#define SCTLR_ITD (1U << 7)
1047#define SCTLR_S (1U << 8)
1048#define SCTLR_SED (1U << 8)
1049#define SCTLR_R (1U << 9)
1050#define SCTLR_UMA (1U << 9)
1051#define SCTLR_F (1U << 10)
1052#define SCTLR_SW (1U << 10)
1053#define SCTLR_EnRCTX (1U << 10)
1054#define SCTLR_Z (1U << 11)
1055#define SCTLR_EOS (1U << 11)
1056#define SCTLR_I (1U << 12)
1057#define SCTLR_V (1U << 13)
1058#define SCTLR_EnDB (1U << 13)
1059#define SCTLR_RR (1U << 14)
1060#define SCTLR_DZE (1U << 14)
1061#define SCTLR_L4 (1U << 15)
1062#define SCTLR_UCT (1U << 15)
1063#define SCTLR_DT (1U << 16)
1064#define SCTLR_nTWI (1U << 16)
1065#define SCTLR_HA (1U << 17)
1066#define SCTLR_BR (1U << 17)
1067#define SCTLR_IT (1U << 18)
1068#define SCTLR_nTWE (1U << 18)
1069#define SCTLR_WXN (1U << 19)
1070#define SCTLR_ST (1U << 20)
1071#define SCTLR_UWXN (1U << 20)
1072#define SCTLR_FI (1U << 21)
1073#define SCTLR_IESB (1U << 21)
1074#define SCTLR_U (1U << 22)
1075#define SCTLR_EIS (1U << 22)
1076#define SCTLR_XP (1U << 23)
1077#define SCTLR_SPAN (1U << 23)
1078#define SCTLR_VE (1U << 24)
1079#define SCTLR_E0E (1U << 24)
1080#define SCTLR_EE (1U << 25)
1081#define SCTLR_L2 (1U << 26)
1082#define SCTLR_UCI (1U << 26)
1083#define SCTLR_NMFI (1U << 27)
1084#define SCTLR_EnDA (1U << 27)
1085#define SCTLR_TRE (1U << 28)
1086#define SCTLR_nTLSMD_64 (1U << 28)
1087#define SCTLR_AFE (1U << 29)
1088#define SCTLR_LSMAOE_64 (1U << 29)
1089#define SCTLR_TE (1U << 30)
1090#define SCTLR_EnIB (1U << 30)
1091#define SCTLR_EnIA (1U << 31)
1092#define SCTLR_BT0 (1ULL << 35)
1093#define SCTLR_BT1 (1ULL << 36)
1094#define SCTLR_ITFSB (1ULL << 37)
1095#define SCTLR_TCF0 (3ULL << 38)
1096#define SCTLR_TCF (3ULL << 40)
1097#define SCTLR_ATA0 (1ULL << 42)
1098#define SCTLR_ATA (1ULL << 43)
1099#define SCTLR_DSSBS (1ULL << 44)
1100
1101#define CPTR_TCPAC (1U << 31)
1102#define CPTR_TTA (1U << 20)
1103#define CPTR_TFP (1U << 10)
1104#define CPTR_TZ (1U << 8)
1105#define CPTR_EZ (1U << 8)
1106
1107#define MDCR_EPMAD (1U << 21)
1108#define MDCR_EDAD (1U << 20)
1109#define MDCR_SPME (1U << 17)
1110#define MDCR_HPMD (1U << 17)
1111#define MDCR_SDD (1U << 16)
1112#define MDCR_SPD (3U << 14)
1113#define MDCR_TDRA (1U << 11)
1114#define MDCR_TDOSA (1U << 10)
1115#define MDCR_TDA (1U << 9)
1116#define MDCR_TDE (1U << 8)
1117#define MDCR_HPME (1U << 7)
1118#define MDCR_TPM (1U << 6)
1119#define MDCR_TPMCR (1U << 5)
1120#define MDCR_HPMN (0x1fU)
1121
1122
1123#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1124
1125#define CPSR_M (0x1fU)
1126#define CPSR_T (1U << 5)
1127#define CPSR_F (1U << 6)
1128#define CPSR_I (1U << 7)
1129#define CPSR_A (1U << 8)
1130#define CPSR_E (1U << 9)
1131#define CPSR_IT_2_7 (0xfc00U)
1132#define CPSR_GE (0xfU << 16)
1133#define CPSR_IL (1U << 20)
1134
1135
1136
1137
1138
1139#define CPSR_RESERVED (0x7U << 21)
1140#define CPSR_J (1U << 24)
1141#define CPSR_IT_0_1 (3U << 25)
1142#define CPSR_Q (1U << 27)
1143#define CPSR_V (1U << 28)
1144#define CPSR_C (1U << 29)
1145#define CPSR_Z (1U << 30)
1146#define CPSR_N (1U << 31)
1147#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1148#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1149
1150#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1151#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1152 | CPSR_NZCV)
1153
1154#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
1155
1156#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1157
1158#define CPSR_ERET_MASK (~CPSR_RESERVED)
1159
1160
1161#define XPSR_EXCP 0x1ffU
1162#define XPSR_SPREALIGN (1U << 9)
1163#define XPSR_IT_2_7 CPSR_IT_2_7
1164#define XPSR_GE CPSR_GE
1165#define XPSR_SFPA (1U << 20)
1166#define XPSR_T (1U << 24)
1167#define XPSR_IT_0_1 CPSR_IT_0_1
1168#define XPSR_Q CPSR_Q
1169#define XPSR_V CPSR_V
1170#define XPSR_C CPSR_C
1171#define XPSR_Z CPSR_Z
1172#define XPSR_N CPSR_N
1173#define XPSR_NZCV CPSR_NZCV
1174#define XPSR_IT CPSR_IT
1175
1176#define TTBCR_N (7U << 0)
1177#define TTBCR_T0SZ (7U << 0)
1178#define TTBCR_PD0 (1U << 4)
1179#define TTBCR_PD1 (1U << 5)
1180#define TTBCR_EPD0 (1U << 7)
1181#define TTBCR_IRGN0 (3U << 8)
1182#define TTBCR_ORGN0 (3U << 10)
1183#define TTBCR_SH0 (3U << 12)
1184#define TTBCR_T1SZ (3U << 16)
1185#define TTBCR_A1 (1U << 22)
1186#define TTBCR_EPD1 (1U << 23)
1187#define TTBCR_IRGN1 (3U << 24)
1188#define TTBCR_ORGN1 (3U << 26)
1189#define TTBCR_SH1 (1U << 28)
1190#define TTBCR_EAE (1U << 31)
1191
1192
1193
1194
1195
1196#define PSTATE_SP (1U)
1197#define PSTATE_M (0xFU)
1198#define PSTATE_nRW (1U << 4)
1199#define PSTATE_F (1U << 6)
1200#define PSTATE_I (1U << 7)
1201#define PSTATE_A (1U << 8)
1202#define PSTATE_D (1U << 9)
1203#define PSTATE_BTYPE (3U << 10)
1204#define PSTATE_IL (1U << 20)
1205#define PSTATE_SS (1U << 21)
1206#define PSTATE_V (1U << 28)
1207#define PSTATE_C (1U << 29)
1208#define PSTATE_Z (1U << 30)
1209#define PSTATE_N (1U << 31)
1210#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1211#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1212#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1213
1214#define PSTATE_MODE_EL3h 13
1215#define PSTATE_MODE_EL3t 12
1216#define PSTATE_MODE_EL2h 9
1217#define PSTATE_MODE_EL2t 8
1218#define PSTATE_MODE_EL1h 5
1219#define PSTATE_MODE_EL1t 4
1220#define PSTATE_MODE_EL0t 0
1221
1222
1223
1224
1225void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1226
1227
1228static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1229{
1230 return (el << 2) | handler;
1231}
1232
1233
1234
1235
1236
1237static inline uint32_t pstate_read(CPUARMState *env)
1238{
1239 int ZF;
1240
1241 ZF = (env->ZF == 0);
1242 return (env->NF & 0x80000000) | (ZF << 30)
1243 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1244 | env->pstate | env->daif | (env->btype << 10);
1245}
1246
1247static inline void pstate_write(CPUARMState *env, uint32_t val)
1248{
1249 env->ZF = (~val) & PSTATE_Z;
1250 env->NF = val;
1251 env->CF = (val >> 29) & 1;
1252 env->VF = (val << 3) & 0x80000000;
1253 env->daif = val & PSTATE_DAIF;
1254 env->btype = (val >> 10) & 3;
1255 env->pstate = val & ~CACHED_PSTATE_BITS;
1256}
1257
1258
1259uint32_t cpsr_read(CPUARMState *env);
1260
1261typedef enum CPSRWriteType {
1262 CPSRWriteByInstr = 0,
1263 CPSRWriteExceptionReturn = 1,
1264 CPSRWriteRaw = 2,
1265 CPSRWriteByGDBStub = 3,
1266} CPSRWriteType;
1267
1268
1269void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1270 CPSRWriteType write_type);
1271
1272
1273static inline uint32_t xpsr_read(CPUARMState *env)
1274{
1275 int ZF;
1276 ZF = (env->ZF == 0);
1277 return (env->NF & 0x80000000) | (ZF << 30)
1278 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1279 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1280 | ((env->condexec_bits & 0xfc) << 8)
1281 | env->v7m.exception;
1282}
1283
1284
1285static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1286{
1287 if (mask & XPSR_NZCV) {
1288 env->ZF = (~val) & XPSR_Z;
1289 env->NF = val;
1290 env->CF = (val >> 29) & 1;
1291 env->VF = (val << 3) & 0x80000000;
1292 }
1293 if (mask & XPSR_Q) {
1294 env->QF = ((val & XPSR_Q) != 0);
1295 }
1296 if (mask & XPSR_T) {
1297 env->thumb = ((val & XPSR_T) != 0);
1298 }
1299 if (mask & XPSR_IT_0_1) {
1300 env->condexec_bits &= ~3;
1301 env->condexec_bits |= (val >> 25) & 3;
1302 }
1303 if (mask & XPSR_IT_2_7) {
1304 env->condexec_bits &= 3;
1305 env->condexec_bits |= (val >> 8) & 0xfc;
1306 }
1307 if (mask & XPSR_EXCP) {
1308
1309 write_v7m_exception(env, val & XPSR_EXCP);
1310 }
1311}
1312
1313#define HCR_VM (1ULL << 0)
1314#define HCR_SWIO (1ULL << 1)
1315#define HCR_PTW (1ULL << 2)
1316#define HCR_FMO (1ULL << 3)
1317#define HCR_IMO (1ULL << 4)
1318#define HCR_AMO (1ULL << 5)
1319#define HCR_VF (1ULL << 6)
1320#define HCR_VI (1ULL << 7)
1321#define HCR_VSE (1ULL << 8)
1322#define HCR_FB (1ULL << 9)
1323#define HCR_BSU_MASK (3ULL << 10)
1324#define HCR_DC (1ULL << 12)
1325#define HCR_TWI (1ULL << 13)
1326#define HCR_TWE (1ULL << 14)
1327#define HCR_TID0 (1ULL << 15)
1328#define HCR_TID1 (1ULL << 16)
1329#define HCR_TID2 (1ULL << 17)
1330#define HCR_TID3 (1ULL << 18)
1331#define HCR_TSC (1ULL << 19)
1332#define HCR_TIDCP (1ULL << 20)
1333#define HCR_TACR (1ULL << 21)
1334#define HCR_TSW (1ULL << 22)
1335#define HCR_TPCP (1ULL << 23)
1336#define HCR_TPU (1ULL << 24)
1337#define HCR_TTLB (1ULL << 25)
1338#define HCR_TVM (1ULL << 26)
1339#define HCR_TGE (1ULL << 27)
1340#define HCR_TDZ (1ULL << 28)
1341#define HCR_HCD (1ULL << 29)
1342#define HCR_TRVM (1ULL << 30)
1343#define HCR_RW (1ULL << 31)
1344#define HCR_CD (1ULL << 32)
1345#define HCR_ID (1ULL << 33)
1346#define HCR_E2H (1ULL << 34)
1347#define HCR_TLOR (1ULL << 35)
1348#define HCR_TERR (1ULL << 36)
1349#define HCR_TEA (1ULL << 37)
1350#define HCR_MIOCNCE (1ULL << 38)
1351#define HCR_APK (1ULL << 40)
1352#define HCR_API (1ULL << 41)
1353#define HCR_NV (1ULL << 42)
1354#define HCR_NV1 (1ULL << 43)
1355#define HCR_AT (1ULL << 44)
1356#define HCR_NV2 (1ULL << 45)
1357#define HCR_FWB (1ULL << 46)
1358#define HCR_FIEN (1ULL << 47)
1359#define HCR_TID4 (1ULL << 49)
1360#define HCR_TICAB (1ULL << 50)
1361#define HCR_TOCU (1ULL << 52)
1362#define HCR_TTLBIS (1ULL << 54)
1363#define HCR_TTLBOS (1ULL << 55)
1364#define HCR_ATA (1ULL << 56)
1365#define HCR_DCT (1ULL << 57)
1366
1367
1368
1369
1370
1371
1372#define HCR_MASK ((1ULL << 34) - 1)
1373
1374#define SCR_NS (1U << 0)
1375#define SCR_IRQ (1U << 1)
1376#define SCR_FIQ (1U << 2)
1377#define SCR_EA (1U << 3)
1378#define SCR_FW (1U << 4)
1379#define SCR_AW (1U << 5)
1380#define SCR_NET (1U << 6)
1381#define SCR_SMD (1U << 7)
1382#define SCR_HCE (1U << 8)
1383#define SCR_SIF (1U << 9)
1384#define SCR_RW (1U << 10)
1385#define SCR_ST (1U << 11)
1386#define SCR_TWI (1U << 12)
1387#define SCR_TWE (1U << 13)
1388#define SCR_TLOR (1U << 14)
1389#define SCR_TERR (1U << 15)
1390#define SCR_APK (1U << 16)
1391#define SCR_API (1U << 17)
1392#define SCR_EEL2 (1U << 18)
1393#define SCR_EASE (1U << 19)
1394#define SCR_NMEA (1U << 20)
1395#define SCR_FIEN (1U << 21)
1396#define SCR_ENSCXT (1U << 25)
1397#define SCR_ATA (1U << 26)
1398
1399
1400uint32_t vfp_get_fpscr(CPUARMState *env);
1401void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1402
1403
1404
1405
1406
1407
1408
1409
1410#define FPSR_MASK 0xf800009f
1411#define FPCR_MASK 0x07ff9f00
1412
1413#define FPCR_IOE (1 << 8)
1414#define FPCR_DZE (1 << 9)
1415#define FPCR_OFE (1 << 10)
1416#define FPCR_UFE (1 << 11)
1417#define FPCR_IXE (1 << 12)
1418#define FPCR_IDE (1 << 15)
1419#define FPCR_FZ16 (1 << 19)
1420#define FPCR_FZ (1 << 24)
1421#define FPCR_DN (1 << 25)
1422#define FPCR_QC (1 << 27)
1423
1424static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1425{
1426 return vfp_get_fpscr(env) & FPSR_MASK;
1427}
1428
1429static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1430{
1431 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1432 vfp_set_fpscr(env, new_fpscr);
1433}
1434
1435static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1436{
1437 return vfp_get_fpscr(env) & FPCR_MASK;
1438}
1439
1440static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1441{
1442 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1443 vfp_set_fpscr(env, new_fpscr);
1444}
1445
1446enum arm_cpu_mode {
1447 ARM_CPU_MODE_USR = 0x10,
1448 ARM_CPU_MODE_FIQ = 0x11,
1449 ARM_CPU_MODE_IRQ = 0x12,
1450 ARM_CPU_MODE_SVC = 0x13,
1451 ARM_CPU_MODE_MON = 0x16,
1452 ARM_CPU_MODE_ABT = 0x17,
1453 ARM_CPU_MODE_HYP = 0x1a,
1454 ARM_CPU_MODE_UND = 0x1b,
1455 ARM_CPU_MODE_SYS = 0x1f
1456};
1457
1458
1459#define ARM_VFP_FPSID 0
1460#define ARM_VFP_FPSCR 1
1461#define ARM_VFP_MVFR2 5
1462#define ARM_VFP_MVFR1 6
1463#define ARM_VFP_MVFR0 7
1464#define ARM_VFP_FPEXC 8
1465#define ARM_VFP_FPINST 9
1466#define ARM_VFP_FPINST2 10
1467
1468
1469#define ARM_IWMMXT_wCID 0
1470#define ARM_IWMMXT_wCon 1
1471#define ARM_IWMMXT_wCSSF 2
1472#define ARM_IWMMXT_wCASF 3
1473#define ARM_IWMMXT_wCGR0 8
1474#define ARM_IWMMXT_wCGR1 9
1475#define ARM_IWMMXT_wCGR2 10
1476#define ARM_IWMMXT_wCGR3 11
1477
1478
1479FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1480FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1481FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1482FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1483FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1484FIELD(V7M_CCR, STKALIGN, 9, 1)
1485FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1486FIELD(V7M_CCR, DC, 16, 1)
1487FIELD(V7M_CCR, IC, 17, 1)
1488FIELD(V7M_CCR, BP, 18, 1)
1489
1490
1491FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1492FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1493FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1494FIELD(V7M_SCR, SEVONPEND, 4, 1)
1495
1496
1497FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1498FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1499FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1500FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1501FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1502FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1503FIELD(V7M_AIRCR, PRIS, 14, 1)
1504FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1505FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1506
1507
1508FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1509FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1510FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1511FIELD(V7M_CFSR, MSTKERR, 4, 1)
1512FIELD(V7M_CFSR, MLSPERR, 5, 1)
1513FIELD(V7M_CFSR, MMARVALID, 7, 1)
1514
1515
1516FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1517FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1518FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1519FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1520FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1521FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1522FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1523
1524
1525FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1526FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1527FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1528FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1529FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1530FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1531FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1532
1533
1534FIELD(V7M_CFSR, MMFSR, 0, 8)
1535FIELD(V7M_CFSR, BFSR, 8, 8)
1536FIELD(V7M_CFSR, UFSR, 16, 16)
1537
1538
1539FIELD(V7M_HFSR, VECTTBL, 1, 1)
1540FIELD(V7M_HFSR, FORCED, 30, 1)
1541FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1542
1543
1544FIELD(V7M_DFSR, HALTED, 0, 1)
1545FIELD(V7M_DFSR, BKPT, 1, 1)
1546FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1547FIELD(V7M_DFSR, VCATCH, 3, 1)
1548FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1549
1550
1551FIELD(V7M_SFSR, INVEP, 0, 1)
1552FIELD(V7M_SFSR, INVIS, 1, 1)
1553FIELD(V7M_SFSR, INVER, 2, 1)
1554FIELD(V7M_SFSR, AUVIOL, 3, 1)
1555FIELD(V7M_SFSR, INVTRAN, 4, 1)
1556FIELD(V7M_SFSR, LSPERR, 5, 1)
1557FIELD(V7M_SFSR, SFARVALID, 6, 1)
1558FIELD(V7M_SFSR, LSERR, 7, 1)
1559
1560
1561FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1562FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1563FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1564
1565
1566FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1567FIELD(V7M_CLIDR, LOUIS, 21, 3)
1568FIELD(V7M_CLIDR, LOC, 24, 3)
1569FIELD(V7M_CLIDR, LOUU, 27, 3)
1570FIELD(V7M_CLIDR, ICB, 30, 2)
1571
1572FIELD(V7M_CSSELR, IND, 0, 1)
1573FIELD(V7M_CSSELR, LEVEL, 1, 3)
1574
1575
1576
1577
1578FIELD(V7M_CSSELR, INDEX, 0, 4)
1579
1580
1581
1582
1583FIELD(ID_ISAR0, SWAP, 0, 4)
1584FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1585FIELD(ID_ISAR0, BITFIELD, 8, 4)
1586FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1587FIELD(ID_ISAR0, COPROC, 16, 4)
1588FIELD(ID_ISAR0, DEBUG, 20, 4)
1589FIELD(ID_ISAR0, DIVIDE, 24, 4)
1590
1591FIELD(ID_ISAR1, ENDIAN, 0, 4)
1592FIELD(ID_ISAR1, EXCEPT, 4, 4)
1593FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1594FIELD(ID_ISAR1, EXTEND, 12, 4)
1595FIELD(ID_ISAR1, IFTHEN, 16, 4)
1596FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1597FIELD(ID_ISAR1, INTERWORK, 24, 4)
1598FIELD(ID_ISAR1, JAZELLE, 28, 4)
1599
1600FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1601FIELD(ID_ISAR2, MEMHINT, 4, 4)
1602FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1603FIELD(ID_ISAR2, MULT, 12, 4)
1604FIELD(ID_ISAR2, MULTS, 16, 4)
1605FIELD(ID_ISAR2, MULTU, 20, 4)
1606FIELD(ID_ISAR2, PSR_AR, 24, 4)
1607FIELD(ID_ISAR2, REVERSAL, 28, 4)
1608
1609FIELD(ID_ISAR3, SATURATE, 0, 4)
1610FIELD(ID_ISAR3, SIMD, 4, 4)
1611FIELD(ID_ISAR3, SVC, 8, 4)
1612FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1613FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1614FIELD(ID_ISAR3, T32COPY, 20, 4)
1615FIELD(ID_ISAR3, TRUENOP, 24, 4)
1616FIELD(ID_ISAR3, T32EE, 28, 4)
1617
1618FIELD(ID_ISAR4, UNPRIV, 0, 4)
1619FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1620FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1621FIELD(ID_ISAR4, SMC, 12, 4)
1622FIELD(ID_ISAR4, BARRIER, 16, 4)
1623FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1624FIELD(ID_ISAR4, PSR_M, 24, 4)
1625FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1626
1627FIELD(ID_ISAR5, SEVL, 0, 4)
1628FIELD(ID_ISAR5, AES, 4, 4)
1629FIELD(ID_ISAR5, SHA1, 8, 4)
1630FIELD(ID_ISAR5, SHA2, 12, 4)
1631FIELD(ID_ISAR5, CRC32, 16, 4)
1632FIELD(ID_ISAR5, RDM, 24, 4)
1633FIELD(ID_ISAR5, VCMA, 28, 4)
1634
1635FIELD(ID_ISAR6, JSCVT, 0, 4)
1636FIELD(ID_ISAR6, DP, 4, 4)
1637FIELD(ID_ISAR6, FHM, 8, 4)
1638FIELD(ID_ISAR6, SB, 12, 4)
1639FIELD(ID_ISAR6, SPECRES, 16, 4)
1640
1641FIELD(ID_MMFR4, SPECSEI, 0, 4)
1642FIELD(ID_MMFR4, AC2, 4, 4)
1643FIELD(ID_MMFR4, XNX, 8, 4)
1644FIELD(ID_MMFR4, CNP, 12, 4)
1645FIELD(ID_MMFR4, HPDS, 16, 4)
1646FIELD(ID_MMFR4, LSM, 20, 4)
1647FIELD(ID_MMFR4, CCIDX, 24, 4)
1648FIELD(ID_MMFR4, EVT, 28, 4)
1649
1650FIELD(ID_AA64ISAR0, AES, 4, 4)
1651FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1652FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1653FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1654FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1655FIELD(ID_AA64ISAR0, RDM, 28, 4)
1656FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1657FIELD(ID_AA64ISAR0, SM3, 36, 4)
1658FIELD(ID_AA64ISAR0, SM4, 40, 4)
1659FIELD(ID_AA64ISAR0, DP, 44, 4)
1660FIELD(ID_AA64ISAR0, FHM, 48, 4)
1661FIELD(ID_AA64ISAR0, TS, 52, 4)
1662FIELD(ID_AA64ISAR0, TLB, 56, 4)
1663FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1664
1665FIELD(ID_AA64ISAR1, DPB, 0, 4)
1666FIELD(ID_AA64ISAR1, APA, 4, 4)
1667FIELD(ID_AA64ISAR1, API, 8, 4)
1668FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1669FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1670FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1671FIELD(ID_AA64ISAR1, GPA, 24, 4)
1672FIELD(ID_AA64ISAR1, GPI, 28, 4)
1673FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1674FIELD(ID_AA64ISAR1, SB, 36, 4)
1675FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1676
1677FIELD(ID_AA64PFR0, EL0, 0, 4)
1678FIELD(ID_AA64PFR0, EL1, 4, 4)
1679FIELD(ID_AA64PFR0, EL2, 8, 4)
1680FIELD(ID_AA64PFR0, EL3, 12, 4)
1681FIELD(ID_AA64PFR0, FP, 16, 4)
1682FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1683FIELD(ID_AA64PFR0, GIC, 24, 4)
1684FIELD(ID_AA64PFR0, RAS, 28, 4)
1685FIELD(ID_AA64PFR0, SVE, 32, 4)
1686
1687FIELD(ID_AA64PFR1, BT, 0, 4)
1688FIELD(ID_AA64PFR1, SBSS, 4, 4)
1689FIELD(ID_AA64PFR1, MTE, 8, 4)
1690FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
1691
1692FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
1693FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
1694FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
1695FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
1696FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
1697FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
1698FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
1699FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
1700FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
1701FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
1702FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
1703FIELD(ID_AA64MMFR0, EXS, 44, 4)
1704
1705FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
1706FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
1707FIELD(ID_AA64MMFR1, VH, 8, 4)
1708FIELD(ID_AA64MMFR1, HPDS, 12, 4)
1709FIELD(ID_AA64MMFR1, LO, 16, 4)
1710FIELD(ID_AA64MMFR1, PAN, 20, 4)
1711FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
1712FIELD(ID_AA64MMFR1, XNX, 28, 4)
1713
1714FIELD(ID_DFR0, COPDBG, 0, 4)
1715FIELD(ID_DFR0, COPSDBG, 4, 4)
1716FIELD(ID_DFR0, MMAPDBG, 8, 4)
1717FIELD(ID_DFR0, COPTRC, 12, 4)
1718FIELD(ID_DFR0, MMAPTRC, 16, 4)
1719FIELD(ID_DFR0, MPROFDBG, 20, 4)
1720FIELD(ID_DFR0, PERFMON, 24, 4)
1721FIELD(ID_DFR0, TRACEFILT, 28, 4)
1722
1723FIELD(MVFR0, SIMDREG, 0, 4)
1724FIELD(MVFR0, FPSP, 4, 4)
1725FIELD(MVFR0, FPDP, 8, 4)
1726FIELD(MVFR0, FPTRAP, 12, 4)
1727FIELD(MVFR0, FPDIVIDE, 16, 4)
1728FIELD(MVFR0, FPSQRT, 20, 4)
1729FIELD(MVFR0, FPSHVEC, 24, 4)
1730FIELD(MVFR0, FPROUND, 28, 4)
1731
1732FIELD(MVFR1, FPFTZ, 0, 4)
1733FIELD(MVFR1, FPDNAN, 4, 4)
1734FIELD(MVFR1, SIMDLS, 8, 4)
1735FIELD(MVFR1, SIMDINT, 12, 4)
1736FIELD(MVFR1, SIMDSP, 16, 4)
1737FIELD(MVFR1, SIMDHP, 20, 4)
1738FIELD(MVFR1, FPHP, 24, 4)
1739FIELD(MVFR1, SIMDFMAC, 28, 4)
1740
1741FIELD(MVFR2, SIMDMISC, 0, 4)
1742FIELD(MVFR2, FPMISC, 4, 4)
1743
1744QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
1745
1746
1747
1748
1749
1750enum arm_features {
1751 ARM_FEATURE_VFP,
1752 ARM_FEATURE_AUXCR,
1753 ARM_FEATURE_XSCALE,
1754 ARM_FEATURE_IWMMXT,
1755 ARM_FEATURE_V6,
1756 ARM_FEATURE_V6K,
1757 ARM_FEATURE_V7,
1758 ARM_FEATURE_THUMB2,
1759 ARM_FEATURE_PMSA,
1760 ARM_FEATURE_VFP3,
1761 ARM_FEATURE_NEON,
1762 ARM_FEATURE_M,
1763 ARM_FEATURE_OMAPCP,
1764 ARM_FEATURE_THUMB2EE,
1765 ARM_FEATURE_V7MP,
1766 ARM_FEATURE_V7VE,
1767 ARM_FEATURE_V4T,
1768 ARM_FEATURE_V5,
1769 ARM_FEATURE_STRONGARM,
1770 ARM_FEATURE_VAPA,
1771 ARM_FEATURE_VFP4,
1772 ARM_FEATURE_GENERIC_TIMER,
1773 ARM_FEATURE_MVFR,
1774 ARM_FEATURE_DUMMY_C15_REGS,
1775 ARM_FEATURE_CACHE_TEST_CLEAN,
1776 ARM_FEATURE_CACHE_DIRTY_REG,
1777 ARM_FEATURE_CACHE_BLOCK_OPS,
1778 ARM_FEATURE_MPIDR,
1779 ARM_FEATURE_PXN,
1780 ARM_FEATURE_LPAE,
1781 ARM_FEATURE_V8,
1782 ARM_FEATURE_AARCH64,
1783 ARM_FEATURE_CBAR,
1784 ARM_FEATURE_CRC,
1785 ARM_FEATURE_CBAR_RO,
1786 ARM_FEATURE_EL2,
1787 ARM_FEATURE_EL3,
1788 ARM_FEATURE_THUMB_DSP,
1789 ARM_FEATURE_PMU,
1790 ARM_FEATURE_VBAR,
1791 ARM_FEATURE_M_SECURITY,
1792 ARM_FEATURE_M_MAIN,
1793};
1794
1795static inline int arm_feature(CPUARMState *env, int feature)
1796{
1797 return (env->features & (1ULL << feature)) != 0;
1798}
1799
1800#if !defined(CONFIG_USER_ONLY)
1801
1802
1803
1804
1805
1806
1807static inline bool arm_is_secure_below_el3(CPUARMState *env)
1808{
1809 if (arm_feature(env, ARM_FEATURE_EL3)) {
1810 return !(env->cp15.scr_el3 & SCR_NS);
1811 } else {
1812
1813
1814
1815 return false;
1816 }
1817}
1818
1819
1820static inline bool arm_is_el3_or_mon(CPUARMState *env)
1821{
1822 if (arm_feature(env, ARM_FEATURE_EL3)) {
1823 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
1824
1825 return true;
1826 } else if (!is_a64(env) &&
1827 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
1828
1829 return true;
1830 }
1831 }
1832 return false;
1833}
1834
1835
1836static inline bool arm_is_secure(CPUARMState *env)
1837{
1838 if (arm_is_el3_or_mon(env)) {
1839 return true;
1840 }
1841 return arm_is_secure_below_el3(env);
1842}
1843
1844#else
1845static inline bool arm_is_secure_below_el3(CPUARMState *env)
1846{
1847 return false;
1848}
1849
1850static inline bool arm_is_secure(CPUARMState *env)
1851{
1852 return false;
1853}
1854#endif
1855
1856
1857
1858
1859
1860
1861
1862uint64_t arm_hcr_el2_eff(CPUARMState *env);
1863
1864
1865static inline bool arm_el_is_aa64(CPUARMState *env, int el)
1866{
1867
1868
1869
1870 assert(el >= 1 && el <= 3);
1871 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
1872
1873
1874
1875
1876
1877 if (el == 3) {
1878 return aa64;
1879 }
1880
1881 if (arm_feature(env, ARM_FEATURE_EL3)) {
1882 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
1883 }
1884
1885 if (el == 2) {
1886 return aa64;
1887 }
1888
1889 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
1890 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
1891 }
1892
1893 return aa64;
1894}
1895
1896
1897
1898
1899
1900
1901
1902
1903static inline bool access_secure_reg(CPUARMState *env)
1904{
1905 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
1906 !arm_el_is_aa64(env, 3) &&
1907 !(env->cp15.scr_el3 & SCR_NS));
1908
1909 return ret;
1910}
1911
1912
1913#define A32_BANKED_REG_GET(_env, _regname, _secure) \
1914 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1915
1916#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1917 do { \
1918 if (_secure) { \
1919 (_env)->cp15._regname##_s = (_val); \
1920 } else { \
1921 (_env)->cp15._regname##_ns = (_val); \
1922 } \
1923 } while (0)
1924
1925
1926
1927
1928
1929
1930#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1931 A32_BANKED_REG_GET((_env), _regname, \
1932 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1933
1934#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1935 A32_BANKED_REG_SET((_env), _regname, \
1936 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1937 (_val))
1938
1939void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1940uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1941 uint32_t cur_el, bool secure);
1942
1943
1944#ifndef CONFIG_USER_ONLY
1945bool armv7m_nvic_can_take_pending_exception(void *opaque);
1946#else
1947static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
1948{
1949 return true;
1950}
1951#endif
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
1992 bool *ptargets_secure);
1993
1994
1995
1996
1997
1998
1999
2000
2001void armv7m_nvic_acknowledge_irq(void *opaque);
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023int armv7m_nvic_raw_execution_priority(void *opaque);
2024
2025
2026
2027
2028
2029
2030
2031#ifndef CONFIG_USER_ONLY
2032bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2033#else
2034static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2035{
2036 return false;
2037}
2038#endif
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066#define CP_REG_AA64_SHIFT 28
2067#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2068
2069
2070
2071
2072
2073#define CP_REG_NS_SHIFT 29
2074#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2075
2076#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
2077 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
2078 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2079
2080#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2081 (CP_REG_AA64_MASK | \
2082 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
2083 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
2084 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
2085 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
2086 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
2087 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2088
2089
2090
2091
2092static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2093{
2094 uint32_t cpregid = kvmid;
2095 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2096 cpregid |= CP_REG_AA64_MASK;
2097 } else {
2098 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2099 cpregid |= (1 << 15);
2100 }
2101
2102
2103
2104
2105 cpregid |= 1 << CP_REG_NS_SHIFT;
2106 }
2107 return cpregid;
2108}
2109
2110
2111
2112
2113static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2114{
2115 uint64_t kvmid;
2116
2117 if (cpregid & CP_REG_AA64_MASK) {
2118 kvmid = cpregid & ~CP_REG_AA64_MASK;
2119 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2120 } else {
2121 kvmid = cpregid & ~(1 << 15);
2122 if (cpregid & (1 << 15)) {
2123 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2124 } else {
2125 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2126 }
2127 }
2128 return kvmid;
2129}
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153#define ARM_CP_SPECIAL 0x0001
2154#define ARM_CP_CONST 0x0002
2155#define ARM_CP_64BIT 0x0004
2156#define ARM_CP_SUPPRESS_TB_END 0x0008
2157#define ARM_CP_OVERRIDE 0x0010
2158#define ARM_CP_ALIAS 0x0020
2159#define ARM_CP_IO 0x0040
2160#define ARM_CP_NO_RAW 0x0080
2161#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
2162#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
2163#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
2164#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
2165#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
2166#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
2167#define ARM_CP_FPU 0x1000
2168#define ARM_CP_SVE 0x2000
2169#define ARM_CP_NO_GDB 0x4000
2170
2171#define ARM_CP_SENTINEL 0xffff
2172
2173#define ARM_CP_FLAG_MASK 0x70ff
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184enum {
2185 ARM_CP_STATE_AA32 = 0,
2186 ARM_CP_STATE_AA64 = 1,
2187 ARM_CP_STATE_BOTH = 2,
2188};
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200enum {
2201 ARM_CP_SECSTATE_S = (1 << 0),
2202 ARM_CP_SECSTATE_NS = (1 << 1),
2203};
2204
2205
2206
2207
2208
2209static inline bool cptype_valid(int cptype)
2210{
2211 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2212 || ((cptype & ARM_CP_SPECIAL) &&
2213 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2214}
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233#define PL3_R 0x80
2234#define PL3_W 0x40
2235#define PL2_R (0x20 | PL3_R)
2236#define PL2_W (0x10 | PL3_W)
2237#define PL1_R (0x08 | PL2_R)
2238#define PL1_W (0x04 | PL2_W)
2239#define PL0_R (0x02 | PL1_R)
2240#define PL0_W (0x01 | PL1_W)
2241
2242
2243
2244
2245
2246
2247
2248#ifdef CONFIG_USER_ONLY
2249#define PL0U_R PL0_R
2250#else
2251#define PL0U_R PL1_R
2252#endif
2253
2254#define PL3_RW (PL3_R | PL3_W)
2255#define PL2_RW (PL2_R | PL2_W)
2256#define PL1_RW (PL1_R | PL1_W)
2257#define PL0_RW (PL0_R | PL0_W)
2258
2259
2260static inline int arm_highest_el(CPUARMState *env)
2261{
2262 if (arm_feature(env, ARM_FEATURE_EL3)) {
2263 return 3;
2264 }
2265 if (arm_feature(env, ARM_FEATURE_EL2)) {
2266 return 2;
2267 }
2268 return 1;
2269}
2270
2271
2272static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2273{
2274 return env->v7m.exception != 0;
2275}
2276
2277
2278
2279
2280static inline int arm_current_el(CPUARMState *env)
2281{
2282 if (arm_feature(env, ARM_FEATURE_M)) {
2283 return arm_v7m_is_handler_mode(env) ||
2284 !(env->v7m.control[env->v7m.secure] & 1);
2285 }
2286
2287 if (is_a64(env)) {
2288 return extract32(env->pstate, 2, 2);
2289 }
2290
2291 switch (env->uncached_cpsr & 0x1f) {
2292 case ARM_CPU_MODE_USR:
2293 return 0;
2294 case ARM_CPU_MODE_HYP:
2295 return 2;
2296 case ARM_CPU_MODE_MON:
2297 return 3;
2298 default:
2299 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2300
2301
2302
2303 return 3;
2304 }
2305
2306 return 1;
2307 }
2308}
2309
2310typedef struct ARMCPRegInfo ARMCPRegInfo;
2311
2312typedef enum CPAccessResult {
2313
2314 CP_ACCESS_OK = 0,
2315
2316
2317
2318
2319
2320
2321 CP_ACCESS_TRAP = 1,
2322
2323
2324
2325
2326 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2327
2328 CP_ACCESS_TRAP_EL2 = 3,
2329 CP_ACCESS_TRAP_EL3 = 4,
2330
2331 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2332 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2333
2334
2335
2336 CP_ACCESS_TRAP_FP_EL2 = 7,
2337 CP_ACCESS_TRAP_FP_EL3 = 8,
2338} CPAccessResult;
2339
2340
2341
2342
2343typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2344typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2345 uint64_t value);
2346
2347typedef CPAccessResult CPAccessFn(CPUARMState *env,
2348 const ARMCPRegInfo *opaque,
2349 bool isread);
2350
2351typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2352
2353#define CP_ANY 0xff
2354
2355
2356struct ARMCPRegInfo {
2357
2358 const char *name;
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376 uint8_t cp;
2377 uint8_t crn;
2378 uint8_t crm;
2379 uint8_t opc0;
2380 uint8_t opc1;
2381 uint8_t opc2;
2382
2383 int state;
2384
2385 int type;
2386
2387 int access;
2388
2389 int secure;
2390
2391
2392
2393
2394 void *opaque;
2395
2396
2397
2398 uint64_t resetvalue;
2399
2400
2401
2402
2403
2404
2405 ptrdiff_t fieldoffset;
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418 ptrdiff_t bank_fieldoffsets[2];
2419
2420
2421
2422
2423
2424
2425 CPAccessFn *accessfn;
2426
2427
2428
2429
2430 CPReadFn *readfn;
2431
2432
2433
2434
2435 CPWriteFn *writefn;
2436
2437
2438
2439
2440
2441 CPReadFn *raw_readfn;
2442
2443
2444
2445
2446
2447
2448 CPWriteFn *raw_writefn;
2449
2450
2451
2452
2453 CPResetFn *resetfn;
2454};
2455
2456
2457
2458
2459#define CPREG_FIELD32(env, ri) \
2460 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2461#define CPREG_FIELD64(env, ri) \
2462 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2463
2464#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2465
2466void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2467 const ARMCPRegInfo *regs, void *opaque);
2468void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2469 const ARMCPRegInfo *regs, void *opaque);
2470static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2471{
2472 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2473}
2474static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2475{
2476 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2477}
2478const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2479
2480
2481
2482
2483
2484
2485
2486typedef struct ARMCPRegUserSpaceInfo {
2487
2488 const char *name;
2489
2490
2491 bool is_glob;
2492
2493
2494 uint64_t exported_bits;
2495
2496
2497 uint64_t fixed_bits;
2498} ARMCPRegUserSpaceInfo;
2499
2500#define REGUSERINFO_SENTINEL { .name = NULL }
2501
2502void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2503
2504
2505void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2506 uint64_t value);
2507
2508uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2509
2510
2511
2512
2513void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2514
2515
2516
2517
2518static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2519{
2520 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2521}
2522
2523static inline bool cp_access_ok(int current_el,
2524 const ARMCPRegInfo *ri, int isread)
2525{
2526 return (ri->access >> ((current_el * 2) + isread)) & 1;
2527}
2528
2529
2530uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546bool write_list_to_cpustate(ARMCPU *cpu);
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562bool write_cpustate_to_list(ARMCPU *cpu);
2563
2564#define ARM_CPUID_TI915T 0x54029152
2565#define ARM_CPUID_TI925T 0x54029252
2566
2567#if defined(CONFIG_USER_ONLY)
2568#define TARGET_PAGE_BITS 12
2569#else
2570
2571
2572
2573#define TARGET_PAGE_BITS_VARY
2574#define TARGET_PAGE_BITS_MIN 10
2575#endif
2576
2577#if defined(TARGET_AARCH64)
2578# define TARGET_PHYS_ADDR_SPACE_BITS 48
2579# define TARGET_VIRT_ADDR_SPACE_BITS 48
2580#else
2581# define TARGET_PHYS_ADDR_SPACE_BITS 40
2582# define TARGET_VIRT_ADDR_SPACE_BITS 32
2583#endif
2584
2585static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
2586 unsigned int target_el)
2587{
2588 CPUARMState *env = cs->env_ptr;
2589 unsigned int cur_el = arm_current_el(env);
2590 bool secure = arm_is_secure(env);
2591 bool pstate_unmasked;
2592 int8_t unmasked = 0;
2593 uint64_t hcr_el2;
2594
2595
2596
2597
2598
2599 if (cur_el > target_el) {
2600 return false;
2601 }
2602
2603 hcr_el2 = arm_hcr_el2_eff(env);
2604
2605 switch (excp_idx) {
2606 case EXCP_FIQ:
2607 pstate_unmasked = !(env->daif & PSTATE_F);
2608 break;
2609
2610 case EXCP_IRQ:
2611 pstate_unmasked = !(env->daif & PSTATE_I);
2612 break;
2613
2614 case EXCP_VFIQ:
2615 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
2616
2617 return false;
2618 }
2619 return !(env->daif & PSTATE_F);
2620 case EXCP_VIRQ:
2621 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
2622
2623 return false;
2624 }
2625 return !(env->daif & PSTATE_I);
2626 default:
2627 g_assert_not_reached();
2628 }
2629
2630
2631
2632
2633
2634 if ((target_el > cur_el) && (target_el != 1)) {
2635
2636 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2637
2638
2639
2640
2641
2642 if (target_el == 3 || !secure) {
2643 unmasked = 1;
2644 }
2645 } else {
2646
2647
2648
2649
2650 bool hcr, scr;
2651
2652 switch (excp_idx) {
2653 case EXCP_FIQ:
2654
2655
2656
2657
2658
2659
2660 hcr = hcr_el2 & HCR_FMO;
2661 scr = (env->cp15.scr_el3 & SCR_FIQ);
2662
2663
2664
2665
2666
2667
2668 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
2669 break;
2670 case EXCP_IRQ:
2671
2672
2673
2674
2675
2676
2677 hcr = hcr_el2 & HCR_IMO;
2678 scr = false;
2679 break;
2680 default:
2681 g_assert_not_reached();
2682 }
2683
2684 if ((scr || hcr) && !secure) {
2685 unmasked = 1;
2686 }
2687 }
2688 }
2689
2690
2691
2692
2693 return unmasked || pstate_unmasked;
2694}
2695
2696#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2697#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2698#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2699
2700#define cpu_signal_handler cpu_arm_signal_handler
2701#define cpu_list arm_cpu_list
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782#define ARM_MMU_IDX_A 0x10
2783#define ARM_MMU_IDX_NOTLB 0x20
2784#define ARM_MMU_IDX_M 0x40
2785
2786
2787#define ARM_MMU_IDX_M_PRIV 0x1
2788#define ARM_MMU_IDX_M_NEGPRI 0x2
2789#define ARM_MMU_IDX_M_S 0x4
2790
2791#define ARM_MMU_IDX_TYPE_MASK (~0x7)
2792#define ARM_MMU_IDX_COREIDX_MASK 0x7
2793
2794typedef enum ARMMMUIdx {
2795 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A,
2796 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A,
2797 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
2798 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
2799 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
2800 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
2801 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A,
2802 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
2803 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
2804 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M,
2805 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M,
2806 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M,
2807 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M,
2808 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M,
2809 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M,
2810
2811
2812
2813 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB,
2814 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB,
2815} ARMMMUIdx;
2816
2817
2818
2819
2820typedef enum ARMMMUIdxBit {
2821 ARMMMUIdxBit_S12NSE0 = 1 << 0,
2822 ARMMMUIdxBit_S12NSE1 = 1 << 1,
2823 ARMMMUIdxBit_S1E2 = 1 << 2,
2824 ARMMMUIdxBit_S1E3 = 1 << 3,
2825 ARMMMUIdxBit_S1SE0 = 1 << 4,
2826 ARMMMUIdxBit_S1SE1 = 1 << 5,
2827 ARMMMUIdxBit_S2NS = 1 << 6,
2828 ARMMMUIdxBit_MUser = 1 << 0,
2829 ARMMMUIdxBit_MPriv = 1 << 1,
2830 ARMMMUIdxBit_MUserNegPri = 1 << 2,
2831 ARMMMUIdxBit_MPrivNegPri = 1 << 3,
2832 ARMMMUIdxBit_MSUser = 1 << 4,
2833 ARMMMUIdxBit_MSPriv = 1 << 5,
2834 ARMMMUIdxBit_MSUserNegPri = 1 << 6,
2835 ARMMMUIdxBit_MSPrivNegPri = 1 << 7,
2836} ARMMMUIdxBit;
2837
2838#define MMU_USER_IDX 0
2839
2840static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
2841{
2842 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
2843}
2844
2845static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
2846{
2847 if (arm_feature(env, ARM_FEATURE_M)) {
2848 return mmu_idx | ARM_MMU_IDX_M;
2849 } else {
2850 return mmu_idx | ARM_MMU_IDX_A;
2851 }
2852}
2853
2854
2855static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
2856{
2857 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) {
2858 case ARM_MMU_IDX_A:
2859 return mmu_idx & 3;
2860 case ARM_MMU_IDX_M:
2861 return mmu_idx & ARM_MMU_IDX_M_PRIV;
2862 default:
2863 g_assert_not_reached();
2864 }
2865}
2866
2867
2868
2869
2870ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
2871 bool secstate, bool priv);
2872
2873
2874ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884int cpu_mmu_index(CPUARMState *env, bool ifetch);
2885
2886
2887typedef enum ARMASIdx {
2888 ARMASIdx_NS = 0,
2889 ARMASIdx_S = 1,
2890} ARMASIdx;
2891
2892
2893static inline int arm_debug_target_el(CPUARMState *env)
2894{
2895 bool secure = arm_is_secure(env);
2896 bool route_to_el2 = false;
2897
2898 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
2899 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
2900 env->cp15.mdcr_el2 & MDCR_TDE;
2901 }
2902
2903 if (route_to_el2) {
2904 return 2;
2905 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
2906 !arm_el_is_aa64(env, 3) && secure) {
2907 return 3;
2908 } else {
2909 return 1;
2910 }
2911}
2912
2913static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
2914{
2915
2916
2917
2918 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
2919}
2920
2921
2922static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
2923{
2924 int cur_el = arm_current_el(env);
2925 int debug_el;
2926
2927 if (cur_el == 3) {
2928 return false;
2929 }
2930
2931
2932 if (arm_is_secure_below_el3(env)
2933 && extract32(env->cp15.mdcr_el3, 16, 1)) {
2934 return false;
2935 }
2936
2937
2938
2939
2940
2941 debug_el = arm_debug_target_el(env);
2942
2943 if (cur_el == debug_el) {
2944 return extract32(env->cp15.mdscr_el1, 13, 1)
2945 && !(env->daif & PSTATE_D);
2946 }
2947
2948
2949 return debug_el > cur_el;
2950}
2951
2952static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
2953{
2954 int el = arm_current_el(env);
2955
2956 if (el == 0 && arm_el_is_aa64(env, 1)) {
2957 return aa64_generate_debug_exceptions(env);
2958 }
2959
2960 if (arm_is_secure(env)) {
2961 int spd;
2962
2963 if (el == 0 && (env->cp15.sder & 1)) {
2964
2965
2966
2967
2968 return true;
2969 }
2970
2971 spd = extract32(env->cp15.mdcr_el3, 14, 2);
2972 switch (spd) {
2973 case 1:
2974
2975 case 0:
2976
2977
2978
2979
2980
2981 return true;
2982 case 2:
2983 return false;
2984 case 3:
2985 return true;
2986 }
2987 }
2988
2989 return el != 2;
2990}
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3004{
3005 if (env->aarch64) {
3006 return aa64_generate_debug_exceptions(env);
3007 } else {
3008 return aa32_generate_debug_exceptions(env);
3009 }
3010}
3011
3012
3013
3014
3015static inline bool arm_singlestep_active(CPUARMState *env)
3016{
3017 return extract32(env->cp15.mdscr_el1, 0, 1)
3018 && arm_el_is_aa64(env, arm_debug_target_el(env))
3019 && arm_generate_debug_exceptions(env);
3020}
3021
3022static inline bool arm_sctlr_b(CPUARMState *env)
3023{
3024 return
3025
3026
3027
3028
3029#ifndef CONFIG_USER_ONLY
3030 !arm_feature(env, ARM_FEATURE_V7) &&
3031#endif
3032 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3033}
3034
3035static inline uint64_t arm_sctlr(CPUARMState *env, int el)
3036{
3037 if (el == 0) {
3038
3039 return env->cp15.sctlr_el[1];
3040 } else {
3041 return env->cp15.sctlr_el[el];
3042 }
3043}
3044
3045
3046
3047static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3048{
3049
3050 if (!is_a64(env)) {
3051 return
3052#ifdef CONFIG_USER_ONLY
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064 arm_sctlr_b(env) ||
3065#endif
3066 ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
3067 } else {
3068 int cur_el = arm_current_el(env);
3069 uint64_t sctlr = arm_sctlr(env, cur_el);
3070
3071 return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0;
3072 }
3073}
3074
3075#include "exec/cpu-all.h"
3076
3077
3078
3079
3080
3081
3082FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
3083FIELD(TBFLAG_ANY, MMUIDX, 28, 3)
3084FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1)
3085FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1)
3086
3087FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
3088FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
3089
3090
3091FIELD(TBFLAG_A32, THUMB, 0, 1)
3092FIELD(TBFLAG_A32, VECLEN, 1, 3)
3093FIELD(TBFLAG_A32, VECSTRIDE, 4, 2)
3094FIELD(TBFLAG_A32, VFPEN, 7, 1)
3095FIELD(TBFLAG_A32, CONDEXEC, 8, 8)
3096FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
3097
3098
3099
3100FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2)
3101
3102
3103
3104
3105FIELD(TBFLAG_A32, NS, 19, 1)
3106
3107FIELD(TBFLAG_A32, HANDLER, 21, 1)
3108
3109FIELD(TBFLAG_A32, STACKCHECK, 22, 1)
3110
3111
3112FIELD(TBFLAG_A64, TBII, 0, 2)
3113FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3114FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3115FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3116FIELD(TBFLAG_A64, BT, 9, 1)
3117FIELD(TBFLAG_A64, BTYPE, 10, 2)
3118FIELD(TBFLAG_A64, TBID, 12, 2)
3119
3120static inline bool bswap_code(bool sctlr_b)
3121{
3122#ifdef CONFIG_USER_ONLY
3123
3124
3125
3126
3127 return
3128#ifdef TARGET_WORDS_BIGENDIAN
3129 1 ^
3130#endif
3131 sctlr_b;
3132#else
3133
3134
3135
3136 return 0;
3137#endif
3138}
3139
3140#ifdef CONFIG_USER_ONLY
3141static inline bool arm_cpu_bswap_data(CPUARMState *env)
3142{
3143 return
3144#ifdef TARGET_WORDS_BIGENDIAN
3145 1 ^
3146#endif
3147 arm_cpu_data_is_big_endian(env);
3148}
3149#endif
3150
3151void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3152 target_ulong *cs_base, uint32_t *flags);
3153
3154enum {
3155 QEMU_PSCI_CONDUIT_DISABLED = 0,
3156 QEMU_PSCI_CONDUIT_SMC = 1,
3157 QEMU_PSCI_CONDUIT_HVC = 2,
3158};
3159
3160#ifndef CONFIG_USER_ONLY
3161
3162static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3163{
3164 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3165}
3166
3167
3168
3169
3170
3171static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3172{
3173 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3174}
3175#endif
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3188 void *opaque);
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3200 *opaque);
3201
3202
3203
3204
3205
3206static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3207{
3208 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3209}
3210
3211
3212
3213
3214
3215static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3216{
3217 return &env->vfp.zregs[regno].d[0];
3218}
3219
3220
3221
3222
3223
3224static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3225{
3226 return &env->vfp.zregs[regno].d[0];
3227}
3228
3229
3230extern const uint64_t pred_esz_masks[4];
3231
3232
3233
3234
3235static inline bool isar_feature_thumb_div(const ARMISARegisters *id)
3236{
3237 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3238}
3239
3240static inline bool isar_feature_arm_div(const ARMISARegisters *id)
3241{
3242 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3243}
3244
3245static inline bool isar_feature_jazelle(const ARMISARegisters *id)
3246{
3247 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3248}
3249
3250static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3251{
3252 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3253}
3254
3255static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3256{
3257 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3258}
3259
3260static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3261{
3262 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3263}
3264
3265static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3266{
3267 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3268}
3269
3270static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3271{
3272 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3273}
3274
3275static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3276{
3277 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3278}
3279
3280static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3281{
3282 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3283}
3284
3285static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3286{
3287 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3288}
3289
3290static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3291{
3292 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3293}
3294
3295static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3296{
3297 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3298}
3299
3300static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3301{
3302 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3303}
3304
3305static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3306{
3307 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3308}
3309
3310static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3311{
3312
3313
3314
3315
3316
3317 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3318}
3319
3320
3321
3322
3323
3324
3325static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3326{
3327 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
3328}
3329
3330static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3331{
3332 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
3333}
3334
3335static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3336{
3337 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;
3338}
3339
3340static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3341{
3342 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;
3343}
3344
3345static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3346{
3347 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;
3348}
3349
3350static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3351{
3352 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
3353}
3354
3355
3356
3357
3358static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
3359{
3360 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
3361}
3362
3363static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
3364{
3365 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
3366}
3367
3368static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
3369{
3370 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
3371}
3372
3373static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
3374{
3375 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
3376}
3377
3378static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
3379{
3380 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
3381}
3382
3383static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
3384{
3385 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
3386}
3387
3388static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
3389{
3390 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
3391}
3392
3393static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
3394{
3395 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
3396}
3397
3398static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
3399{
3400 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
3401}
3402
3403static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
3404{
3405 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
3406}
3407
3408static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
3409{
3410 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
3411}
3412
3413static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
3414{
3415 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
3416}
3417
3418static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
3419{
3420 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
3421}
3422
3423static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
3424{
3425 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
3426}
3427
3428static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
3429{
3430 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
3431}
3432
3433static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
3434{
3435 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
3436}
3437
3438static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
3439{
3440 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
3441}
3442
3443static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
3444{
3445
3446
3447
3448
3449
3450
3451 return (id->id_aa64isar1 &
3452 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
3453 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
3454 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
3455 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
3456}
3457
3458static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
3459{
3460 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
3461}
3462
3463static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
3464{
3465 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
3466}
3467
3468static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
3469{
3470 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
3471}
3472
3473static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
3474{
3475
3476 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3477}
3478
3479static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
3480{
3481 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
3482}
3483
3484static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
3485{
3486 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
3487}
3488
3489static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
3490{
3491 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
3492}
3493
3494static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
3495{
3496 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
3497}
3498
3499
3500
3501
3502#define cpu_isar_feature(name, cpu) \
3503 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
3504
3505#endif
3506