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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "cpu.h"
24#include "internal.h"
25#include "kvm_mips.h"
26#include "qemu-common.h"
27#include "sysemu/kvm.h"
28#include "exec/exec-all.h"
29
30
31static void mips_cpu_set_pc(CPUState *cs, vaddr value)
32{
33 MIPSCPU *cpu = MIPS_CPU(cs);
34 CPUMIPSState *env = &cpu->env;
35
36 env->active_tc.PC = value & ~(target_ulong)1;
37 if (value & 1) {
38 env->hflags |= MIPS_HFLAG_M16;
39 } else {
40 env->hflags &= ~(MIPS_HFLAG_M16);
41 }
42}
43
44static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
45{
46 MIPSCPU *cpu = MIPS_CPU(cs);
47 CPUMIPSState *env = &cpu->env;
48
49 env->active_tc.PC = tb->pc;
50 env->hflags &= ~MIPS_HFLAG_BMASK;
51 env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
52}
53
54static bool mips_cpu_has_work(CPUState *cs)
55{
56 MIPSCPU *cpu = MIPS_CPU(cs);
57 CPUMIPSState *env = &cpu->env;
58 bool has_work = false;
59
60
61
62
63 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
64 cpu_mips_hw_interrupts_pending(env)) {
65 if (cpu_mips_hw_interrupts_enabled(env) ||
66 (env->insn_flags & ISA_MIPS32R6)) {
67 has_work = true;
68 }
69 }
70
71
72 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
73
74
75 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
76 has_work = true;
77 }
78
79 if (!mips_vpe_active(env)) {
80 has_work = false;
81 }
82 }
83
84 if (env->CP0_Config5 & (1 << CP0C5_VP)) {
85 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
86 has_work = true;
87 }
88 if (!mips_vp_active(env)) {
89 has_work = false;
90 }
91 }
92 return has_work;
93}
94
95
96static void mips_cpu_reset(CPUState *s)
97{
98 MIPSCPU *cpu = MIPS_CPU(s);
99 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
100 CPUMIPSState *env = &cpu->env;
101
102 mcc->parent_reset(s);
103
104 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
105
106 cpu_state_reset(env);
107
108#ifndef CONFIG_USER_ONLY
109 if (kvm_enabled()) {
110 kvm_mips_reset_vcpu(cpu);
111 }
112#endif
113}
114
115static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
116 MIPSCPU *cpu = MIPS_CPU(s);
117 CPUMIPSState *env = &cpu->env;
118
119 if (!(env->insn_flags & ISA_NANOMIPS32)) {
120#ifdef TARGET_WORDS_BIGENDIAN
121 info->print_insn = print_insn_big_mips;
122#else
123 info->print_insn = print_insn_little_mips;
124#endif
125 } else {
126#if defined(CONFIG_NANOMIPS_DIS)
127 info->print_insn = print_insn_nanomips;
128#endif
129 }
130}
131
132static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
133{
134 CPUState *cs = CPU(dev);
135 MIPSCPU *cpu = MIPS_CPU(dev);
136 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
137 Error *local_err = NULL;
138
139 cpu_exec_realizefn(cs, &local_err);
140 if (local_err != NULL) {
141 error_propagate(errp, local_err);
142 return;
143 }
144
145 cpu_mips_realize_env(&cpu->env);
146
147 cpu_reset(cs);
148 qemu_init_vcpu(cs);
149
150 mcc->parent_realize(dev, errp);
151}
152
153static void mips_cpu_initfn(Object *obj)
154{
155 CPUState *cs = CPU(obj);
156 MIPSCPU *cpu = MIPS_CPU(obj);
157 CPUMIPSState *env = &cpu->env;
158 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
159
160 cs->env_ptr = env;
161 env->cpu_model = mcc->cpu_def;
162}
163
164static char *mips_cpu_type_name(const char *cpu_model)
165{
166 return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
167}
168
169static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
170{
171 ObjectClass *oc;
172 char *typename;
173
174 typename = mips_cpu_type_name(cpu_model);
175 oc = object_class_by_name(typename);
176 g_free(typename);
177 return oc;
178}
179
180static void mips_cpu_class_init(ObjectClass *c, void *data)
181{
182 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
183 CPUClass *cc = CPU_CLASS(c);
184 DeviceClass *dc = DEVICE_CLASS(c);
185
186 device_class_set_parent_realize(dc, mips_cpu_realizefn,
187 &mcc->parent_realize);
188 mcc->parent_reset = cc->reset;
189 cc->reset = mips_cpu_reset;
190
191 cc->class_by_name = mips_cpu_class_by_name;
192 cc->has_work = mips_cpu_has_work;
193 cc->do_interrupt = mips_cpu_do_interrupt;
194 cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
195 cc->dump_state = mips_cpu_dump_state;
196 cc->set_pc = mips_cpu_set_pc;
197 cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
198 cc->gdb_read_register = mips_cpu_gdb_read_register;
199 cc->gdb_write_register = mips_cpu_gdb_write_register;
200#ifdef CONFIG_USER_ONLY
201 cc->handle_mmu_fault = mips_cpu_handle_mmu_fault;
202#else
203 cc->do_unassigned_access = mips_cpu_unassigned_access;
204 cc->do_unaligned_access = mips_cpu_do_unaligned_access;
205 cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
206 cc->vmsd = &vmstate_mips_cpu;
207#endif
208 cc->disas_set_info = mips_cpu_disas_set_info;
209#ifdef CONFIG_TCG
210 cc->tcg_initialize = mips_tcg_init;
211#endif
212
213 cc->gdb_num_core_regs = 73;
214 cc->gdb_stop_before_watchpoint = true;
215}
216
217static const TypeInfo mips_cpu_type_info = {
218 .name = TYPE_MIPS_CPU,
219 .parent = TYPE_CPU,
220 .instance_size = sizeof(MIPSCPU),
221 .instance_init = mips_cpu_initfn,
222 .abstract = true,
223 .class_size = sizeof(MIPSCPUClass),
224 .class_init = mips_cpu_class_init,
225};
226
227static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
228{
229 MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
230 mcc->cpu_def = data;
231}
232
233static void mips_register_cpudef_type(const struct mips_def_t *def)
234{
235 char *typename = mips_cpu_type_name(def->name);
236 TypeInfo ti = {
237 .name = typename,
238 .parent = TYPE_MIPS_CPU,
239 .class_init = mips_cpu_cpudef_class_init,
240 .class_data = (void *)def,
241 };
242
243 type_register(&ti);
244 g_free(typename);
245}
246
247static void mips_cpu_register_types(void)
248{
249 int i;
250
251 type_register_static(&mips_cpu_type_info);
252 for (i = 0; i < mips_defs_number; i++) {
253 mips_register_cpudef_type(&mips_defs[i]);
254 }
255}
256
257type_init(mips_cpu_register_types)
258
