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21#ifndef S390X_CPU_H
22#define S390X_CPU_H
23
24#include "qemu-common.h"
25#include "cpu-qom.h"
26#include "cpu_models.h"
27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE_UNAME "S390X"
31
32#define CPUArchState struct CPUS390XState
33
34#include "exec/cpu-defs.h"
35
36
37#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
38
39#define TARGET_PAGE_BITS 12
40
41#define TARGET_PHYS_ADDR_SPACE_BITS 64
42#define TARGET_VIRT_ADDR_SPACE_BITS 64
43
44#include "exec/cpu-all.h"
45
46#define NB_MMU_MODES 4
47#define TARGET_INSN_START_EXTRA_WORDS 1
48
49#define MMU_MODE0_SUFFIX _primary
50#define MMU_MODE1_SUFFIX _secondary
51#define MMU_MODE2_SUFFIX _home
52#define MMU_MODE3_SUFFIX _real
53
54#define MMU_USER_IDX 0
55
56#define S390_MAX_CPUS 248
57
58typedef struct PSW {
59 uint64_t mask;
60 uint64_t addr;
61} PSW;
62
63struct CPUS390XState {
64 uint64_t regs[16];
65
66
67
68
69 CPU_DoubleU vregs[32][2];
70 uint32_t aregs[16];
71 uint8_t riccb[64];
72 uint64_t gscb[4];
73 uint64_t etoken;
74 uint64_t etoken_extension;
75
76
77 struct {} start_initial_reset_fields;
78
79 uint32_t fpc;
80 uint32_t cc_op;
81 bool bpbc;
82
83 float_status fpu_status;
84
85
86 uint64_t retxl;
87
88 PSW psw;
89
90 S390CrashReason crash_reason;
91
92 uint64_t cc_src;
93 uint64_t cc_dst;
94 uint64_t cc_vr;
95
96 uint64_t ex_value;
97
98 uint64_t __excp_addr;
99 uint64_t psa;
100
101 uint32_t int_pgm_code;
102 uint32_t int_pgm_ilen;
103
104 uint32_t int_svc_code;
105 uint32_t int_svc_ilen;
106
107 uint64_t per_address;
108 uint16_t per_perc_atmid;
109
110 uint64_t cregs[16];
111
112 int pending_int;
113 uint16_t external_call_addr;
114 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
115
116 uint64_t ckc;
117 uint64_t cputm;
118 uint32_t todpr;
119
120 uint64_t pfault_token;
121 uint64_t pfault_compare;
122 uint64_t pfault_select;
123
124 uint64_t gbea;
125 uint64_t pp;
126
127
128 struct {} end_reset_fields;
129
130 CPU_COMMON
131
132#if !defined(CONFIG_USER_ONLY)
133 uint32_t core_id;
134 uint64_t cpuid;
135#endif
136
137 QEMUTimer *tod_timer;
138
139 QEMUTimer *cpu_timer;
140
141
142
143
144
145
146
147
148
149 uint8_t cpu_state;
150
151
152 uint8_t sigp_order;
153
154};
155
156static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
157{
158 return &cs->vregs[nr][0];
159}
160
161
162
163
164
165
166
167struct S390CPU {
168
169 CPUState parent_obj;
170
171
172 CPUS390XState env;
173 S390CPUModel *model;
174
175 void *irqstate;
176 uint32_t irqstate_saved_size;
177};
178
179static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
180{
181 return container_of(env, S390CPU, env);
182}
183
184#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
185
186#define ENV_OFFSET offsetof(S390CPU, env)
187
188#ifndef CONFIG_USER_ONLY
189extern const struct VMStateDescription vmstate_s390_cpu;
190#endif
191
192
193#define HIGH_ORDER_BIT 0x80000000
194
195
196
197#define PGM_OPERATION 0x0001
198#define PGM_PRIVILEGED 0x0002
199#define PGM_EXECUTE 0x0003
200#define PGM_PROTECTION 0x0004
201#define PGM_ADDRESSING 0x0005
202#define PGM_SPECIFICATION 0x0006
203#define PGM_DATA 0x0007
204#define PGM_FIXPT_OVERFLOW 0x0008
205#define PGM_FIXPT_DIVIDE 0x0009
206#define PGM_DEC_OVERFLOW 0x000a
207#define PGM_DEC_DIVIDE 0x000b
208#define PGM_HFP_EXP_OVERFLOW 0x000c
209#define PGM_HFP_EXP_UNDERFLOW 0x000d
210#define PGM_HFP_SIGNIFICANCE 0x000e
211#define PGM_HFP_DIVIDE 0x000f
212#define PGM_SEGMENT_TRANS 0x0010
213#define PGM_PAGE_TRANS 0x0011
214#define PGM_TRANS_SPEC 0x0012
215#define PGM_SPECIAL_OP 0x0013
216#define PGM_OPERAND 0x0015
217#define PGM_TRACE_TABLE 0x0016
218#define PGM_SPACE_SWITCH 0x001c
219#define PGM_HFP_SQRT 0x001d
220#define PGM_PC_TRANS_SPEC 0x001f
221#define PGM_AFX_TRANS 0x0020
222#define PGM_ASX_TRANS 0x0021
223#define PGM_LX_TRANS 0x0022
224#define PGM_EX_TRANS 0x0023
225#define PGM_PRIM_AUTH 0x0024
226#define PGM_SEC_AUTH 0x0025
227#define PGM_ALET_SPEC 0x0028
228#define PGM_ALEN_SPEC 0x0029
229#define PGM_ALE_SEQ 0x002a
230#define PGM_ASTE_VALID 0x002b
231#define PGM_ASTE_SEQ 0x002c
232#define PGM_EXT_AUTH 0x002d
233#define PGM_STACK_FULL 0x0030
234#define PGM_STACK_EMPTY 0x0031
235#define PGM_STACK_SPEC 0x0032
236#define PGM_STACK_TYPE 0x0033
237#define PGM_STACK_OP 0x0034
238#define PGM_ASCE_TYPE 0x0038
239#define PGM_REG_FIRST_TRANS 0x0039
240#define PGM_REG_SEC_TRANS 0x003a
241#define PGM_REG_THIRD_TRANS 0x003b
242#define PGM_MONITOR 0x0040
243#define PGM_PER 0x0080
244#define PGM_CRYPTO 0x0119
245
246
247#define EXT_INTERRUPT_KEY 0x0040
248#define EXT_CLOCK_COMP 0x1004
249#define EXT_CPU_TIMER 0x1005
250#define EXT_MALFUNCTION 0x1200
251#define EXT_EMERGENCY 0x1201
252#define EXT_EXTERNAL_CALL 0x1202
253#define EXT_ETR 0x1406
254#define EXT_SERVICE 0x2401
255#define EXT_VIRTIO 0x2603
256
257
258#undef PSW_MASK_PER
259#undef PSW_MASK_UNUSED_2
260#undef PSW_MASK_UNUSED_3
261#undef PSW_MASK_DAT
262#undef PSW_MASK_IO
263#undef PSW_MASK_EXT
264#undef PSW_MASK_KEY
265#undef PSW_SHIFT_KEY
266#undef PSW_MASK_MCHECK
267#undef PSW_MASK_WAIT
268#undef PSW_MASK_PSTATE
269#undef PSW_MASK_ASC
270#undef PSW_SHIFT_ASC
271#undef PSW_MASK_CC
272#undef PSW_MASK_PM
273#undef PSW_SHIFT_MASK_PM
274#undef PSW_MASK_64
275#undef PSW_MASK_32
276#undef PSW_MASK_ESA_ADDR
277
278#define PSW_MASK_PER 0x4000000000000000ULL
279#define PSW_MASK_UNUSED_2 0x2000000000000000ULL
280#define PSW_MASK_UNUSED_3 0x1000000000000000ULL
281#define PSW_MASK_DAT 0x0400000000000000ULL
282#define PSW_MASK_IO 0x0200000000000000ULL
283#define PSW_MASK_EXT 0x0100000000000000ULL
284#define PSW_MASK_KEY 0x00F0000000000000ULL
285#define PSW_SHIFT_KEY 52
286#define PSW_MASK_MCHECK 0x0004000000000000ULL
287#define PSW_MASK_WAIT 0x0002000000000000ULL
288#define PSW_MASK_PSTATE 0x0001000000000000ULL
289#define PSW_MASK_ASC 0x0000C00000000000ULL
290#define PSW_SHIFT_ASC 46
291#define PSW_MASK_CC 0x0000300000000000ULL
292#define PSW_MASK_PM 0x00000F0000000000ULL
293#define PSW_SHIFT_MASK_PM 40
294#define PSW_MASK_64 0x0000000100000000ULL
295#define PSW_MASK_32 0x0000000080000000ULL
296#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
297
298#undef PSW_ASC_PRIMARY
299#undef PSW_ASC_ACCREG
300#undef PSW_ASC_SECONDARY
301#undef PSW_ASC_HOME
302
303#define PSW_ASC_PRIMARY 0x0000000000000000ULL
304#define PSW_ASC_ACCREG 0x0000400000000000ULL
305#define PSW_ASC_SECONDARY 0x0000800000000000ULL
306#define PSW_ASC_HOME 0x0000C00000000000ULL
307
308
309#define AS_PRIMARY 0
310#define AS_ACCREG 1
311#define AS_SECONDARY 2
312#define AS_HOME 3
313
314
315
316#define FLAG_MASK_PSW_SHIFT 31
317#define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
318#define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT)
319#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
320#define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
321#define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
322#define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
323#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
324 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
325
326
327#define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
328#define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)
329
330
331#define CR0_LOWPROT 0x0000000010000000ULL
332#define CR0_SECONDARY 0x0000000004000000ULL
333#define CR0_EDAT 0x0000000000800000ULL
334#define CR0_AFP 0x0000000000040000ULL
335#define CR0_VECTOR 0x0000000000020000ULL
336#define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
337#define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
338#define CR0_CKC_SC 0x0000000000000800ULL
339#define CR0_CPU_TIMER_SC 0x0000000000000400ULL
340#define CR0_SERVICE_SC 0x0000000000000200ULL
341
342
343#define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL
344
345
346#define MMU_PRIMARY_IDX 0
347#define MMU_SECONDARY_IDX 1
348#define MMU_HOME_IDX 2
349#define MMU_REAL_IDX 3
350
351static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
352{
353 if (!(env->psw.mask & PSW_MASK_DAT)) {
354 return MMU_REAL_IDX;
355 }
356
357 switch (env->psw.mask & PSW_MASK_ASC) {
358 case PSW_ASC_PRIMARY:
359 return MMU_PRIMARY_IDX;
360 case PSW_ASC_SECONDARY:
361 return MMU_SECONDARY_IDX;
362 case PSW_ASC_HOME:
363 return MMU_HOME_IDX;
364 case PSW_ASC_ACCREG:
365
366 default:
367 abort();
368 }
369}
370
371static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
372 target_ulong *cs_base, uint32_t *flags)
373{
374 *pc = env->psw.addr;
375 *cs_base = env->ex_value;
376 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
377 if (env->cregs[0] & CR0_AFP) {
378 *flags |= FLAG_MASK_AFP;
379 }
380 if (env->cregs[0] & CR0_VECTOR) {
381 *flags |= FLAG_MASK_VECTOR;
382 }
383}
384
385
386#define PER_CR9_EVENT_BRANCH 0x80000000
387#define PER_CR9_EVENT_IFETCH 0x40000000
388#define PER_CR9_EVENT_STORE 0x20000000
389#define PER_CR9_EVENT_STORE_REAL 0x08000000
390#define PER_CR9_EVENT_NULLIFICATION 0x01000000
391#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
392#define PER_CR9_CONTROL_ALTERATION 0x00200000
393
394
395#define PER_CODE_EVENT_BRANCH 0x8000
396#define PER_CODE_EVENT_IFETCH 0x4000
397#define PER_CODE_EVENT_STORE 0x2000
398#define PER_CODE_EVENT_STORE_REAL 0x0800
399#define PER_CODE_EVENT_NULLIFICATION 0x0100
400
401#define EXCP_EXT 1
402#define EXCP_SVC 2
403#define EXCP_PGM 3
404#define EXCP_RESTART 4
405#define EXCP_STOP 5
406#define EXCP_IO 7
407#define EXCP_MCHK 8
408
409#define INTERRUPT_EXT_CPU_TIMER (1 << 3)
410#define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
411#define INTERRUPT_EXTERNAL_CALL (1 << 5)
412#define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
413#define INTERRUPT_RESTART (1 << 7)
414#define INTERRUPT_STOP (1 << 8)
415
416
417#define S390_PSWM_REGNUM 0
418#define S390_PSWA_REGNUM 1
419
420#define S390_R0_REGNUM 2
421#define S390_R1_REGNUM 3
422#define S390_R2_REGNUM 4
423#define S390_R3_REGNUM 5
424#define S390_R4_REGNUM 6
425#define S390_R5_REGNUM 7
426#define S390_R6_REGNUM 8
427#define S390_R7_REGNUM 9
428#define S390_R8_REGNUM 10
429#define S390_R9_REGNUM 11
430#define S390_R10_REGNUM 12
431#define S390_R11_REGNUM 13
432#define S390_R12_REGNUM 14
433#define S390_R13_REGNUM 15
434#define S390_R14_REGNUM 16
435#define S390_R15_REGNUM 17
436
437#define S390_NUM_CORE_REGS 18
438
439static inline void setcc(S390CPU *cpu, uint64_t cc)
440{
441 CPUS390XState *env = &cpu->env;
442
443 env->psw.mask &= ~(3ull << 44);
444 env->psw.mask |= (cc & 3) << 44;
445 env->cc_op = cc;
446}
447
448
449#define STSI_R0_FC_MASK 0x00000000f0000000ULL
450#define STSI_R0_FC_CURRENT 0x0000000000000000ULL
451#define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL
452#define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL
453#define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL
454#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
455#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
456#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
457#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
458
459
460typedef struct SysIB_111 {
461 uint8_t res1[32];
462 uint8_t manuf[16];
463 uint8_t type[4];
464 uint8_t res2[12];
465 uint8_t model[16];
466 uint8_t sequence[16];
467 uint8_t plant[4];
468 uint8_t res3[3996];
469} SysIB_111;
470QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
471
472
473typedef struct SysIB_121 {
474 uint8_t res1[80];
475 uint8_t sequence[16];
476 uint8_t plant[4];
477 uint8_t res2[2];
478 uint16_t cpu_addr;
479 uint8_t res3[3992];
480} SysIB_121;
481QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
482
483
484typedef struct SysIB_122 {
485 uint8_t res1[32];
486 uint32_t capability;
487 uint16_t total_cpus;
488 uint16_t conf_cpus;
489 uint16_t standby_cpus;
490 uint16_t reserved_cpus;
491 uint16_t adjustments[2026];
492} SysIB_122;
493QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
494
495
496typedef struct SysIB_221 {
497 uint8_t res1[80];
498 uint8_t sequence[16];
499 uint8_t plant[4];
500 uint16_t cpu_id;
501 uint16_t cpu_addr;
502 uint8_t res3[3992];
503} SysIB_221;
504QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
505
506
507typedef struct SysIB_222 {
508 uint8_t res1[32];
509 uint16_t lpar_num;
510 uint8_t res2;
511 uint8_t lcpuc;
512 uint16_t total_cpus;
513 uint16_t conf_cpus;
514 uint16_t standby_cpus;
515 uint16_t reserved_cpus;
516 uint8_t name[8];
517 uint32_t caf;
518 uint8_t res3[16];
519 uint16_t dedicated_cpus;
520 uint16_t shared_cpus;
521 uint8_t res4[4020];
522} SysIB_222;
523QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
524
525
526typedef struct SysIB_322 {
527 uint8_t res1[31];
528 uint8_t count;
529 struct {
530 uint8_t res2[4];
531 uint16_t total_cpus;
532 uint16_t conf_cpus;
533 uint16_t standby_cpus;
534 uint16_t reserved_cpus;
535 uint8_t name[8];
536 uint32_t caf;
537 uint8_t cpi[16];
538 uint8_t res5[3];
539 uint8_t ext_name_encoding;
540 uint32_t res3;
541 uint8_t uuid[16];
542 } vm[8];
543 uint8_t res4[1504];
544 uint8_t ext_names[8][256];
545} SysIB_322;
546QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
547
548typedef union SysIB {
549 SysIB_111 sysib_111;
550 SysIB_121 sysib_121;
551 SysIB_122 sysib_122;
552 SysIB_221 sysib_221;
553 SysIB_222 sysib_222;
554 SysIB_322 sysib_322;
555} SysIB;
556QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
557
558
559#define ASCE_ORIGIN (~0xfffULL)
560#define ASCE_SUBSPACE 0x200
561#define ASCE_PRIVATE_SPACE 0x100
562#define ASCE_ALT_EVENT 0x80
563#define ASCE_SPACE_SWITCH 0x40
564#define ASCE_REAL_SPACE 0x20
565#define ASCE_TYPE_MASK 0x0c
566#define ASCE_TYPE_REGION1 0x0c
567#define ASCE_TYPE_REGION2 0x08
568#define ASCE_TYPE_REGION3 0x04
569#define ASCE_TYPE_SEGMENT 0x00
570#define ASCE_TABLE_LENGTH 0x03
571
572#define REGION_ENTRY_ORIGIN (~0xfffULL)
573#define REGION_ENTRY_RO 0x200
574#define REGION_ENTRY_TF 0xc0
575#define REGION_ENTRY_INV 0x20
576#define REGION_ENTRY_TYPE_MASK 0x0c
577#define REGION_ENTRY_TYPE_R1 0x0c
578#define REGION_ENTRY_TYPE_R2 0x08
579#define REGION_ENTRY_TYPE_R3 0x04
580#define REGION_ENTRY_LENGTH 0x03
581
582#define SEGMENT_ENTRY_ORIGIN (~0x7ffULL)
583#define SEGMENT_ENTRY_FC 0x400
584#define SEGMENT_ENTRY_RO 0x200
585#define SEGMENT_ENTRY_INV 0x20
586
587#define VADDR_PX 0xff000
588
589#define PAGE_RO 0x200
590#define PAGE_INVALID 0x400
591#define PAGE_RES0 0x800
592
593#define SK_C (0x1 << 1)
594#define SK_R (0x1 << 2)
595#define SK_F (0x1 << 3)
596#define SK_ACC_MASK (0xf << 4)
597
598
599#define SIGP_SENSE 0x01
600#define SIGP_EXTERNAL_CALL 0x02
601#define SIGP_EMERGENCY 0x03
602#define SIGP_START 0x04
603#define SIGP_STOP 0x05
604#define SIGP_RESTART 0x06
605#define SIGP_STOP_STORE_STATUS 0x09
606#define SIGP_INITIAL_CPU_RESET 0x0b
607#define SIGP_CPU_RESET 0x0c
608#define SIGP_SET_PREFIX 0x0d
609#define SIGP_STORE_STATUS_ADDR 0x0e
610#define SIGP_SET_ARCH 0x12
611#define SIGP_COND_EMERGENCY 0x13
612#define SIGP_SENSE_RUNNING 0x15
613#define SIGP_STORE_ADTL_STATUS 0x17
614
615
616#define SIGP_CC_ORDER_CODE_ACCEPTED 0
617#define SIGP_CC_STATUS_STORED 1
618#define SIGP_CC_BUSY 2
619#define SIGP_CC_NOT_OPERATIONAL 3
620
621
622#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
623#define SIGP_STAT_NOT_RUNNING 0x00000400UL
624#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
625#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
626#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
627#define SIGP_STAT_STOPPED 0x00000040UL
628#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
629#define SIGP_STAT_CHECK_STOP 0x00000010UL
630#define SIGP_STAT_INOPERATIVE 0x00000004UL
631#define SIGP_STAT_INVALID_ORDER 0x00000002UL
632#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
633
634
635#define SIGP_MODE_ESA_S390 0
636#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
637#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
638
639
640#define SIGP_ORDER_MASK 0x000000ff
641
642
643
644
645#define MCIC_SC_SD 0x8000000000000000ULL
646#define MCIC_SC_PD 0x4000000000000000ULL
647#define MCIC_SC_SR 0x2000000000000000ULL
648#define MCIC_SC_CD 0x0800000000000000ULL
649#define MCIC_SC_ED 0x0400000000000000ULL
650#define MCIC_SC_DG 0x0100000000000000ULL
651#define MCIC_SC_W 0x0080000000000000ULL
652#define MCIC_SC_CP 0x0040000000000000ULL
653#define MCIC_SC_SP 0x0020000000000000ULL
654#define MCIC_SC_CK 0x0010000000000000ULL
655
656
657#define MCIC_SCM_B 0x0002000000000000ULL
658#define MCIC_SCM_DA 0x0000000020000000ULL
659#define MCIC_SCM_AP 0x0000000000080000ULL
660
661
662#define MCIC_SE_SE 0x0000800000000000ULL
663#define MCIC_SE_SC 0x0000400000000000ULL
664#define MCIC_SE_KE 0x0000200000000000ULL
665#define MCIC_SE_DS 0x0000100000000000ULL
666#define MCIC_SE_IE 0x0000000080000000ULL
667
668
669#define MCIC_VB_WP 0x0000080000000000ULL
670#define MCIC_VB_MS 0x0000040000000000ULL
671#define MCIC_VB_PM 0x0000020000000000ULL
672#define MCIC_VB_IA 0x0000010000000000ULL
673#define MCIC_VB_FA 0x0000008000000000ULL
674#define MCIC_VB_VR 0x0000004000000000ULL
675#define MCIC_VB_EC 0x0000002000000000ULL
676#define MCIC_VB_FP 0x0000001000000000ULL
677#define MCIC_VB_GR 0x0000000800000000ULL
678#define MCIC_VB_CR 0x0000000400000000ULL
679#define MCIC_VB_ST 0x0000000100000000ULL
680#define MCIC_VB_AR 0x0000000040000000ULL
681#define MCIC_VB_GS 0x0000000008000000ULL
682#define MCIC_VB_PR 0x0000000000200000ULL
683#define MCIC_VB_FC 0x0000000000100000ULL
684#define MCIC_VB_CT 0x0000000000020000ULL
685#define MCIC_VB_CC 0x0000000000010000ULL
686
687static inline uint64_t s390_build_validity_mcic(void)
688{
689 uint64_t mcic;
690
691
692
693
694
695 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
696 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
697 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
698 if (s390_has_feat(S390_FEAT_VECTOR)) {
699 mcic |= MCIC_VB_VR;
700 }
701 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
702 mcic |= MCIC_VB_GS;
703 }
704 return mcic;
705}
706
707static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
708{
709 cpu_reset(cs);
710}
711
712static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
713{
714 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
715
716 scc->cpu_reset(cs);
717}
718
719static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg)
720{
721 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
722
723 scc->initial_cpu_reset(cs);
724}
725
726static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg)
727{
728 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
729
730 scc->load_normal(cs);
731}
732
733
734
735void s390_crypto_reset(void);
736int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
737void s390_cmma_reset(void);
738void s390_enable_css_support(S390CPU *cpu);
739int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
740 int vq, bool assign);
741#ifndef CONFIG_USER_ONLY
742unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
743#else
744static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
745{
746 return 0;
747}
748#endif
749static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
750{
751 return cpu->env.cpu_state;
752}
753
754
755
756void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
757#define cpu_list s390_cpu_list
758void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
759 const S390FeatInit feat_init);
760
761
762
763#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
764#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
765#define CPU_RESOLVING_TYPE TYPE_S390_CPU
766
767
768
769
770int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
771#define cpu_signal_handler cpu_s390x_signal_handler
772
773
774
775void s390_crw_mchk(void);
776void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
777 uint32_t io_int_parm, uint32_t io_int_word);
778
779#define ILEN_AUTO 0xff
780#define RA_IGNORED 0
781void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen,
782 uintptr_t ra);
783
784void s390_sclp_extint(uint32_t parm);
785
786
787int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
788 int len, bool is_write);
789#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
790 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
791#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
792 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
793#define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \
794 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
795#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
796 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
797void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
798
799
800
801int s390_cpu_restart(S390CPU *cpu);
802void s390_init_sigp(void);
803
804
805
806S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
807
808#endif
809