1#ifndef SPARC_CPU_H
2#define SPARC_CPU_H
3
4#include "qemu-common.h"
5#include "qemu/bswap.h"
6#include "cpu-qom.h"
7
8#define ALIGNED_ONLY
9
10#if !defined(TARGET_SPARC64)
11#define TARGET_LONG_BITS 32
12#define TARGET_DPREGS 16
13#define TARGET_PAGE_BITS 12
14#define TARGET_PHYS_ADDR_SPACE_BITS 36
15#define TARGET_VIRT_ADDR_SPACE_BITS 32
16#else
17#define TARGET_LONG_BITS 64
18#define TARGET_DPREGS 32
19#define TARGET_PAGE_BITS 13
20#define TARGET_PHYS_ADDR_SPACE_BITS 41
21# ifdef TARGET_ABI32
22# define TARGET_VIRT_ADDR_SPACE_BITS 32
23# else
24# define TARGET_VIRT_ADDR_SPACE_BITS 44
25# endif
26#endif
27
28#define CPUArchState struct CPUSPARCState
29
30#include "exec/cpu-defs.h"
31
32
33
34
35#ifndef TARGET_SPARC64
36#define TT_TFAULT 0x01
37#define TT_ILL_INSN 0x02
38#define TT_PRIV_INSN 0x03
39#define TT_NFPU_INSN 0x04
40#define TT_WIN_OVF 0x05
41#define TT_WIN_UNF 0x06
42#define TT_UNALIGNED 0x07
43#define TT_FP_EXCP 0x08
44#define TT_DFAULT 0x09
45#define TT_TOVF 0x0a
46#define TT_EXTINT 0x10
47#define TT_CODE_ACCESS 0x21
48#define TT_UNIMP_FLUSH 0x25
49#define TT_DATA_ACCESS 0x29
50#define TT_DIV_ZERO 0x2a
51#define TT_NCP_INSN 0x24
52#define TT_TRAP 0x80
53#else
54#define TT_POWER_ON_RESET 0x01
55#define TT_TFAULT 0x08
56#define TT_CODE_ACCESS 0x0a
57#define TT_ILL_INSN 0x10
58#define TT_UNIMP_FLUSH TT_ILL_INSN
59#define TT_PRIV_INSN 0x11
60#define TT_NFPU_INSN 0x20
61#define TT_FP_EXCP 0x21
62#define TT_TOVF 0x23
63#define TT_CLRWIN 0x24
64#define TT_DIV_ZERO 0x28
65#define TT_DFAULT 0x30
66#define TT_DATA_ACCESS 0x32
67#define TT_UNALIGNED 0x34
68#define TT_PRIV_ACT 0x37
69#define TT_INSN_REAL_TRANSLATION_MISS 0x3e
70#define TT_DATA_REAL_TRANSLATION_MISS 0x3f
71#define TT_EXTINT 0x40
72#define TT_IVEC 0x60
73#define TT_TMISS 0x64
74#define TT_DMISS 0x68
75#define TT_DPROT 0x6c
76#define TT_SPILL 0x80
77#define TT_FILL 0xc0
78#define TT_WOTHER (1 << 5)
79#define TT_TRAP 0x100
80#define TT_HTRAP 0x180
81#endif
82
83#define PSR_NEG_SHIFT 23
84#define PSR_NEG (1 << PSR_NEG_SHIFT)
85#define PSR_ZERO_SHIFT 22
86#define PSR_ZERO (1 << PSR_ZERO_SHIFT)
87#define PSR_OVF_SHIFT 21
88#define PSR_OVF (1 << PSR_OVF_SHIFT)
89#define PSR_CARRY_SHIFT 20
90#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
91#define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
92#if !defined(TARGET_SPARC64)
93#define PSR_EF (1<<12)
94#define PSR_PIL 0xf00
95#define PSR_S (1<<7)
96#define PSR_PS (1<<6)
97#define PSR_ET (1<<5)
98#define PSR_CWP 0x1f
99#endif
100
101#define CC_SRC (env->cc_src)
102#define CC_SRC2 (env->cc_src2)
103#define CC_DST (env->cc_dst)
104#define CC_OP (env->cc_op)
105
106
107
108
109
110
111enum {
112 CC_OP_DYNAMIC,
113 CC_OP_FLAGS,
114 CC_OP_DIV,
115 CC_OP_ADD,
116 CC_OP_ADDX,
117 CC_OP_TADD,
118 CC_OP_TADDTV,
119 CC_OP_SUB,
120 CC_OP_SUBX,
121 CC_OP_TSUB,
122 CC_OP_TSUBTV,
123 CC_OP_LOGIC,
124 CC_OP_NB,
125};
126
127
128#define TBR_BASE_MASK 0xfffff000
129
130#if defined(TARGET_SPARC64)
131#define PS_TCT (1<<12)
132#define PS_IG (1<<11)
133#define PS_MG (1<<10)
134#define PS_CLE (1<<9)
135#define PS_TLE (1<<8)
136#define PS_RMO (1<<7)
137#define PS_RED (1<<5)
138#define PS_PEF (1<<4)
139#define PS_AM (1<<3)
140#define PS_PRIV (1<<2)
141#define PS_IE (1<<1)
142#define PS_AG (1<<0)
143
144#define FPRS_FEF (1<<2)
145
146#define HS_PRIV (1<<2)
147#endif
148
149
150#define FSR_RD1 (1ULL << 31)
151#define FSR_RD0 (1ULL << 30)
152#define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
153#define FSR_RD_NEAREST 0
154#define FSR_RD_ZERO FSR_RD0
155#define FSR_RD_POS FSR_RD1
156#define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
157
158#define FSR_NVM (1ULL << 27)
159#define FSR_OFM (1ULL << 26)
160#define FSR_UFM (1ULL << 25)
161#define FSR_DZM (1ULL << 24)
162#define FSR_NXM (1ULL << 23)
163#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
164
165#define FSR_NVA (1ULL << 9)
166#define FSR_OFA (1ULL << 8)
167#define FSR_UFA (1ULL << 7)
168#define FSR_DZA (1ULL << 6)
169#define FSR_NXA (1ULL << 5)
170#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
171
172#define FSR_NVC (1ULL << 4)
173#define FSR_OFC (1ULL << 3)
174#define FSR_UFC (1ULL << 2)
175#define FSR_DZC (1ULL << 1)
176#define FSR_NXC (1ULL << 0)
177#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
178
179#define FSR_FTT2 (1ULL << 16)
180#define FSR_FTT1 (1ULL << 15)
181#define FSR_FTT0 (1ULL << 14)
182
183
184#ifdef TARGET_SPARC64
185#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
186#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
187#define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
188#define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
189#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
190#else
191#define FSR_FTT_NMASK 0xfffe3fffULL
192#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
193#define FSR_LDFSR_OLDMASK 0x000fc000ULL
194#endif
195#define FSR_LDFSR_MASK 0xcfc00fffULL
196#define FSR_FTT_IEEE_EXCP (1ULL << 14)
197#define FSR_FTT_UNIMPFPOP (3ULL << 14)
198#define FSR_FTT_SEQ_ERROR (4ULL << 14)
199#define FSR_FTT_INVAL_FPR (6ULL << 14)
200
201#define FSR_FCC1_SHIFT 11
202#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
203#define FSR_FCC0_SHIFT 10
204#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
205
206
207#define MMU_E (1<<0)
208#define MMU_NF (1<<1)
209
210#define PTE_ENTRYTYPE_MASK 3
211#define PTE_ACCESS_MASK 0x1c
212#define PTE_ACCESS_SHIFT 2
213#define PTE_PPN_SHIFT 7
214#define PTE_ADDR_MASK 0xffffff00
215
216#define PG_ACCESSED_BIT 5
217#define PG_MODIFIED_BIT 6
218#define PG_CACHE_BIT 7
219
220#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
221#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
222#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
223
224
225#define MIN_NWINDOWS 3
226#define MAX_NWINDOWS 32
227
228#if !defined(TARGET_SPARC64)
229#define NB_MMU_MODES 3
230#else
231#define NB_MMU_MODES 6
232typedef struct trap_state {
233 uint64_t tpc;
234 uint64_t tnpc;
235 uint64_t tstate;
236 uint32_t tt;
237} trap_state;
238#endif
239#define TARGET_INSN_START_EXTRA_WORDS 1
240
241struct sparc_def_t {
242 const char *name;
243 target_ulong iu_version;
244 uint32_t fpu_version;
245 uint32_t mmu_version;
246 uint32_t mmu_bm;
247 uint32_t mmu_ctpr_mask;
248 uint32_t mmu_cxr_mask;
249 uint32_t mmu_sfsr_mask;
250 uint32_t mmu_trcr_mask;
251 uint32_t mxcc_version;
252 uint32_t features;
253 uint32_t nwindows;
254 uint32_t maxtl;
255};
256
257#define CPU_FEATURE_FLOAT (1 << 0)
258#define CPU_FEATURE_FLOAT128 (1 << 1)
259#define CPU_FEATURE_SWAP (1 << 2)
260#define CPU_FEATURE_MUL (1 << 3)
261#define CPU_FEATURE_DIV (1 << 4)
262#define CPU_FEATURE_FLUSH (1 << 5)
263#define CPU_FEATURE_FSQRT (1 << 6)
264#define CPU_FEATURE_FMUL (1 << 7)
265#define CPU_FEATURE_VIS1 (1 << 8)
266#define CPU_FEATURE_VIS2 (1 << 9)
267#define CPU_FEATURE_FSMULD (1 << 10)
268#define CPU_FEATURE_HYPV (1 << 11)
269#define CPU_FEATURE_CMT (1 << 12)
270#define CPU_FEATURE_GL (1 << 13)
271#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14)
272#define CPU_FEATURE_ASR17 (1 << 15)
273#define CPU_FEATURE_CACHE_CTRL (1 << 16)
274#define CPU_FEATURE_POWERDOWN (1 << 17)
275#define CPU_FEATURE_CASA (1 << 18)
276
277#ifndef TARGET_SPARC64
278#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
279 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
280 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
281 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
282#else
283#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
284 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
285 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
286 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
287 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
288 CPU_FEATURE_CASA)
289enum {
290 mmu_us_12,
291 mmu_us_3,
292 mmu_us_4,
293 mmu_sun4v,
294};
295#endif
296
297#define TTE_VALID_BIT (1ULL << 63)
298#define TTE_NFO_BIT (1ULL << 60)
299#define TTE_USED_BIT (1ULL << 41)
300#define TTE_LOCKED_BIT (1ULL << 6)
301#define TTE_SIDEEFFECT_BIT (1ULL << 3)
302#define TTE_PRIV_BIT (1ULL << 2)
303#define TTE_W_OK_BIT (1ULL << 1)
304#define TTE_GLOBAL_BIT (1ULL << 0)
305
306#define TTE_NFO_BIT_UA2005 (1ULL << 62)
307#define TTE_USED_BIT_UA2005 (1ULL << 47)
308#define TTE_LOCKED_BIT_UA2005 (1ULL << 61)
309#define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11)
310#define TTE_PRIV_BIT_UA2005 (1ULL << 8)
311#define TTE_W_OK_BIT_UA2005 (1ULL << 6)
312
313#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
314#define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
315#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
316#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
317#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
318#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
319#define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
320#define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
321
322#define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005)
323#define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005)
324#define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005)
325#define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
326#define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005)
327#define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005)
328
329#define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
330
331#define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
332#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
333
334#define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL)
335#define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL)
336#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
337
338
339#define TLB_UST1_IS_REAL_BIT (1ULL << 9)
340#define TLB_UST1_IS_SUN4V_BIT (1ULL << 10)
341
342#define SFSR_NF_BIT (1ULL << 24)
343#define SFSR_TM_BIT (1ULL << 15)
344#define SFSR_FT_VA_IMMU_BIT (1ULL << 13)
345#define SFSR_FT_VA_DMMU_BIT (1ULL << 12)
346#define SFSR_FT_NFO_BIT (1ULL << 11)
347#define SFSR_FT_ILL_BIT (1ULL << 10)
348#define SFSR_FT_ATOMIC_BIT (1ULL << 9)
349#define SFSR_FT_NF_E_BIT (1ULL << 8)
350#define SFSR_FT_PRIV_BIT (1ULL << 7)
351#define SFSR_PR_BIT (1ULL << 3)
352#define SFSR_WRITE_BIT (1ULL << 2)
353#define SFSR_OW_BIT (1ULL << 1)
354#define SFSR_VALID_BIT (1ULL << 0)
355
356#define SFSR_ASI_SHIFT 16
357#define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT)
358#define SFSR_CT_PRIMARY (0ULL << 4)
359#define SFSR_CT_SECONDARY (1ULL << 4)
360#define SFSR_CT_NUCLEUS (2ULL << 4)
361#define SFSR_CT_NOTRANS (3ULL << 4)
362#define SFSR_CT_MASK (3ULL << 4)
363
364
365
366
367
368
369#define CACHE_STATE_MASK 0x3
370#define CACHE_DISABLED 0x0
371#define CACHE_FROZEN 0x1
372#define CACHE_ENABLED 0x3
373
374
375
376#define CACHE_CTRL_IF (1 << 4)
377#define CACHE_CTRL_DF (1 << 5)
378#define CACHE_CTRL_DP (1 << 14)
379#define CACHE_CTRL_IP (1 << 15)
380#define CACHE_CTRL_IB (1 << 16)
381#define CACHE_CTRL_FI (1 << 21)
382#define CACHE_CTRL_FD (1 << 22)
383#define CACHE_CTRL_DS (1 << 23)
384
385#define CONVERT_BIT(X, SRC, DST) \
386 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
387
388typedef struct SparcTLBEntry {
389 uint64_t tag;
390 uint64_t tte;
391} SparcTLBEntry;
392
393struct CPUTimer
394{
395 const char *name;
396 uint32_t frequency;
397 uint32_t disabled;
398 uint64_t disabled_mask;
399 uint32_t npt;
400 uint64_t npt_mask;
401 int64_t clock_offset;
402 QEMUTimer *qtimer;
403};
404
405typedef struct CPUTimer CPUTimer;
406
407typedef struct CPUSPARCState CPUSPARCState;
408#if defined(TARGET_SPARC64)
409typedef union {
410 uint64_t mmuregs[16];
411 struct {
412 uint64_t tsb_tag_target;
413 uint64_t mmu_primary_context;
414 uint64_t mmu_secondary_context;
415 uint64_t sfsr;
416 uint64_t sfar;
417 uint64_t tsb;
418 uint64_t tag_access;
419 uint64_t virtual_watchpoint;
420 uint64_t physical_watchpoint;
421 uint64_t sun4v_ctx_config[2];
422 uint64_t sun4v_tsb_pointers[4];
423 };
424} SparcV9MMU;
425#endif
426struct CPUSPARCState {
427 target_ulong gregs[8];
428 target_ulong *regwptr;
429 target_ulong pc;
430 target_ulong npc;
431 target_ulong y;
432
433
434 target_ulong cc_src, cc_src2;
435 target_ulong cc_dst;
436 uint32_t cc_op;
437
438 target_ulong cond;
439
440
441 uint32_t psr;
442 target_ulong fsr;
443 CPU_DoubleU fpr[TARGET_DPREGS];
444 uint32_t cwp;
445
446#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
447 uint32_t wim;
448#endif
449 target_ulong tbr;
450#if !defined(TARGET_SPARC64)
451 int psrs;
452 int psrps;
453 int psret;
454#endif
455 uint32_t psrpil;
456 uint32_t pil_in;
457#if !defined(TARGET_SPARC64)
458 int psref;
459#endif
460 int interrupt_index;
461
462 target_ulong regbase[MAX_NWINDOWS * 16 + 8];
463
464
465 struct {} end_reset_fields;
466
467 CPU_COMMON
468
469
470 target_ulong version;
471 uint32_t nwindows;
472
473
474#if defined(TARGET_SPARC64)
475 uint64_t lsu;
476#define DMMU_E 0x8
477#define IMMU_E 0x4
478 SparcV9MMU immu;
479 SparcV9MMU dmmu;
480 SparcTLBEntry itlb[64];
481 SparcTLBEntry dtlb[64];
482 uint32_t mmu_version;
483#else
484 uint32_t mmuregs[32];
485 uint64_t mxccdata[4];
486 uint64_t mxccregs[8];
487 uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
488 uint64_t mmubpaction;
489 uint64_t mmubpregs[4];
490 uint64_t prom_addr;
491#endif
492
493 float128 qt0, qt1;
494 float_status fp_status;
495#if defined(TARGET_SPARC64)
496#define MAXTL_MAX 8
497#define MAXTL_MASK (MAXTL_MAX - 1)
498 trap_state ts[MAXTL_MAX];
499 uint32_t xcc;
500 uint32_t asi;
501 uint32_t pstate;
502 uint32_t tl;
503 uint32_t maxtl;
504 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
505 uint64_t agregs[8];
506 uint64_t bgregs[8];
507 uint64_t igregs[8];
508 uint64_t mgregs[8];
509 uint64_t glregs[8 * MAXTL_MAX];
510 uint64_t fprs;
511 uint64_t tick_cmpr, stick_cmpr;
512 CPUTimer *tick, *stick;
513#define TICK_NPT_MASK 0x8000000000000000ULL
514#define TICK_INT_DIS 0x8000000000000000ULL
515 uint64_t gsr;
516 uint32_t gl;
517
518 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
519 uint64_t scratch[8];
520 CPUTimer *hstick;
521
522 uint64_t ivec_status;
523 uint64_t ivec_data[3];
524 uint32_t softint;
525#define SOFTINT_TIMER 1
526#define SOFTINT_STIMER (1 << 16)
527#define SOFTINT_INTRMASK (0xFFFE)
528#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
529#endif
530 sparc_def_t def;
531
532 void *irq_manager;
533 void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
534
535
536 uint32_t cache_control;
537};
538
539
540
541
542
543
544
545struct SPARCCPU {
546
547 CPUState parent_obj;
548
549
550 CPUSPARCState env;
551};
552
553static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env)
554{
555 return container_of(env, SPARCCPU, env);
556}
557
558#define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e))
559
560#define ENV_OFFSET offsetof(SPARCCPU, env)
561
562#ifndef CONFIG_USER_ONLY
563extern const struct VMStateDescription vmstate_sparc_cpu;
564#endif
565
566void sparc_cpu_do_interrupt(CPUState *cpu);
567void sparc_cpu_dump_state(CPUState *cpu, FILE *f,
568 fprintf_function cpu_fprintf, int flags);
569hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
570int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
571int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
572void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
573 MMUAccessType access_type,
574 int mmu_idx,
575 uintptr_t retaddr);
576void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN;
577
578#ifndef NO_CPU_IO_DEFS
579
580void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
581void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
582
583int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
584 int mmu_idx);
585target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
586void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
587
588#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
589int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
590 uint8_t *buf, int len, bool is_write);
591#endif
592
593
594
595void sparc_tcg_init(void);
596
597
598
599
600target_ulong cpu_get_psr(CPUSPARCState *env1);
601void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
602void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
603#ifdef TARGET_SPARC64
604target_ulong cpu_get_ccr(CPUSPARCState *env1);
605void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
606target_ulong cpu_get_cwp64(CPUSPARCState *env1);
607void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
608void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
609void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl);
610#endif
611int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
612int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
613void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
614
615
616void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
617
618
619void cpu_check_irqs(CPUSPARCState *env);
620
621
622void leon3_irq_ack(void *irq_manager, int intno);
623
624#if defined (TARGET_SPARC64)
625
626static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
627{
628 return (x & mask) == (y & mask);
629}
630
631#define MMU_CONTEXT_BITS 13
632#define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
633
634static inline int tlb_compare_context(const SparcTLBEntry *tlb,
635 uint64_t context)
636{
637 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
638}
639
640#endif
641#endif
642
643
644#if !defined(CONFIG_USER_ONLY)
645void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
646 bool is_write, bool is_exec, int is_asi,
647 unsigned size);
648#if defined(TARGET_SPARC64)
649hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
650 int mmu_idx);
651#endif
652#endif
653int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
654
655#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
656#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
657#define CPU_RESOLVING_TYPE TYPE_SPARC_CPU
658
659#define cpu_signal_handler cpu_sparc_signal_handler
660#define cpu_list sparc_cpu_list
661
662
663#if defined (TARGET_SPARC64)
664#define MMU_USER_IDX 0
665#define MMU_USER_SECONDARY_IDX 1
666#define MMU_KERNEL_IDX 2
667#define MMU_KERNEL_SECONDARY_IDX 3
668#define MMU_NUCLEUS_IDX 4
669#define MMU_PHYS_IDX 5
670#else
671#define MMU_USER_IDX 0
672#define MMU_KERNEL_IDX 1
673#define MMU_PHYS_IDX 2
674#endif
675
676#if defined (TARGET_SPARC64)
677static inline int cpu_has_hypervisor(CPUSPARCState *env1)
678{
679 return env1->def.features & CPU_FEATURE_HYPV;
680}
681
682static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
683{
684 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
685}
686
687static inline int cpu_supervisor_mode(CPUSPARCState *env1)
688{
689 return env1->pstate & PS_PRIV;
690}
691#else
692static inline int cpu_supervisor_mode(CPUSPARCState *env1)
693{
694 return env1->psrs;
695}
696#endif
697
698static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
699{
700#if defined(CONFIG_USER_ONLY)
701 return MMU_USER_IDX;
702#elif !defined(TARGET_SPARC64)
703 if ((env->mmuregs[0] & MMU_E) == 0) {
704 return MMU_PHYS_IDX;
705 } else {
706 return env->psrs;
707 }
708#else
709
710 if (ifetch
711 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
712 : (env->lsu & DMMU_E) == 0) {
713 return MMU_PHYS_IDX;
714 } else if (cpu_hypervisor_mode(env)) {
715 return MMU_PHYS_IDX;
716 } else if (env->tl > 0) {
717 return MMU_NUCLEUS_IDX;
718 } else if (cpu_supervisor_mode(env)) {
719 return MMU_KERNEL_IDX;
720 } else {
721 return MMU_USER_IDX;
722 }
723#endif
724}
725
726static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
727{
728#if !defined (TARGET_SPARC64)
729 if (env1->psret != 0)
730 return 1;
731#else
732 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) {
733 return 1;
734 }
735#endif
736
737 return 0;
738}
739
740static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
741{
742#if !defined(TARGET_SPARC64)
743
744 return pil == 15 || pil > env1->psrpil;
745#else
746 return pil > env1->psrpil;
747#endif
748}
749
750#include "exec/cpu-all.h"
751
752#ifdef TARGET_SPARC64
753
754void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
755uint64_t cpu_tick_get_count(CPUTimer *timer);
756void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
757trap_state* cpu_tsptr(CPUSPARCState* env);
758#endif
759
760#define TB_FLAG_MMU_MASK 7
761#define TB_FLAG_FPU_ENABLED (1 << 4)
762#define TB_FLAG_AM_ENABLED (1 << 5)
763#define TB_FLAG_SUPER (1 << 6)
764#define TB_FLAG_HYPER (1 << 7)
765#define TB_FLAG_ASI_SHIFT 24
766
767static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
768 target_ulong *cs_base, uint32_t *pflags)
769{
770 uint32_t flags;
771 *pc = env->pc;
772 *cs_base = env->npc;
773 flags = cpu_mmu_index(env, false);
774#ifndef CONFIG_USER_ONLY
775 if (cpu_supervisor_mode(env)) {
776 flags |= TB_FLAG_SUPER;
777 }
778#endif
779#ifdef TARGET_SPARC64
780#ifndef CONFIG_USER_ONLY
781 if (cpu_hypervisor_mode(env)) {
782 flags |= TB_FLAG_HYPER;
783 }
784#endif
785 if (env->pstate & PS_AM) {
786 flags |= TB_FLAG_AM_ENABLED;
787 }
788 if ((env->def.features & CPU_FEATURE_FLOAT)
789 && (env->pstate & PS_PEF)
790 && (env->fprs & FPRS_FEF)) {
791 flags |= TB_FLAG_FPU_ENABLED;
792 }
793 flags |= env->asi << TB_FLAG_ASI_SHIFT;
794#else
795 if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
796 flags |= TB_FLAG_FPU_ENABLED;
797 }
798#endif
799 *pflags = flags;
800}
801
802static inline bool tb_fpu_enabled(int tb_flags)
803{
804#if defined(CONFIG_USER_ONLY)
805 return true;
806#else
807 return tb_flags & TB_FLAG_FPU_ENABLED;
808#endif
809}
810
811static inline bool tb_am_enabled(int tb_flags)
812{
813#ifndef TARGET_SPARC64
814 return false;
815#else
816 return tb_flags & TB_FLAG_AM_ENABLED;
817#endif
818}
819
820#endif
821