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26
27#ifdef HOST_WORDS_BIGENDIAN
28# define MIPS_BE 1
29#else
30# define MIPS_BE 0
31#endif
32
33#if TCG_TARGET_REG_BITS == 32
34# define LO_OFF (MIPS_BE * 4)
35# define HI_OFF (4 - LO_OFF)
36#else
37
38
39int link_error(void);
40# define LO_OFF link_error()
41# define HI_OFF link_error()
42#endif
43
44#ifdef CONFIG_DEBUG_TCG
45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 "zero",
47 "at",
48 "v0",
49 "v1",
50 "a0",
51 "a1",
52 "a2",
53 "a3",
54 "t0",
55 "t1",
56 "t2",
57 "t3",
58 "t4",
59 "t5",
60 "t6",
61 "t7",
62 "s0",
63 "s1",
64 "s2",
65 "s3",
66 "s4",
67 "s5",
68 "s6",
69 "s7",
70 "t8",
71 "t9",
72 "k0",
73 "k1",
74 "gp",
75 "sp",
76 "s8",
77 "ra",
78};
79#endif
80
81#define TCG_TMP0 TCG_REG_AT
82#define TCG_TMP1 TCG_REG_T9
83#define TCG_TMP2 TCG_REG_T8
84#define TCG_TMP3 TCG_REG_T7
85
86#ifndef CONFIG_SOFTMMU
87#define TCG_GUEST_BASE_REG TCG_REG_S1
88#endif
89
90
91static const int tcg_target_reg_alloc_order[] = {
92
93 TCG_REG_S0,
94 TCG_REG_S1,
95 TCG_REG_S2,
96 TCG_REG_S3,
97 TCG_REG_S4,
98 TCG_REG_S5,
99 TCG_REG_S6,
100 TCG_REG_S7,
101 TCG_REG_S8,
102
103
104 TCG_REG_T4,
105 TCG_REG_T5,
106 TCG_REG_T6,
107 TCG_REG_T7,
108 TCG_REG_T8,
109 TCG_REG_T9,
110 TCG_REG_V1,
111 TCG_REG_V0,
112
113
114 TCG_REG_T3,
115 TCG_REG_T2,
116 TCG_REG_T1,
117 TCG_REG_T0,
118 TCG_REG_A3,
119 TCG_REG_A2,
120 TCG_REG_A1,
121 TCG_REG_A0,
122};
123
124static const TCGReg tcg_target_call_iarg_regs[] = {
125 TCG_REG_A0,
126 TCG_REG_A1,
127 TCG_REG_A2,
128 TCG_REG_A3,
129#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
130 TCG_REG_T0,
131 TCG_REG_T1,
132 TCG_REG_T2,
133 TCG_REG_T3,
134#endif
135};
136
137static const TCGReg tcg_target_call_oarg_regs[2] = {
138 TCG_REG_V0,
139 TCG_REG_V1
140};
141
142static tcg_insn_unit *tb_ret_addr;
143static tcg_insn_unit *bswap32_addr;
144static tcg_insn_unit *bswap32u_addr;
145static tcg_insn_unit *bswap64_addr;
146
147static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target)
148{
149
150 ptrdiff_t disp = target - (pc + 1);
151 tcg_debug_assert(disp == (int16_t)disp);
152 return disp & 0xffff;
153}
154
155static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target)
156{
157 *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target));
158}
159
160static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
161{
162 tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
163 return ((uintptr_t)target >> 2) & 0x3ffffff;
164}
165
166static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target)
167{
168 *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target));
169}
170
171static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
172 intptr_t value, intptr_t addend)
173{
174 tcg_debug_assert(type == R_MIPS_PC16);
175 tcg_debug_assert(addend == 0);
176 reloc_pc16(code_ptr, (tcg_insn_unit *)value);
177 return true;
178}
179
180#define TCG_CT_CONST_ZERO 0x100
181#define TCG_CT_CONST_U16 0x200
182#define TCG_CT_CONST_S16 0x400
183#define TCG_CT_CONST_P2M1 0x800
184#define TCG_CT_CONST_N16 0x1000
185#define TCG_CT_CONST_WSZ 0x2000
186
187static inline bool is_p2m1(tcg_target_long val)
188{
189 return val && ((val + 1) & val) == 0;
190}
191
192
193static const char *target_parse_constraint(TCGArgConstraint *ct,
194 const char *ct_str, TCGType type)
195{
196 switch(*ct_str++) {
197 case 'r':
198 ct->ct |= TCG_CT_REG;
199 ct->u.regs = 0xffffffff;
200 break;
201 case 'L':
202 ct->ct |= TCG_CT_REG;
203 ct->u.regs = 0xffffffff;
204 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
205#if defined(CONFIG_SOFTMMU)
206 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
207 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
208 }
209#endif
210 break;
211 case 'S':
212 ct->ct |= TCG_CT_REG;
213 ct->u.regs = 0xffffffff;
214 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
215#if defined(CONFIG_SOFTMMU)
216 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
217 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
218 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
219 } else {
220 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
221 }
222#endif
223 break;
224 case 'I':
225 ct->ct |= TCG_CT_CONST_U16;
226 break;
227 case 'J':
228 ct->ct |= TCG_CT_CONST_S16;
229 break;
230 case 'K':
231 ct->ct |= TCG_CT_CONST_P2M1;
232 break;
233 case 'N':
234 ct->ct |= TCG_CT_CONST_N16;
235 break;
236 case 'W':
237 ct->ct |= TCG_CT_CONST_WSZ;
238 break;
239 case 'Z':
240
241
242
243 ct->ct |= TCG_CT_CONST_ZERO;
244 break;
245 default:
246 return NULL;
247 }
248 return ct_str;
249}
250
251
252static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
253 const TCGArgConstraint *arg_ct)
254{
255 int ct;
256 ct = arg_ct->ct;
257 if (ct & TCG_CT_CONST) {
258 return 1;
259 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
260 return 1;
261 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
262 return 1;
263 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
264 return 1;
265 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
266 return 1;
267 } else if ((ct & TCG_CT_CONST_P2M1)
268 && use_mips32r2_instructions && is_p2m1(val)) {
269 return 1;
270 } else if ((ct & TCG_CT_CONST_WSZ)
271 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
272 return 1;
273 }
274 return 0;
275}
276
277
278typedef enum {
279 OPC_J = 002 << 26,
280 OPC_JAL = 003 << 26,
281 OPC_BEQ = 004 << 26,
282 OPC_BNE = 005 << 26,
283 OPC_BLEZ = 006 << 26,
284 OPC_BGTZ = 007 << 26,
285 OPC_ADDIU = 011 << 26,
286 OPC_SLTI = 012 << 26,
287 OPC_SLTIU = 013 << 26,
288 OPC_ANDI = 014 << 26,
289 OPC_ORI = 015 << 26,
290 OPC_XORI = 016 << 26,
291 OPC_LUI = 017 << 26,
292 OPC_DADDIU = 031 << 26,
293 OPC_LB = 040 << 26,
294 OPC_LH = 041 << 26,
295 OPC_LW = 043 << 26,
296 OPC_LBU = 044 << 26,
297 OPC_LHU = 045 << 26,
298 OPC_LWU = 047 << 26,
299 OPC_SB = 050 << 26,
300 OPC_SH = 051 << 26,
301 OPC_SW = 053 << 26,
302 OPC_LD = 067 << 26,
303 OPC_SD = 077 << 26,
304
305 OPC_SPECIAL = 000 << 26,
306 OPC_SLL = OPC_SPECIAL | 000,
307 OPC_SRL = OPC_SPECIAL | 002,
308 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
309 OPC_SRA = OPC_SPECIAL | 003,
310 OPC_SLLV = OPC_SPECIAL | 004,
311 OPC_SRLV = OPC_SPECIAL | 006,
312 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
313 OPC_SRAV = OPC_SPECIAL | 007,
314 OPC_JR_R5 = OPC_SPECIAL | 010,
315 OPC_JALR = OPC_SPECIAL | 011,
316 OPC_MOVZ = OPC_SPECIAL | 012,
317 OPC_MOVN = OPC_SPECIAL | 013,
318 OPC_SYNC = OPC_SPECIAL | 017,
319 OPC_MFHI = OPC_SPECIAL | 020,
320 OPC_MFLO = OPC_SPECIAL | 022,
321 OPC_DSLLV = OPC_SPECIAL | 024,
322 OPC_DSRLV = OPC_SPECIAL | 026,
323 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
324 OPC_DSRAV = OPC_SPECIAL | 027,
325 OPC_MULT = OPC_SPECIAL | 030,
326 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
327 OPC_MUH = OPC_SPECIAL | 030 | 0300,
328 OPC_MULTU = OPC_SPECIAL | 031,
329 OPC_MULU = OPC_SPECIAL | 031 | 0200,
330 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
331 OPC_DIV = OPC_SPECIAL | 032,
332 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
333 OPC_MOD = OPC_SPECIAL | 032 | 0300,
334 OPC_DIVU = OPC_SPECIAL | 033,
335 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
336 OPC_MODU = OPC_SPECIAL | 033 | 0300,
337 OPC_DMULT = OPC_SPECIAL | 034,
338 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
339 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
340 OPC_DMULTU = OPC_SPECIAL | 035,
341 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
342 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
343 OPC_DDIV = OPC_SPECIAL | 036,
344 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
345 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
346 OPC_DDIVU = OPC_SPECIAL | 037,
347 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
348 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
349 OPC_ADDU = OPC_SPECIAL | 041,
350 OPC_SUBU = OPC_SPECIAL | 043,
351 OPC_AND = OPC_SPECIAL | 044,
352 OPC_OR = OPC_SPECIAL | 045,
353 OPC_XOR = OPC_SPECIAL | 046,
354 OPC_NOR = OPC_SPECIAL | 047,
355 OPC_SLT = OPC_SPECIAL | 052,
356 OPC_SLTU = OPC_SPECIAL | 053,
357 OPC_DADDU = OPC_SPECIAL | 055,
358 OPC_DSUBU = OPC_SPECIAL | 057,
359 OPC_SELEQZ = OPC_SPECIAL | 065,
360 OPC_SELNEZ = OPC_SPECIAL | 067,
361 OPC_DSLL = OPC_SPECIAL | 070,
362 OPC_DSRL = OPC_SPECIAL | 072,
363 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
364 OPC_DSRA = OPC_SPECIAL | 073,
365 OPC_DSLL32 = OPC_SPECIAL | 074,
366 OPC_DSRL32 = OPC_SPECIAL | 076,
367 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
368 OPC_DSRA32 = OPC_SPECIAL | 077,
369 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
370 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
371
372 OPC_REGIMM = 001 << 26,
373 OPC_BLTZ = OPC_REGIMM | (000 << 16),
374 OPC_BGEZ = OPC_REGIMM | (001 << 16),
375
376 OPC_SPECIAL2 = 034 << 26,
377 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
378 OPC_CLZ = OPC_SPECIAL2 | 040,
379 OPC_DCLZ = OPC_SPECIAL2 | 044,
380
381 OPC_SPECIAL3 = 037 << 26,
382 OPC_EXT = OPC_SPECIAL3 | 000,
383 OPC_DEXTM = OPC_SPECIAL3 | 001,
384 OPC_DEXTU = OPC_SPECIAL3 | 002,
385 OPC_DEXT = OPC_SPECIAL3 | 003,
386 OPC_INS = OPC_SPECIAL3 | 004,
387 OPC_DINSM = OPC_SPECIAL3 | 005,
388 OPC_DINSU = OPC_SPECIAL3 | 006,
389 OPC_DINS = OPC_SPECIAL3 | 007,
390 OPC_WSBH = OPC_SPECIAL3 | 00240,
391 OPC_DSBH = OPC_SPECIAL3 | 00244,
392 OPC_DSHD = OPC_SPECIAL3 | 00544,
393 OPC_SEB = OPC_SPECIAL3 | 02040,
394 OPC_SEH = OPC_SPECIAL3 | 03040,
395
396
397 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
398
399
400
401
402
403 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
404
405
406
407 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 5,
408 OPC_SYNC_MB = OPC_SYNC | 0x10 << 5,
409 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 5,
410 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 5,
411 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 5,
412
413
414 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
415 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
416 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
417 ? OPC_SRL : OPC_DSRL,
418} MIPSInsn;
419
420
421
422
423static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
424 TCGReg rd, TCGReg rs, TCGReg rt)
425{
426 int32_t inst;
427
428 inst = opc;
429 inst |= (rs & 0x1F) << 21;
430 inst |= (rt & 0x1F) << 16;
431 inst |= (rd & 0x1F) << 11;
432 tcg_out32(s, inst);
433}
434
435
436
437
438static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
439 TCGReg rt, TCGReg rs, TCGArg imm)
440{
441 int32_t inst;
442
443 inst = opc;
444 inst |= (rs & 0x1F) << 21;
445 inst |= (rt & 0x1F) << 16;
446 inst |= (imm & 0xffff);
447 tcg_out32(s, inst);
448}
449
450
451
452
453static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
454 TCGReg rs, int msb, int lsb)
455{
456 int32_t inst;
457
458 inst = opc;
459 inst |= (rs & 0x1F) << 21;
460 inst |= (rt & 0x1F) << 16;
461 inst |= (msb & 0x1F) << 11;
462 inst |= (lsb & 0x1F) << 6;
463 tcg_out32(s, inst);
464}
465
466static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
467 MIPSInsn oph, TCGReg rt, TCGReg rs,
468 int msb, int lsb)
469{
470 if (lsb >= 32) {
471 opc = oph;
472 msb -= 32;
473 lsb -= 32;
474 } else if (msb >= 32) {
475 opc = opm;
476 msb -= 32;
477 }
478 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
479}
480
481
482
483
484static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
485 TCGReg rt, TCGReg rs)
486{
487 tcg_out_opc_imm(s, opc, rt, rs, 0);
488}
489
490
491
492
493static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
494 TCGReg rd, TCGReg rt, TCGArg sa)
495{
496 int32_t inst;
497
498 inst = opc;
499 inst |= (rt & 0x1F) << 16;
500 inst |= (rd & 0x1F) << 11;
501 inst |= (sa & 0x1F) << 6;
502 tcg_out32(s, inst);
503
504}
505
506static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
507 TCGReg rd, TCGReg rt, TCGArg sa)
508{
509 int32_t inst;
510
511 inst = (sa & 32 ? opc2 : opc1);
512 inst |= (rt & 0x1F) << 16;
513 inst |= (rd & 0x1F) << 11;
514 inst |= (sa & 0x1F) << 6;
515 tcg_out32(s, inst);
516}
517
518
519
520
521
522static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target)
523{
524 uintptr_t dest = (uintptr_t)target;
525 uintptr_t from = (uintptr_t)s->code_ptr + 4;
526 int32_t inst;
527
528
529
530 if ((from ^ dest) & -(1 << 28)) {
531 return false;
532 }
533 tcg_debug_assert((dest & 3) == 0);
534
535 inst = opc;
536 inst |= (dest >> 2) & 0x3ffffff;
537 tcg_out32(s, inst);
538 return true;
539}
540
541static inline void tcg_out_nop(TCGContext *s)
542{
543 tcg_out32(s, 0);
544}
545
546static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
547{
548 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
549}
550
551static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
552{
553 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
554}
555
556static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
557{
558 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
559}
560
561static inline void tcg_out_mov(TCGContext *s, TCGType type,
562 TCGReg ret, TCGReg arg)
563{
564
565 if (ret != arg) {
566 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
567 }
568}
569
570static void tcg_out_movi(TCGContext *s, TCGType type,
571 TCGReg ret, tcg_target_long arg)
572{
573 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
574 arg = (int32_t)arg;
575 }
576 if (arg == (int16_t)arg) {
577 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
578 return;
579 }
580 if (arg == (uint16_t)arg) {
581 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
582 return;
583 }
584 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
585 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
586 } else {
587 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
588 if (arg & 0xffff0000ull) {
589 tcg_out_dsll(s, ret, ret, 16);
590 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
591 tcg_out_dsll(s, ret, ret, 16);
592 } else {
593 tcg_out_dsll(s, ret, ret, 32);
594 }
595 }
596 if (arg & 0xffff) {
597 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
598 }
599}
600
601static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
602{
603 if (use_mips32r2_instructions) {
604 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
605 } else {
606
607 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
608 tcg_abort();
609 }
610
611 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
612 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
613 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
614 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
615 }
616}
617
618static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
619{
620 if (use_mips32r2_instructions) {
621 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
622 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
623 } else {
624
625 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
626 tcg_abort();
627 }
628
629 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
630 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
631 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
632 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
633 }
634}
635
636static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub)
637{
638 bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub);
639 tcg_debug_assert(ok);
640}
641
642static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
643{
644 if (use_mips32r2_instructions) {
645 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
646 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
647 } else {
648 tcg_out_bswap_subr(s, bswap32_addr);
649
650 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
651 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
652 }
653}
654
655static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
656{
657 if (use_mips32r2_instructions) {
658 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
659 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
660 tcg_out_dsrl(s, ret, ret, 32);
661 } else {
662 tcg_out_bswap_subr(s, bswap32u_addr);
663
664 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
665 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
666 }
667}
668
669static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
670{
671 if (use_mips32r2_instructions) {
672 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
673 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
674 } else {
675 tcg_out_bswap_subr(s, bswap64_addr);
676
677 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
678 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
679 }
680}
681
682static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
683{
684 if (use_mips32r2_instructions) {
685 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg);
686 } else {
687 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
688 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24);
689 }
690}
691
692static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
693{
694 if (use_mips32r2_instructions) {
695 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg);
696 } else {
697 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16);
698 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
699 }
700}
701
702static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
703{
704 if (use_mips32r2_instructions) {
705 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
706 } else {
707 tcg_out_dsll(s, ret, arg, 32);
708 tcg_out_dsrl(s, ret, ret, 32);
709 }
710}
711
712static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
713 TCGReg addr, intptr_t ofs)
714{
715 int16_t lo = ofs;
716 if (ofs != lo) {
717 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
718 if (addr != TCG_REG_ZERO) {
719 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
720 }
721 addr = TCG_TMP0;
722 }
723 tcg_out_opc_imm(s, opc, data, addr, lo);
724}
725
726static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
727 TCGReg arg1, intptr_t arg2)
728{
729 MIPSInsn opc = OPC_LD;
730 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
731 opc = OPC_LW;
732 }
733 tcg_out_ldst(s, opc, arg, arg1, arg2);
734}
735
736static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
737 TCGReg arg1, intptr_t arg2)
738{
739 MIPSInsn opc = OPC_SD;
740 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
741 opc = OPC_SW;
742 }
743 tcg_out_ldst(s, opc, arg, arg1, arg2);
744}
745
746static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
747 TCGReg base, intptr_t ofs)
748{
749 if (val == 0) {
750 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
751 return true;
752 }
753 return false;
754}
755
756static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
757 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
758 bool cbh, bool is_sub)
759{
760 TCGReg th = TCG_TMP1;
761
762
763
764 if (cbl && cbh && bh == -1 && bl != 0) {
765 bl = -bl;
766 bh = 0;
767 is_sub = !is_sub;
768 }
769
770
771
772 if (!cbh) {
773 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
774 } else if (bh != 0 || ah == rl) {
775 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
776 } else {
777 th = ah;
778 }
779
780
781 if (is_sub) {
782 if (cbl) {
783 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
784 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
785 } else {
786 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
787 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
788 }
789 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
790 } else {
791 if (cbl) {
792 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
793 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
794 } else if (rl == al && rl == bl) {
795 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
796 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
797 } else {
798 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
799 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
800 }
801 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
802 }
803}
804
805
806#define MIPS_CMP_INV 1
807#define MIPS_CMP_SWAP 2
808
809static const uint8_t mips_cmp_map[16] = {
810 [TCG_COND_LT] = 0,
811 [TCG_COND_LTU] = 0,
812 [TCG_COND_GE] = MIPS_CMP_INV,
813 [TCG_COND_GEU] = MIPS_CMP_INV,
814 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
815 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
816 [TCG_COND_GT] = MIPS_CMP_SWAP,
817 [TCG_COND_GTU] = MIPS_CMP_SWAP,
818};
819
820static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
821 TCGReg arg1, TCGReg arg2)
822{
823 MIPSInsn s_opc = OPC_SLTU;
824 int cmp_map;
825
826 switch (cond) {
827 case TCG_COND_EQ:
828 if (arg2 != 0) {
829 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
830 arg1 = ret;
831 }
832 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
833 break;
834
835 case TCG_COND_NE:
836 if (arg2 != 0) {
837 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
838 arg1 = ret;
839 }
840 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
841 break;
842
843 case TCG_COND_LT:
844 case TCG_COND_GE:
845 case TCG_COND_LE:
846 case TCG_COND_GT:
847 s_opc = OPC_SLT;
848
849
850 case TCG_COND_LTU:
851 case TCG_COND_GEU:
852 case TCG_COND_LEU:
853 case TCG_COND_GTU:
854 cmp_map = mips_cmp_map[cond];
855 if (cmp_map & MIPS_CMP_SWAP) {
856 TCGReg t = arg1;
857 arg1 = arg2;
858 arg2 = t;
859 }
860 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
861 if (cmp_map & MIPS_CMP_INV) {
862 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
863 }
864 break;
865
866 default:
867 tcg_abort();
868 break;
869 }
870}
871
872static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
873 TCGReg arg2, TCGLabel *l)
874{
875 static const MIPSInsn b_zero[16] = {
876 [TCG_COND_LT] = OPC_BLTZ,
877 [TCG_COND_GT] = OPC_BGTZ,
878 [TCG_COND_LE] = OPC_BLEZ,
879 [TCG_COND_GE] = OPC_BGEZ,
880 };
881
882 MIPSInsn s_opc = OPC_SLTU;
883 MIPSInsn b_opc;
884 int cmp_map;
885
886 switch (cond) {
887 case TCG_COND_EQ:
888 b_opc = OPC_BEQ;
889 break;
890 case TCG_COND_NE:
891 b_opc = OPC_BNE;
892 break;
893
894 case TCG_COND_LT:
895 case TCG_COND_GT:
896 case TCG_COND_LE:
897 case TCG_COND_GE:
898 if (arg2 == 0) {
899 b_opc = b_zero[cond];
900 arg2 = arg1;
901 arg1 = 0;
902 break;
903 }
904 s_opc = OPC_SLT;
905
906
907 case TCG_COND_LTU:
908 case TCG_COND_GTU:
909 case TCG_COND_LEU:
910 case TCG_COND_GEU:
911 cmp_map = mips_cmp_map[cond];
912 if (cmp_map & MIPS_CMP_SWAP) {
913 TCGReg t = arg1;
914 arg1 = arg2;
915 arg2 = t;
916 }
917 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
918 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
919 arg1 = TCG_TMP0;
920 arg2 = TCG_REG_ZERO;
921 break;
922
923 default:
924 tcg_abort();
925 break;
926 }
927
928 tcg_out_opc_br(s, b_opc, arg1, arg2);
929 if (l->has_value) {
930 reloc_pc16(s->code_ptr - 1, l->u.value_ptr);
931 } else {
932 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
933 }
934 tcg_out_nop(s);
935}
936
937static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
938 TCGReg al, TCGReg ah,
939 TCGReg bl, TCGReg bh)
940{
941
942 if (bh != 0) {
943 if (ah != 0) {
944 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
945 ah = tmp0;
946 } else {
947 ah = bh;
948 }
949 }
950
951 if (bl != 0) {
952 if (al != 0) {
953 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
954 al = tmp1;
955 } else {
956 al = bl;
957 }
958 }
959
960 if (ah != 0) {
961 if (al != 0) {
962 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
963 al = tmp0;
964 } else {
965 al = ah;
966 }
967 }
968 return al;
969}
970
971static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
972 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
973{
974 TCGReg tmp0 = TCG_TMP0;
975 TCGReg tmp1 = ret;
976
977 tcg_debug_assert(ret != TCG_TMP0);
978 if (ret == ah || ret == bh) {
979 tcg_debug_assert(ret != TCG_TMP1);
980 tmp1 = TCG_TMP1;
981 }
982
983 switch (cond) {
984 case TCG_COND_EQ:
985 case TCG_COND_NE:
986 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
987 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
988 break;
989
990 default:
991 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
992 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
993 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
994 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
995 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
996 break;
997 }
998}
999
1000static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
1001 TCGReg bl, TCGReg bh, TCGLabel *l)
1002{
1003 TCGCond b_cond = TCG_COND_NE;
1004 TCGReg tmp = TCG_TMP1;
1005
1006
1007
1008
1009 switch (cond) {
1010 case TCG_COND_EQ:
1011 case TCG_COND_NE:
1012 b_cond = cond;
1013 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
1014 break;
1015
1016 default:
1017
1018 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1019 cond = tcg_invert_cond(cond);
1020 b_cond = TCG_COND_EQ;
1021 }
1022 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
1023 break;
1024 }
1025
1026 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
1027}
1028
1029static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
1030 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
1031{
1032 bool eqz = false;
1033
1034
1035 if (use_mips32r6_instructions && v1 == 0) {
1036 v1 = v2;
1037 v2 = 0;
1038 cond = tcg_invert_cond(cond);
1039 }
1040
1041 switch (cond) {
1042 case TCG_COND_EQ:
1043 eqz = true;
1044
1045 case TCG_COND_NE:
1046 if (c2 != 0) {
1047 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
1048 c1 = TCG_TMP0;
1049 }
1050 break;
1051
1052 default:
1053
1054 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1055 cond = tcg_invert_cond(cond);
1056 eqz = true;
1057 }
1058 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
1059 c1 = TCG_TMP0;
1060 break;
1061 }
1062
1063 if (use_mips32r6_instructions) {
1064 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1065 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1066
1067 if (v2 != 0) {
1068 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1069 }
1070 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1071 if (v2 != 0) {
1072 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1073 }
1074 } else {
1075 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1076
1077 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1078
1079
1080 tcg_debug_assert(v2 == ret);
1081 }
1082}
1083
1084static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
1085{
1086
1087
1088 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1089
1090
1091 if (tail) {
1092 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1093 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1094 }
1095 } else {
1096 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1097 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1098 }
1099 }
1100}
1101
1102static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
1103{
1104 tcg_out_call_int(s, arg, false);
1105 tcg_out_nop(s);
1106}
1107
1108#if defined(CONFIG_SOFTMMU)
1109#include "tcg-ldst.inc.c"
1110
1111static void * const qemu_ld_helpers[16] = {
1112 [MO_UB] = helper_ret_ldub_mmu,
1113 [MO_SB] = helper_ret_ldsb_mmu,
1114 [MO_LEUW] = helper_le_lduw_mmu,
1115 [MO_LESW] = helper_le_ldsw_mmu,
1116 [MO_LEUL] = helper_le_ldul_mmu,
1117 [MO_LEQ] = helper_le_ldq_mmu,
1118 [MO_BEUW] = helper_be_lduw_mmu,
1119 [MO_BESW] = helper_be_ldsw_mmu,
1120 [MO_BEUL] = helper_be_ldul_mmu,
1121 [MO_BEQ] = helper_be_ldq_mmu,
1122#if TCG_TARGET_REG_BITS == 64
1123 [MO_LESL] = helper_le_ldsl_mmu,
1124 [MO_BESL] = helper_be_ldsl_mmu,
1125#endif
1126};
1127
1128static void * const qemu_st_helpers[16] = {
1129 [MO_UB] = helper_ret_stb_mmu,
1130 [MO_LEUW] = helper_le_stw_mmu,
1131 [MO_LEUL] = helper_le_stl_mmu,
1132 [MO_LEQ] = helper_le_stq_mmu,
1133 [MO_BEUW] = helper_be_stw_mmu,
1134 [MO_BEUL] = helper_be_stl_mmu,
1135 [MO_BEQ] = helper_be_stq_mmu,
1136};
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
1149{
1150 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1151 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
1152 } else {
1153
1154
1155 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1156 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
1157 }
1158 return i + 1;
1159}
1160
1161static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
1162{
1163 TCGReg tmp = TCG_TMP0;
1164 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1165 tmp = tcg_target_call_iarg_regs[i];
1166 }
1167 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff);
1168 return tcg_out_call_iarg_reg(s, i, tmp);
1169}
1170
1171static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
1172{
1173 TCGReg tmp = TCG_TMP0;
1174 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1175 tmp = tcg_target_call_iarg_regs[i];
1176 }
1177 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
1178 return tcg_out_call_iarg_reg(s, i, tmp);
1179}
1180
1181static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
1182{
1183 TCGReg tmp = TCG_TMP0;
1184 if (arg == 0) {
1185 tmp = TCG_REG_ZERO;
1186 } else {
1187 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1188 tmp = tcg_target_call_iarg_regs[i];
1189 }
1190 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
1191 }
1192 return tcg_out_call_iarg_reg(s, i, tmp);
1193}
1194
1195static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
1196{
1197 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1198 i = (i + 1) & ~1;
1199 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
1200 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
1201 return i;
1202}
1203
1204
1205QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) <
1206 offsetof(CPUArchState, tlb_mask));
1207
1208
1209QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) -
1210 offsetof(CPUArchState, tlb_mask) >= 0x8000);
1211
1212
1213
1214
1215
1216
1217static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
1218 TCGReg addrh, TCGMemOpIdx oi,
1219 tcg_insn_unit *label_ptr[2], bool is_load)
1220{
1221 TCGMemOp opc = get_memop(oi);
1222 unsigned s_bits = opc & MO_SIZE;
1223 unsigned a_bits = get_alignment_bits(opc);
1224 int mem_index = get_mmuidx(oi);
1225 int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]);
1226 int table_off = offsetof(CPUArchState, tlb_table[mem_index]);
1227 int add_off = offsetof(CPUTLBEntry, addend);
1228 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
1229 : offsetof(CPUTLBEntry, addr_write));
1230 TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
1231 target_ulong mask;
1232
1233 if (table_off > 0x7fff) {
1234 int mask_hi = mask_off - (int16_t)mask_off;
1235 int table_hi = table_off - (int16_t)table_off;
1236
1237 table_base = TCG_TMP1;
1238 if (likely(mask_hi == table_hi)) {
1239 mask_base = table_base;
1240 tcg_out_opc_imm(s, OPC_LUI, mask_base, TCG_REG_ZERO, mask_hi >> 16);
1241 tcg_out_opc_reg(s, ALIAS_PADD, mask_base, mask_base, TCG_AREG0);
1242 mask_off -= mask_hi;
1243 table_off -= mask_hi;
1244 } else {
1245 if (mask_hi != 0) {
1246 mask_base = TCG_TMP0;
1247 tcg_out_opc_imm(s, OPC_LUI,
1248 mask_base, TCG_REG_ZERO, mask_hi >> 16);
1249 tcg_out_opc_reg(s, ALIAS_PADD,
1250 mask_base, mask_base, TCG_AREG0);
1251 }
1252 table_off -= mask_off;
1253 mask_off -= mask_hi;
1254 tcg_out_opc_imm(s, ALIAS_PADDI, table_base, mask_base, mask_off);
1255 }
1256 }
1257
1258
1259 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, mask_base, mask_off);
1260 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, table_base, table_off);
1261
1262
1263 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
1264 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1265 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1266
1267
1268 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1269
1270
1271
1272 if (a_bits < s_bits) {
1273 a_bits = s_bits;
1274 }
1275
1276
1277 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
1278
1279
1280 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1281 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
1282 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask);
1283 } else {
1284 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
1285 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
1286 TCG_TMP0, TCG_TMP3, cmp_off);
1287 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask);
1288
1289
1290 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1291 }
1292 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
1293
1294
1295 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1296 tcg_out_ext32u(s, base, addrl);
1297 addrl = base;
1298 }
1299
1300 label_ptr[0] = s->code_ptr;
1301 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1302
1303
1304 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1305
1306 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
1307
1308
1309 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1310
1311 label_ptr[1] = s->code_ptr;
1312 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
1313 }
1314
1315
1316 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
1317}
1318
1319static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
1320 TCGType ext,
1321 TCGReg datalo, TCGReg datahi,
1322 TCGReg addrlo, TCGReg addrhi,
1323 void *raddr, tcg_insn_unit *label_ptr[2])
1324{
1325 TCGLabelQemuLdst *label = new_ldst_label(s);
1326
1327 label->is_ld = is_ld;
1328 label->oi = oi;
1329 label->type = ext;
1330 label->datalo_reg = datalo;
1331 label->datahi_reg = datahi;
1332 label->addrlo_reg = addrlo;
1333 label->addrhi_reg = addrhi;
1334 label->raddr = raddr;
1335 label->label_ptr[0] = label_ptr[0];
1336 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1337 label->label_ptr[1] = label_ptr[1];
1338 }
1339}
1340
1341static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1342{
1343 TCGMemOpIdx oi = l->oi;
1344 TCGMemOp opc = get_memop(oi);
1345 TCGReg v0;
1346 int i;
1347
1348
1349 reloc_pc16(l->label_ptr[0], s->code_ptr);
1350 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1351 reloc_pc16(l->label_ptr[1], s->code_ptr);
1352 }
1353
1354 i = 1;
1355 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1356 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1357 } else {
1358 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1359 }
1360 i = tcg_out_call_iarg_imm(s, i, oi);
1361 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
1362 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
1363
1364 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1365
1366 v0 = l->datalo_reg;
1367 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1368
1369
1370 if (MIPS_BE) {
1371 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
1372 v0 = l->datahi_reg;
1373 } else {
1374 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
1375 }
1376 }
1377
1378 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1379 reloc_pc16(s->code_ptr - 1, l->raddr);
1380
1381
1382 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
1383
1384 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
1385 } else {
1386 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
1387 }
1388}
1389
1390static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1391{
1392 TCGMemOpIdx oi = l->oi;
1393 TCGMemOp opc = get_memop(oi);
1394 TCGMemOp s_bits = opc & MO_SIZE;
1395 int i;
1396
1397
1398 reloc_pc16(l->label_ptr[0], s->code_ptr);
1399 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1400 reloc_pc16(l->label_ptr[1], s->code_ptr);
1401 }
1402
1403 i = 1;
1404 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1405 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1406 } else {
1407 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1408 }
1409 switch (s_bits) {
1410 case MO_8:
1411 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
1412 break;
1413 case MO_16:
1414 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
1415 break;
1416 case MO_32:
1417 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1418 break;
1419 case MO_64:
1420 if (TCG_TARGET_REG_BITS == 32) {
1421 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
1422 } else {
1423 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1424 }
1425 break;
1426 default:
1427 tcg_abort();
1428 }
1429 i = tcg_out_call_iarg_imm(s, i, oi);
1430
1431
1432
1433 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
1434 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
1435 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
1436
1437 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1438}
1439#endif
1440
1441static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1442 TCGReg base, TCGMemOp opc, bool is_64)
1443{
1444 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1445 case MO_UB:
1446 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1447 break;
1448 case MO_SB:
1449 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1450 break;
1451 case MO_UW | MO_BSWAP:
1452 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1453 tcg_out_bswap16(s, lo, TCG_TMP1);
1454 break;
1455 case MO_UW:
1456 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1457 break;
1458 case MO_SW | MO_BSWAP:
1459 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1460 tcg_out_bswap16s(s, lo, TCG_TMP1);
1461 break;
1462 case MO_SW:
1463 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1464 break;
1465 case MO_UL | MO_BSWAP:
1466 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1467 if (use_mips32r2_instructions) {
1468 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1469 tcg_out_bswap32u(s, lo, lo);
1470 } else {
1471 tcg_out_bswap_subr(s, bswap32u_addr);
1472
1473 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
1474 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1475 }
1476 break;
1477 }
1478
1479 case MO_SL | MO_BSWAP:
1480 if (use_mips32r2_instructions) {
1481 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1482 tcg_out_bswap32(s, lo, lo);
1483 } else {
1484 tcg_out_bswap_subr(s, bswap32_addr);
1485
1486 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1487 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
1488 }
1489 break;
1490 case MO_UL:
1491 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1492 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1493 break;
1494 }
1495
1496 case MO_SL:
1497 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1498 break;
1499 case MO_Q | MO_BSWAP:
1500 if (TCG_TARGET_REG_BITS == 64) {
1501 if (use_mips32r2_instructions) {
1502 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1503 tcg_out_bswap64(s, lo, lo);
1504 } else {
1505 tcg_out_bswap_subr(s, bswap64_addr);
1506
1507 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
1508 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1509 }
1510 } else if (use_mips32r2_instructions) {
1511 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1512 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
1513 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1514 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1515 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1516 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1517 } else {
1518 tcg_out_bswap_subr(s, bswap32_addr);
1519
1520 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1521 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
1522 tcg_out_bswap_subr(s, bswap32_addr);
1523
1524 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1525 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1526 }
1527 break;
1528 case MO_Q:
1529
1530 if (TCG_TARGET_REG_BITS == 64) {
1531 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1532 } else if (MIPS_BE ? hi != base : lo == base) {
1533 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1534 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1535 } else {
1536 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1537 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1538 }
1539 break;
1540 default:
1541 tcg_abort();
1542 }
1543}
1544
1545static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1546{
1547 TCGReg addr_regl, addr_regh __attribute__((unused));
1548 TCGReg data_regl, data_regh;
1549 TCGMemOpIdx oi;
1550 TCGMemOp opc;
1551#if defined(CONFIG_SOFTMMU)
1552 tcg_insn_unit *label_ptr[2];
1553#endif
1554 TCGReg base = TCG_REG_A0;
1555
1556 data_regl = *args++;
1557 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1558 addr_regl = *args++;
1559 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1560 oi = *args++;
1561 opc = get_memop(oi);
1562
1563#if defined(CONFIG_SOFTMMU)
1564 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
1565 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1566 add_qemu_ldst_label(s, 1, oi,
1567 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1568 data_regl, data_regh, addr_regl, addr_regh,
1569 s->code_ptr, label_ptr);
1570#else
1571 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1572 tcg_out_ext32u(s, base, addr_regl);
1573 addr_regl = base;
1574 }
1575 if (guest_base == 0 && data_regl != addr_regl) {
1576 base = addr_regl;
1577 } else if (guest_base == (int16_t)guest_base) {
1578 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1579 } else {
1580 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1581 }
1582 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1583#endif
1584}
1585
1586static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1587 TCGReg base, TCGMemOp opc)
1588{
1589
1590 if ((lo | hi) == 0) {
1591 opc &= ~MO_BSWAP;
1592 }
1593
1594 switch (opc & (MO_SIZE | MO_BSWAP)) {
1595 case MO_8:
1596 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1597 break;
1598
1599 case MO_16 | MO_BSWAP:
1600 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);
1601 tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);
1602 lo = TCG_TMP1;
1603
1604 case MO_16:
1605 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
1606 break;
1607
1608 case MO_32 | MO_BSWAP:
1609 tcg_out_bswap32(s, TCG_TMP3, lo);
1610 lo = TCG_TMP3;
1611
1612 case MO_32:
1613 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
1614 break;
1615
1616 case MO_64 | MO_BSWAP:
1617 if (TCG_TARGET_REG_BITS == 64) {
1618 tcg_out_bswap64(s, TCG_TMP3, lo);
1619 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
1620 } else if (use_mips32r2_instructions) {
1621 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
1622 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
1623 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1624 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1625 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
1626 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
1627 } else {
1628 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
1629 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
1630 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
1631 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
1632 }
1633 break;
1634 case MO_64:
1635 if (TCG_TARGET_REG_BITS == 64) {
1636 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1637 } else {
1638 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
1639 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
1640 }
1641 break;
1642
1643 default:
1644 tcg_abort();
1645 }
1646}
1647
1648static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1649{
1650 TCGReg addr_regl, addr_regh __attribute__((unused));
1651 TCGReg data_regl, data_regh;
1652 TCGMemOpIdx oi;
1653 TCGMemOp opc;
1654#if defined(CONFIG_SOFTMMU)
1655 tcg_insn_unit *label_ptr[2];
1656#endif
1657 TCGReg base = TCG_REG_A0;
1658
1659 data_regl = *args++;
1660 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1661 addr_regl = *args++;
1662 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1663 oi = *args++;
1664 opc = get_memop(oi);
1665
1666#if defined(CONFIG_SOFTMMU)
1667 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
1668 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1669 add_qemu_ldst_label(s, 0, oi,
1670 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1671 data_regl, data_regh, addr_regl, addr_regh,
1672 s->code_ptr, label_ptr);
1673#else
1674 base = TCG_REG_A0;
1675 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1676 tcg_out_ext32u(s, base, addr_regl);
1677 addr_regl = base;
1678 }
1679 if (guest_base == 0) {
1680 base = addr_regl;
1681 } else if (guest_base == (int16_t)guest_base) {
1682 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1683 } else {
1684 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1685 }
1686 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1687#endif
1688}
1689
1690static void tcg_out_mb(TCGContext *s, TCGArg a0)
1691{
1692 static const MIPSInsn sync[] = {
1693
1694
1695
1696 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1697 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1698 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1699 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1700 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1701 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1702 };
1703 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1704}
1705
1706static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1707 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1708{
1709 if (use_mips32r6_instructions) {
1710 if (a2 == width) {
1711 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1712 } else {
1713 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1714 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1715 }
1716 } else {
1717 if (a2 == width) {
1718 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1719 } else if (a0 == a2) {
1720 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1721 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1722 } else if (a0 != a1) {
1723 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1724 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1725 } else {
1726 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1727 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1728 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1729 }
1730 }
1731}
1732
1733static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1734 const TCGArg *args, const int *const_args)
1735{
1736 MIPSInsn i1, i2;
1737 TCGArg a0, a1, a2;
1738 int c2;
1739
1740 a0 = args[0];
1741 a1 = args[1];
1742 a2 = args[2];
1743 c2 = const_args[2];
1744
1745 switch (opc) {
1746 case INDEX_op_exit_tb:
1747 {
1748 TCGReg b0 = TCG_REG_ZERO;
1749
1750 a0 = (intptr_t)a0;
1751 if (a0 & ~0xffff) {
1752 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
1753 b0 = TCG_REG_V0;
1754 }
1755 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
1756 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0,
1757 (uintptr_t)tb_ret_addr);
1758 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1759 }
1760 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
1761 }
1762 break;
1763 case INDEX_op_goto_tb:
1764 if (s->tb_jmp_insn_offset) {
1765
1766 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
1767
1768 tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff));
1769 } else {
1770
1771 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
1772 (uintptr_t)(s->tb_jmp_target_addr + a0));
1773 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1774 }
1775 tcg_out_nop(s);
1776 set_jmp_reset_offset(s, a0);
1777 break;
1778 case INDEX_op_goto_ptr:
1779
1780 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
1781 tcg_out_nop(s);
1782 break;
1783 case INDEX_op_br:
1784 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
1785 arg_label(a0));
1786 break;
1787
1788 case INDEX_op_ld8u_i32:
1789 case INDEX_op_ld8u_i64:
1790 i1 = OPC_LBU;
1791 goto do_ldst;
1792 case INDEX_op_ld8s_i32:
1793 case INDEX_op_ld8s_i64:
1794 i1 = OPC_LB;
1795 goto do_ldst;
1796 case INDEX_op_ld16u_i32:
1797 case INDEX_op_ld16u_i64:
1798 i1 = OPC_LHU;
1799 goto do_ldst;
1800 case INDEX_op_ld16s_i32:
1801 case INDEX_op_ld16s_i64:
1802 i1 = OPC_LH;
1803 goto do_ldst;
1804 case INDEX_op_ld_i32:
1805 case INDEX_op_ld32s_i64:
1806 i1 = OPC_LW;
1807 goto do_ldst;
1808 case INDEX_op_ld32u_i64:
1809 i1 = OPC_LWU;
1810 goto do_ldst;
1811 case INDEX_op_ld_i64:
1812 i1 = OPC_LD;
1813 goto do_ldst;
1814 case INDEX_op_st8_i32:
1815 case INDEX_op_st8_i64:
1816 i1 = OPC_SB;
1817 goto do_ldst;
1818 case INDEX_op_st16_i32:
1819 case INDEX_op_st16_i64:
1820 i1 = OPC_SH;
1821 goto do_ldst;
1822 case INDEX_op_st_i32:
1823 case INDEX_op_st32_i64:
1824 i1 = OPC_SW;
1825 goto do_ldst;
1826 case INDEX_op_st_i64:
1827 i1 = OPC_SD;
1828 do_ldst:
1829 tcg_out_ldst(s, i1, a0, a1, a2);
1830 break;
1831
1832 case INDEX_op_add_i32:
1833 i1 = OPC_ADDU, i2 = OPC_ADDIU;
1834 goto do_binary;
1835 case INDEX_op_add_i64:
1836 i1 = OPC_DADDU, i2 = OPC_DADDIU;
1837 goto do_binary;
1838 case INDEX_op_or_i32:
1839 case INDEX_op_or_i64:
1840 i1 = OPC_OR, i2 = OPC_ORI;
1841 goto do_binary;
1842 case INDEX_op_xor_i32:
1843 case INDEX_op_xor_i64:
1844 i1 = OPC_XOR, i2 = OPC_XORI;
1845 do_binary:
1846 if (c2) {
1847 tcg_out_opc_imm(s, i2, a0, a1, a2);
1848 break;
1849 }
1850 do_binaryv:
1851 tcg_out_opc_reg(s, i1, a0, a1, a2);
1852 break;
1853
1854 case INDEX_op_sub_i32:
1855 i1 = OPC_SUBU, i2 = OPC_ADDIU;
1856 goto do_subtract;
1857 case INDEX_op_sub_i64:
1858 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
1859 do_subtract:
1860 if (c2) {
1861 tcg_out_opc_imm(s, i2, a0, a1, -a2);
1862 break;
1863 }
1864 goto do_binaryv;
1865 case INDEX_op_and_i32:
1866 if (c2 && a2 != (uint16_t)a2) {
1867 int msb = ctz32(~a2) - 1;
1868 tcg_debug_assert(use_mips32r2_instructions);
1869 tcg_debug_assert(is_p2m1(a2));
1870 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
1871 break;
1872 }
1873 i1 = OPC_AND, i2 = OPC_ANDI;
1874 goto do_binary;
1875 case INDEX_op_and_i64:
1876 if (c2 && a2 != (uint16_t)a2) {
1877 int msb = ctz64(~a2) - 1;
1878 tcg_debug_assert(use_mips32r2_instructions);
1879 tcg_debug_assert(is_p2m1(a2));
1880 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
1881 break;
1882 }
1883 i1 = OPC_AND, i2 = OPC_ANDI;
1884 goto do_binary;
1885 case INDEX_op_nor_i32:
1886 case INDEX_op_nor_i64:
1887 i1 = OPC_NOR;
1888 goto do_binaryv;
1889
1890 case INDEX_op_mul_i32:
1891 if (use_mips32_instructions) {
1892 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1893 break;
1894 }
1895 i1 = OPC_MULT, i2 = OPC_MFLO;
1896 goto do_hilo1;
1897 case INDEX_op_mulsh_i32:
1898 if (use_mips32r6_instructions) {
1899 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
1900 break;
1901 }
1902 i1 = OPC_MULT, i2 = OPC_MFHI;
1903 goto do_hilo1;
1904 case INDEX_op_muluh_i32:
1905 if (use_mips32r6_instructions) {
1906 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
1907 break;
1908 }
1909 i1 = OPC_MULTU, i2 = OPC_MFHI;
1910 goto do_hilo1;
1911 case INDEX_op_div_i32:
1912 if (use_mips32r6_instructions) {
1913 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
1914 break;
1915 }
1916 i1 = OPC_DIV, i2 = OPC_MFLO;
1917 goto do_hilo1;
1918 case INDEX_op_divu_i32:
1919 if (use_mips32r6_instructions) {
1920 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
1921 break;
1922 }
1923 i1 = OPC_DIVU, i2 = OPC_MFLO;
1924 goto do_hilo1;
1925 case INDEX_op_rem_i32:
1926 if (use_mips32r6_instructions) {
1927 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
1928 break;
1929 }
1930 i1 = OPC_DIV, i2 = OPC_MFHI;
1931 goto do_hilo1;
1932 case INDEX_op_remu_i32:
1933 if (use_mips32r6_instructions) {
1934 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
1935 break;
1936 }
1937 i1 = OPC_DIVU, i2 = OPC_MFHI;
1938 goto do_hilo1;
1939 case INDEX_op_mul_i64:
1940 if (use_mips32r6_instructions) {
1941 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
1942 break;
1943 }
1944 i1 = OPC_DMULT, i2 = OPC_MFLO;
1945 goto do_hilo1;
1946 case INDEX_op_mulsh_i64:
1947 if (use_mips32r6_instructions) {
1948 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
1949 break;
1950 }
1951 i1 = OPC_DMULT, i2 = OPC_MFHI;
1952 goto do_hilo1;
1953 case INDEX_op_muluh_i64:
1954 if (use_mips32r6_instructions) {
1955 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
1956 break;
1957 }
1958 i1 = OPC_DMULTU, i2 = OPC_MFHI;
1959 goto do_hilo1;
1960 case INDEX_op_div_i64:
1961 if (use_mips32r6_instructions) {
1962 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
1963 break;
1964 }
1965 i1 = OPC_DDIV, i2 = OPC_MFLO;
1966 goto do_hilo1;
1967 case INDEX_op_divu_i64:
1968 if (use_mips32r6_instructions) {
1969 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
1970 break;
1971 }
1972 i1 = OPC_DDIVU, i2 = OPC_MFLO;
1973 goto do_hilo1;
1974 case INDEX_op_rem_i64:
1975 if (use_mips32r6_instructions) {
1976 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
1977 break;
1978 }
1979 i1 = OPC_DDIV, i2 = OPC_MFHI;
1980 goto do_hilo1;
1981 case INDEX_op_remu_i64:
1982 if (use_mips32r6_instructions) {
1983 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
1984 break;
1985 }
1986 i1 = OPC_DDIVU, i2 = OPC_MFHI;
1987 do_hilo1:
1988 tcg_out_opc_reg(s, i1, 0, a1, a2);
1989 tcg_out_opc_reg(s, i2, a0, 0, 0);
1990 break;
1991
1992 case INDEX_op_muls2_i32:
1993 i1 = OPC_MULT;
1994 goto do_hilo2;
1995 case INDEX_op_mulu2_i32:
1996 i1 = OPC_MULTU;
1997 goto do_hilo2;
1998 case INDEX_op_muls2_i64:
1999 i1 = OPC_DMULT;
2000 goto do_hilo2;
2001 case INDEX_op_mulu2_i64:
2002 i1 = OPC_DMULTU;
2003 do_hilo2:
2004 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
2005 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
2006 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
2007 break;
2008
2009 case INDEX_op_not_i32:
2010 case INDEX_op_not_i64:
2011 i1 = OPC_NOR;
2012 goto do_unary;
2013 case INDEX_op_bswap16_i32:
2014 case INDEX_op_bswap16_i64:
2015 i1 = OPC_WSBH;
2016 goto do_unary;
2017 case INDEX_op_ext8s_i32:
2018 case INDEX_op_ext8s_i64:
2019 i1 = OPC_SEB;
2020 goto do_unary;
2021 case INDEX_op_ext16s_i32:
2022 case INDEX_op_ext16s_i64:
2023 i1 = OPC_SEH;
2024 do_unary:
2025 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
2026 break;
2027
2028 case INDEX_op_bswap32_i32:
2029 tcg_out_bswap32(s, a0, a1);
2030 break;
2031 case INDEX_op_bswap32_i64:
2032 tcg_out_bswap32u(s, a0, a1);
2033 break;
2034 case INDEX_op_bswap64_i64:
2035 tcg_out_bswap64(s, a0, a1);
2036 break;
2037 case INDEX_op_extrh_i64_i32:
2038 tcg_out_dsra(s, a0, a1, 32);
2039 break;
2040 case INDEX_op_ext32s_i64:
2041 case INDEX_op_ext_i32_i64:
2042 case INDEX_op_extrl_i64_i32:
2043 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
2044 break;
2045 case INDEX_op_ext32u_i64:
2046 case INDEX_op_extu_i32_i64:
2047 tcg_out_ext32u(s, a0, a1);
2048 break;
2049
2050 case INDEX_op_sar_i32:
2051 i1 = OPC_SRAV, i2 = OPC_SRA;
2052 goto do_shift;
2053 case INDEX_op_shl_i32:
2054 i1 = OPC_SLLV, i2 = OPC_SLL;
2055 goto do_shift;
2056 case INDEX_op_shr_i32:
2057 i1 = OPC_SRLV, i2 = OPC_SRL;
2058 goto do_shift;
2059 case INDEX_op_rotr_i32:
2060 i1 = OPC_ROTRV, i2 = OPC_ROTR;
2061 do_shift:
2062 if (c2) {
2063 tcg_out_opc_sa(s, i2, a0, a1, a2);
2064 break;
2065 }
2066 do_shiftv:
2067 tcg_out_opc_reg(s, i1, a0, a2, a1);
2068 break;
2069 case INDEX_op_rotl_i32:
2070 if (c2) {
2071 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
2072 } else {
2073 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2074 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
2075 }
2076 break;
2077 case INDEX_op_sar_i64:
2078 if (c2) {
2079 tcg_out_dsra(s, a0, a1, a2);
2080 break;
2081 }
2082 i1 = OPC_DSRAV;
2083 goto do_shiftv;
2084 case INDEX_op_shl_i64:
2085 if (c2) {
2086 tcg_out_dsll(s, a0, a1, a2);
2087 break;
2088 }
2089 i1 = OPC_DSLLV;
2090 goto do_shiftv;
2091 case INDEX_op_shr_i64:
2092 if (c2) {
2093 tcg_out_dsrl(s, a0, a1, a2);
2094 break;
2095 }
2096 i1 = OPC_DSRLV;
2097 goto do_shiftv;
2098 case INDEX_op_rotr_i64:
2099 if (c2) {
2100 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2101 break;
2102 }
2103 i1 = OPC_DROTRV;
2104 goto do_shiftv;
2105 case INDEX_op_rotl_i64:
2106 if (c2) {
2107 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2108 } else {
2109 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2110 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2111 }
2112 break;
2113
2114 case INDEX_op_clz_i32:
2115 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2116 break;
2117 case INDEX_op_clz_i64:
2118 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2119 break;
2120
2121 case INDEX_op_deposit_i32:
2122 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
2123 break;
2124 case INDEX_op_deposit_i64:
2125 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2126 args[3] + args[4] - 1, args[3]);
2127 break;
2128 case INDEX_op_extract_i32:
2129 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
2130 break;
2131 case INDEX_op_extract_i64:
2132 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2133 args[3] - 1, a2);
2134 break;
2135
2136 case INDEX_op_brcond_i32:
2137 case INDEX_op_brcond_i64:
2138 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
2139 break;
2140 case INDEX_op_brcond2_i32:
2141 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
2142 break;
2143
2144 case INDEX_op_movcond_i32:
2145 case INDEX_op_movcond_i64:
2146 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
2147 break;
2148
2149 case INDEX_op_setcond_i32:
2150 case INDEX_op_setcond_i64:
2151 tcg_out_setcond(s, args[3], a0, a1, a2);
2152 break;
2153 case INDEX_op_setcond2_i32:
2154 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
2155 break;
2156
2157 case INDEX_op_qemu_ld_i32:
2158 tcg_out_qemu_ld(s, args, false);
2159 break;
2160 case INDEX_op_qemu_ld_i64:
2161 tcg_out_qemu_ld(s, args, true);
2162 break;
2163 case INDEX_op_qemu_st_i32:
2164 tcg_out_qemu_st(s, args, false);
2165 break;
2166 case INDEX_op_qemu_st_i64:
2167 tcg_out_qemu_st(s, args, true);
2168 break;
2169
2170 case INDEX_op_add2_i32:
2171 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2172 const_args[4], const_args[5], false);
2173 break;
2174 case INDEX_op_sub2_i32:
2175 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2176 const_args[4], const_args[5], true);
2177 break;
2178
2179 case INDEX_op_mb:
2180 tcg_out_mb(s, a0);
2181 break;
2182 case INDEX_op_mov_i32:
2183 case INDEX_op_mov_i64:
2184 case INDEX_op_movi_i32:
2185 case INDEX_op_movi_i64:
2186 case INDEX_op_call:
2187 default:
2188 tcg_abort();
2189 }
2190}
2191
2192static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2193{
2194 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2195 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2196 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
2197 static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
2198 static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
2199 static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
2200 static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
2201 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
2202 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2203 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
2204 static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
2205 static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
2206 static const TCGTargetOpDef SZ_SZ_S
2207 = { .args_ct_str = { "SZ", "SZ", "S" } };
2208 static const TCGTargetOpDef SZ_SZ_S_S
2209 = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
2210 static const TCGTargetOpDef r_rZ_rN
2211 = { .args_ct_str = { "r", "rZ", "rN" } };
2212 static const TCGTargetOpDef r_rZ_rZ
2213 = { .args_ct_str = { "r", "rZ", "rZ" } };
2214 static const TCGTargetOpDef r_r_rIK
2215 = { .args_ct_str = { "r", "r", "rIK" } };
2216 static const TCGTargetOpDef r_r_rWZ
2217 = { .args_ct_str = { "r", "r", "rWZ" } };
2218 static const TCGTargetOpDef r_r_r_r
2219 = { .args_ct_str = { "r", "r", "r", "r" } };
2220 static const TCGTargetOpDef r_r_L_L
2221 = { .args_ct_str = { "r", "r", "L", "L" } };
2222 static const TCGTargetOpDef dep
2223 = { .args_ct_str = { "r", "0", "rZ" } };
2224 static const TCGTargetOpDef movc
2225 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
2226 static const TCGTargetOpDef movc_r6
2227 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2228 static const TCGTargetOpDef add2
2229 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
2230 static const TCGTargetOpDef br2
2231 = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
2232 static const TCGTargetOpDef setc2
2233 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2234
2235 switch (op) {
2236 case INDEX_op_goto_ptr:
2237 return &r;
2238
2239 case INDEX_op_ld8u_i32:
2240 case INDEX_op_ld8s_i32:
2241 case INDEX_op_ld16u_i32:
2242 case INDEX_op_ld16s_i32:
2243 case INDEX_op_ld_i32:
2244 case INDEX_op_not_i32:
2245 case INDEX_op_bswap16_i32:
2246 case INDEX_op_bswap32_i32:
2247 case INDEX_op_ext8s_i32:
2248 case INDEX_op_ext16s_i32:
2249 case INDEX_op_extract_i32:
2250 case INDEX_op_ld8u_i64:
2251 case INDEX_op_ld8s_i64:
2252 case INDEX_op_ld16u_i64:
2253 case INDEX_op_ld16s_i64:
2254 case INDEX_op_ld32s_i64:
2255 case INDEX_op_ld32u_i64:
2256 case INDEX_op_ld_i64:
2257 case INDEX_op_not_i64:
2258 case INDEX_op_bswap16_i64:
2259 case INDEX_op_bswap32_i64:
2260 case INDEX_op_bswap64_i64:
2261 case INDEX_op_ext8s_i64:
2262 case INDEX_op_ext16s_i64:
2263 case INDEX_op_ext32s_i64:
2264 case INDEX_op_ext32u_i64:
2265 case INDEX_op_ext_i32_i64:
2266 case INDEX_op_extu_i32_i64:
2267 case INDEX_op_extrl_i64_i32:
2268 case INDEX_op_extrh_i64_i32:
2269 case INDEX_op_extract_i64:
2270 return &r_r;
2271
2272 case INDEX_op_st8_i32:
2273 case INDEX_op_st16_i32:
2274 case INDEX_op_st_i32:
2275 case INDEX_op_st8_i64:
2276 case INDEX_op_st16_i64:
2277 case INDEX_op_st32_i64:
2278 case INDEX_op_st_i64:
2279 return &rZ_r;
2280
2281 case INDEX_op_add_i32:
2282 case INDEX_op_add_i64:
2283 return &r_r_rJ;
2284 case INDEX_op_sub_i32:
2285 case INDEX_op_sub_i64:
2286 return &r_rZ_rN;
2287 case INDEX_op_mul_i32:
2288 case INDEX_op_mulsh_i32:
2289 case INDEX_op_muluh_i32:
2290 case INDEX_op_div_i32:
2291 case INDEX_op_divu_i32:
2292 case INDEX_op_rem_i32:
2293 case INDEX_op_remu_i32:
2294 case INDEX_op_nor_i32:
2295 case INDEX_op_setcond_i32:
2296 case INDEX_op_mul_i64:
2297 case INDEX_op_mulsh_i64:
2298 case INDEX_op_muluh_i64:
2299 case INDEX_op_div_i64:
2300 case INDEX_op_divu_i64:
2301 case INDEX_op_rem_i64:
2302 case INDEX_op_remu_i64:
2303 case INDEX_op_nor_i64:
2304 case INDEX_op_setcond_i64:
2305 return &r_rZ_rZ;
2306 case INDEX_op_muls2_i32:
2307 case INDEX_op_mulu2_i32:
2308 case INDEX_op_muls2_i64:
2309 case INDEX_op_mulu2_i64:
2310 return &r_r_r_r;
2311 case INDEX_op_and_i32:
2312 case INDEX_op_and_i64:
2313 return &r_r_rIK;
2314 case INDEX_op_or_i32:
2315 case INDEX_op_xor_i32:
2316 case INDEX_op_or_i64:
2317 case INDEX_op_xor_i64:
2318 return &r_r_rI;
2319 case INDEX_op_shl_i32:
2320 case INDEX_op_shr_i32:
2321 case INDEX_op_sar_i32:
2322 case INDEX_op_rotr_i32:
2323 case INDEX_op_rotl_i32:
2324 case INDEX_op_shl_i64:
2325 case INDEX_op_shr_i64:
2326 case INDEX_op_sar_i64:
2327 case INDEX_op_rotr_i64:
2328 case INDEX_op_rotl_i64:
2329 return &r_r_ri;
2330 case INDEX_op_clz_i32:
2331 case INDEX_op_clz_i64:
2332 return &r_r_rWZ;
2333
2334 case INDEX_op_deposit_i32:
2335 case INDEX_op_deposit_i64:
2336 return &dep;
2337 case INDEX_op_brcond_i32:
2338 case INDEX_op_brcond_i64:
2339 return &rZ_rZ;
2340 case INDEX_op_movcond_i32:
2341 case INDEX_op_movcond_i64:
2342 return use_mips32r6_instructions ? &movc_r6 : &movc;
2343
2344 case INDEX_op_add2_i32:
2345 case INDEX_op_sub2_i32:
2346 return &add2;
2347 case INDEX_op_setcond2_i32:
2348 return &setc2;
2349 case INDEX_op_brcond2_i32:
2350 return &br2;
2351
2352 case INDEX_op_qemu_ld_i32:
2353 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2354 ? &r_L : &r_L_L);
2355 case INDEX_op_qemu_st_i32:
2356 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2357 ? &SZ_S : &SZ_S_S);
2358 case INDEX_op_qemu_ld_i64:
2359 return (TCG_TARGET_REG_BITS == 64 ? &r_L
2360 : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
2361 case INDEX_op_qemu_st_i64:
2362 return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
2363 : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
2364
2365 default:
2366 return NULL;
2367 }
2368}
2369
2370static const int tcg_target_callee_save_regs[] = {
2371 TCG_REG_S0,
2372 TCG_REG_S1,
2373 TCG_REG_S2,
2374 TCG_REG_S3,
2375 TCG_REG_S4,
2376 TCG_REG_S5,
2377 TCG_REG_S6,
2378 TCG_REG_S7,
2379 TCG_REG_S8,
2380 TCG_REG_RA,
2381};
2382
2383
2384
2385
2386
2387#ifndef use_movnz_instructions
2388bool use_movnz_instructions = false;
2389#endif
2390
2391#ifndef use_mips32_instructions
2392bool use_mips32_instructions = false;
2393#endif
2394
2395#ifndef use_mips32r2_instructions
2396bool use_mips32r2_instructions = false;
2397#endif
2398
2399static volatile sig_atomic_t got_sigill;
2400
2401static void sigill_handler(int signo, siginfo_t *si, void *data)
2402{
2403
2404 ucontext_t *uc = (ucontext_t *)data;
2405 uc->uc_mcontext.pc += 4;
2406
2407 got_sigill = 1;
2408}
2409
2410static void tcg_target_detect_isa(void)
2411{
2412 struct sigaction sa_old, sa_new;
2413
2414 memset(&sa_new, 0, sizeof(sa_new));
2415 sa_new.sa_flags = SA_SIGINFO;
2416 sa_new.sa_sigaction = sigill_handler;
2417 sigaction(SIGILL, &sa_new, &sa_old);
2418
2419
2420#ifndef use_movnz_instructions
2421 got_sigill = 0;
2422 asm volatile(".set push\n"
2423 ".set mips32\n"
2424 "movn $zero, $zero, $zero\n"
2425 "movz $zero, $zero, $zero\n"
2426 ".set pop\n"
2427 : : : );
2428 use_movnz_instructions = !got_sigill;
2429#endif
2430
2431
2432
2433
2434#ifndef use_mips32_instructions
2435 got_sigill = 0;
2436 asm volatile(".set push\n"
2437 ".set mips32\n"
2438 "mul $zero, $zero\n"
2439 ".set pop\n"
2440 : : : );
2441 use_mips32_instructions = !got_sigill;
2442#endif
2443
2444
2445
2446
2447#ifndef use_mips32r2_instructions
2448 if (use_mips32_instructions) {
2449 got_sigill = 0;
2450 asm volatile(".set push\n"
2451 ".set mips32r2\n"
2452 "seb $zero, $zero\n"
2453 ".set pop\n"
2454 : : : );
2455 use_mips32r2_instructions = !got_sigill;
2456 }
2457#endif
2458
2459 sigaction(SIGILL, &sa_old, NULL);
2460}
2461
2462static tcg_insn_unit *align_code_ptr(TCGContext *s)
2463{
2464 uintptr_t p = (uintptr_t)s->code_ptr;
2465 if (p & 15) {
2466 p = (p + 15) & -16;
2467 s->code_ptr = (void *)p;
2468 }
2469 return s->code_ptr;
2470}
2471
2472
2473#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2474#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2475#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2476
2477#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2478 + TCG_TARGET_STACK_ALIGN - 1) \
2479 & -TCG_TARGET_STACK_ALIGN)
2480#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2481
2482
2483QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2484
2485
2486static void tcg_target_qemu_prologue(TCGContext *s)
2487{
2488 int i;
2489
2490 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2491
2492
2493 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2494 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2495 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2496 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2497 }
2498
2499#ifndef CONFIG_SOFTMMU
2500 if (guest_base) {
2501 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2502 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2503 }
2504#endif
2505
2506
2507 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
2508
2509 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2510
2511
2512
2513
2514
2515 s->code_gen_epilogue = s->code_ptr;
2516 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2517
2518
2519 tb_ret_addr = s->code_ptr;
2520 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2521 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2522 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2523 }
2524
2525 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2526
2527 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2528
2529 if (use_mips32r2_instructions) {
2530 return;
2531 }
2532
2533
2534
2535
2536
2537
2538
2539 bswap32_addr = align_code_ptr(s);
2540
2541 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2542
2543 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2544
2545 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2546
2547 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2548
2549 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2550
2551 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2552
2553 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2554
2555 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2556 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2557
2558 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2559
2560 if (TCG_TARGET_REG_BITS == 32) {
2561 return;
2562 }
2563
2564
2565
2566
2567 bswap32u_addr = align_code_ptr(s);
2568
2569 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2570
2571 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2572
2573 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2574
2575 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2576
2577 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2578
2579 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2580
2581 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2582
2583 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2584
2585 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2586 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2587
2588 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2589
2590
2591
2592
2593 bswap64_addr = align_code_ptr(s);
2594
2595 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2596
2597 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2598
2599
2600 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2601
2602 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2603
2604 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2605
2606 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2607
2608 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2609
2610
2611 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2612
2613 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2614
2615 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2616
2617
2618 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2619
2620 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2621
2622 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2623
2624 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2625
2626
2627 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2628
2629 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2630
2631 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2632
2633
2634 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2635
2636 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2637
2638 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2639
2640 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2641
2642
2643 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2644 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2645
2646 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2647}
2648
2649static void tcg_target_init(TCGContext *s)
2650{
2651 tcg_target_detect_isa();
2652 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2653 if (TCG_TARGET_REG_BITS == 64) {
2654 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2655 }
2656
2657 tcg_target_call_clobber_regs = 0;
2658 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2659 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2660 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2661 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2662 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2663 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2664 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2665 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2666 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2667 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2668 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2669 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2670 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2671 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2672 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2673 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
2674
2675 s->reserved_regs = 0;
2676 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
2677 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0);
2678 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1);
2679 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
2680 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1);
2681 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2);
2682 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3);
2683 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA);
2684 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
2685 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP);
2686}
2687
2688void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
2689 uintptr_t addr)
2690{
2691 atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2));
2692 flush_icache_range(jmp_addr, jmp_addr + 4);
2693}
2694
2695typedef struct {
2696 DebugFrameHeader h;
2697 uint8_t fde_def_cfa[4];
2698 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2699} DebugFrame;
2700
2701#define ELF_HOST_MACHINE EM_MIPS
2702
2703
2704
2705static const DebugFrame debug_frame = {
2706 .h.cie.len = sizeof(DebugFrameCIE) - 4,
2707 .h.cie.id = -1,
2708 .h.cie.version = 1,
2709 .h.cie.code_align = 1,
2710 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f,
2711 .h.cie.return_column = TCG_REG_RA,
2712
2713
2714 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2715
2716 .fde_def_cfa = {
2717 12, TCG_REG_SP,
2718 (FRAME_SIZE & 0x7f) | 0x80,
2719 (FRAME_SIZE >> 7)
2720 },
2721 .fde_reg_ofs = {
2722 0x80 + 16, 9,
2723 0x80 + 17, 8,
2724 0x80 + 18, 7,
2725 0x80 + 19, 6,
2726 0x80 + 20, 5,
2727 0x80 + 21, 4,
2728 0x80 + 22, 3,
2729 0x80 + 30, 2,
2730 0x80 + 31, 1,
2731 }
2732};
2733
2734void tcg_register_jit(void *buf, size_t buf_size)
2735{
2736 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2737}
2738