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22#include "qemu/osdep.h"
23#include "sysemu/sysemu.h"
24#include "hw/hw.h"
25#include "hw/acpi/acpi.h"
26#include "hw/nvram/fw_cfg.h"
27#include "qemu/config-file.h"
28#include "qapi/error.h"
29#include "qapi/opts-visitor.h"
30#include "qapi/qapi-events-run-state.h"
31#include "qapi/qapi-visit-misc.h"
32#include "qemu/error-report.h"
33#include "qemu/option.h"
34
35struct acpi_table_header {
36 uint16_t _length;
37
38 char sig[4]
39 QEMU_NONSTRING;
40 uint32_t length;
41 uint8_t revision;
42 uint8_t checksum;
43 char oem_id[6]
44 QEMU_NONSTRING;
45 char oem_table_id[8]
46 QEMU_NONSTRING;
47 uint32_t oem_revision;
48 char asl_compiler_id[4]
49 QEMU_NONSTRING;
50 uint32_t asl_compiler_revision;
51} QEMU_PACKED;
52
53#define ACPI_TABLE_HDR_SIZE sizeof(struct acpi_table_header)
54#define ACPI_TABLE_PFX_SIZE sizeof(uint16_t)
55
56static const char unsigned dfl_hdr[ACPI_TABLE_HDR_SIZE - ACPI_TABLE_PFX_SIZE] =
57 "QEMU\0\0\0\0\1\0"
58 "QEMUQEQEMUQEMU\1\0\0\0"
59 "QEMU\1\0\0\0"
60 ;
61
62char unsigned *acpi_tables;
63size_t acpi_tables_len;
64
65static QemuOptsList qemu_acpi_opts = {
66 .name = "acpi",
67 .implied_opt_name = "data",
68 .head = QTAILQ_HEAD_INITIALIZER(qemu_acpi_opts.head),
69 .desc = { { 0 } }
70};
71
72static void acpi_register_config(void)
73{
74 qemu_add_opts(&qemu_acpi_opts);
75}
76
77opts_init(acpi_register_config);
78
79static int acpi_checksum(const uint8_t *data, int len)
80{
81 int sum, i;
82 sum = 0;
83 for (i = 0; i < len; i++) {
84 sum += data[i];
85 }
86 return (-sum) & 0xff;
87}
88
89
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92
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95
96
97
98
99
100
101
102
103
104
105
106static void acpi_table_install(const char unsigned *blob, size_t bloblen,
107 bool has_header,
108 const struct AcpiTableOptions *hdrs,
109 Error **errp)
110{
111 size_t body_start;
112 const char unsigned *hdr_src;
113 size_t body_size, acpi_payload_size;
114 struct acpi_table_header *ext_hdr;
115 unsigned changed_fields;
116
117
118
119
120 if (has_header) {
121
122
123
124
125
126
127
128
129 body_start = sizeof dfl_hdr;
130
131 if (bloblen < body_start) {
132 error_setg(errp, "ACPI table claiming to have header is too "
133 "short, available: %zu, expected: %zu", bloblen,
134 body_start);
135 return;
136 }
137 hdr_src = blob;
138 } else {
139
140
141
142
143
144
145
146
147 body_start = 0;
148 hdr_src = dfl_hdr;
149 }
150 body_size = bloblen - body_start;
151 acpi_payload_size = sizeof dfl_hdr + body_size;
152
153 if (acpi_payload_size > UINT16_MAX) {
154 error_setg(errp, "ACPI table too big, requested: %zu, max: %u",
155 acpi_payload_size, (unsigned)UINT16_MAX);
156 return;
157 }
158
159
160 if (acpi_tables == NULL) {
161 acpi_tables_len = sizeof(uint16_t);
162 acpi_tables = g_malloc0(acpi_tables_len);
163 }
164
165 acpi_tables = g_realloc(acpi_tables, acpi_tables_len +
166 ACPI_TABLE_PFX_SIZE +
167 sizeof dfl_hdr + body_size);
168
169 ext_hdr = (struct acpi_table_header *)(acpi_tables + acpi_tables_len);
170 acpi_tables_len += ACPI_TABLE_PFX_SIZE;
171
172 memcpy(acpi_tables + acpi_tables_len, hdr_src, sizeof dfl_hdr);
173 acpi_tables_len += sizeof dfl_hdr;
174
175 if (blob != NULL) {
176 memcpy(acpi_tables + acpi_tables_len, blob + body_start, body_size);
177 acpi_tables_len += body_size;
178 }
179
180
181 stw_le_p(acpi_tables, lduw_le_p(acpi_tables) + 1u);
182
183
184 changed_fields = 0;
185 ext_hdr->_length = cpu_to_le16(acpi_payload_size);
186
187 if (hdrs->has_sig) {
188 strncpy(ext_hdr->sig, hdrs->sig, sizeof ext_hdr->sig);
189 ++changed_fields;
190 }
191
192 if (has_header && le32_to_cpu(ext_hdr->length) != acpi_payload_size) {
193 warn_report("ACPI table has wrong length, header says "
194 "%" PRIu32 ", actual size %zu bytes",
195 le32_to_cpu(ext_hdr->length), acpi_payload_size);
196 }
197 ext_hdr->length = cpu_to_le32(acpi_payload_size);
198
199 if (hdrs->has_rev) {
200 ext_hdr->revision = hdrs->rev;
201 ++changed_fields;
202 }
203
204 ext_hdr->checksum = 0;
205
206 if (hdrs->has_oem_id) {
207 strncpy(ext_hdr->oem_id, hdrs->oem_id, sizeof ext_hdr->oem_id);
208 ++changed_fields;
209 }
210 if (hdrs->has_oem_table_id) {
211 strncpy(ext_hdr->oem_table_id, hdrs->oem_table_id,
212 sizeof ext_hdr->oem_table_id);
213 ++changed_fields;
214 }
215 if (hdrs->has_oem_rev) {
216 ext_hdr->oem_revision = cpu_to_le32(hdrs->oem_rev);
217 ++changed_fields;
218 }
219 if (hdrs->has_asl_compiler_id) {
220 strncpy(ext_hdr->asl_compiler_id, hdrs->asl_compiler_id,
221 sizeof ext_hdr->asl_compiler_id);
222 ++changed_fields;
223 }
224 if (hdrs->has_asl_compiler_rev) {
225 ext_hdr->asl_compiler_revision = cpu_to_le32(hdrs->asl_compiler_rev);
226 ++changed_fields;
227 }
228
229 if (!has_header && changed_fields == 0) {
230 warn_report("ACPI table: no headers are specified");
231 }
232
233
234 ext_hdr->checksum = acpi_checksum((const char unsigned *)ext_hdr +
235 ACPI_TABLE_PFX_SIZE, acpi_payload_size);
236}
237
238void acpi_table_add(const QemuOpts *opts, Error **errp)
239{
240 AcpiTableOptions *hdrs = NULL;
241 Error *err = NULL;
242 char **pathnames = NULL;
243 char **cur;
244 size_t bloblen = 0;
245 char unsigned *blob = NULL;
246
247 {
248 Visitor *v;
249
250 v = opts_visitor_new(opts);
251 visit_type_AcpiTableOptions(v, NULL, &hdrs, &err);
252 visit_free(v);
253 }
254
255 if (err) {
256 goto out;
257 }
258 if (hdrs->has_file == hdrs->has_data) {
259 error_setg(&err, "'-acpitable' requires one of 'data' or 'file'");
260 goto out;
261 }
262
263 pathnames = g_strsplit(hdrs->has_file ? hdrs->file : hdrs->data, ":", 0);
264 if (pathnames == NULL || pathnames[0] == NULL) {
265 error_setg(&err, "'-acpitable' requires at least one pathname");
266 goto out;
267 }
268
269
270 for (cur = pathnames; *cur; ++cur) {
271 int fd = open(*cur, O_RDONLY | O_BINARY);
272
273 if (fd < 0) {
274 error_setg(&err, "can't open file %s: %s", *cur, strerror(errno));
275 goto out;
276 }
277
278 for (;;) {
279 char unsigned data[8192];
280 ssize_t r;
281
282 r = read(fd, data, sizeof data);
283 if (r == 0) {
284 break;
285 } else if (r > 0) {
286 blob = g_realloc(blob, bloblen + r);
287 memcpy(blob + bloblen, data, r);
288 bloblen += r;
289 } else if (errno != EINTR) {
290 error_setg(&err, "can't read file %s: %s",
291 *cur, strerror(errno));
292 close(fd);
293 goto out;
294 }
295 }
296
297 close(fd);
298 }
299
300 acpi_table_install(blob, bloblen, hdrs->has_file, hdrs, &err);
301
302out:
303 g_free(blob);
304 g_strfreev(pathnames);
305 qapi_free_AcpiTableOptions(hdrs);
306
307 error_propagate(errp, err);
308}
309
310unsigned acpi_table_len(void *current)
311{
312 struct acpi_table_header *hdr = current - sizeof(hdr->_length);
313 return hdr->_length;
314}
315
316static
317void *acpi_table_hdr(void *h)
318{
319 struct acpi_table_header *hdr = h;
320 return &hdr->sig;
321}
322
323uint8_t *acpi_table_first(void)
324{
325 if (!acpi_tables) {
326 return NULL;
327 }
328 return acpi_table_hdr(acpi_tables + ACPI_TABLE_PFX_SIZE);
329}
330
331uint8_t *acpi_table_next(uint8_t *current)
332{
333 uint8_t *next = current + acpi_table_len(current);
334
335 if (next - acpi_tables >= acpi_tables_len) {
336 return NULL;
337 } else {
338 return acpi_table_hdr(next);
339 }
340}
341
342int acpi_get_slic_oem(AcpiSlicOem *oem)
343{
344 uint8_t *u;
345
346 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
347 struct acpi_table_header *hdr = (void *)(u - sizeof(hdr->_length));
348
349 if (memcmp(hdr->sig, "SLIC", 4) == 0) {
350 oem->id = hdr->oem_id;
351 oem->table_id = hdr->oem_table_id;
352 return 0;
353 }
354 }
355 return -1;
356}
357
358static void acpi_notify_wakeup(Notifier *notifier, void *data)
359{
360 ACPIREGS *ar = container_of(notifier, ACPIREGS, wakeup);
361 WakeupReason *reason = data;
362
363 switch (*reason) {
364 case QEMU_WAKEUP_REASON_RTC:
365 ar->pm1.evt.sts |=
366 (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_RT_CLOCK_STATUS);
367 break;
368 case QEMU_WAKEUP_REASON_PMTIMER:
369 ar->pm1.evt.sts |=
370 (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_TIMER_STATUS);
371 break;
372 case QEMU_WAKEUP_REASON_OTHER:
373
374
375 ar->pm1.evt.sts |=
376 (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_POWER_BUTTON_STATUS);
377 break;
378 default:
379 break;
380 }
381}
382
383
384uint16_t acpi_pm1_evt_get_sts(ACPIREGS *ar)
385{
386
387
388 int64_t d = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
389 if (d >= muldiv64(ar->tmr.overflow_time,
390 NANOSECONDS_PER_SECOND, PM_TIMER_FREQUENCY)) {
391 ar->pm1.evt.sts |= ACPI_BITMASK_TIMER_STATUS;
392 }
393 return ar->pm1.evt.sts;
394}
395
396static void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val)
397{
398 uint16_t pm1_sts = acpi_pm1_evt_get_sts(ar);
399 if (pm1_sts & val & ACPI_BITMASK_TIMER_STATUS) {
400
401 acpi_pm_tmr_calc_overflow_time(ar);
402 }
403 ar->pm1.evt.sts &= ~val;
404}
405
406static void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val)
407{
408 ar->pm1.evt.en = val;
409 qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC,
410 val & ACPI_BITMASK_RT_CLOCK_ENABLE);
411 qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_PMTIMER,
412 val & ACPI_BITMASK_TIMER_ENABLE);
413}
414
415void acpi_pm1_evt_power_down(ACPIREGS *ar)
416{
417 if (ar->pm1.evt.en & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
418 ar->pm1.evt.sts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
419 ar->tmr.update_sci(ar);
420 }
421}
422
423void acpi_pm1_evt_reset(ACPIREGS *ar)
424{
425 ar->pm1.evt.sts = 0;
426 ar->pm1.evt.en = 0;
427 qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC, 0);
428 qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_PMTIMER, 0);
429}
430
431static uint64_t acpi_pm_evt_read(void *opaque, hwaddr addr, unsigned width)
432{
433 ACPIREGS *ar = opaque;
434 switch (addr) {
435 case 0:
436 return acpi_pm1_evt_get_sts(ar);
437 case 2:
438 return ar->pm1.evt.en;
439 default:
440 return 0;
441 }
442}
443
444static void acpi_pm_evt_write(void *opaque, hwaddr addr, uint64_t val,
445 unsigned width)
446{
447 ACPIREGS *ar = opaque;
448 switch (addr) {
449 case 0:
450 acpi_pm1_evt_write_sts(ar, val);
451 ar->pm1.evt.update_sci(ar);
452 break;
453 case 2:
454 acpi_pm1_evt_write_en(ar, val);
455 ar->pm1.evt.update_sci(ar);
456 break;
457 }
458}
459
460static const MemoryRegionOps acpi_pm_evt_ops = {
461 .read = acpi_pm_evt_read,
462 .write = acpi_pm_evt_write,
463 .valid.min_access_size = 2,
464 .valid.max_access_size = 2,
465 .endianness = DEVICE_LITTLE_ENDIAN,
466};
467
468void acpi_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
469 MemoryRegion *parent)
470{
471 ar->pm1.evt.update_sci = update_sci;
472 memory_region_init_io(&ar->pm1.evt.io, memory_region_owner(parent),
473 &acpi_pm_evt_ops, ar, "acpi-evt", 4);
474 memory_region_add_subregion(parent, 0, &ar->pm1.evt.io);
475}
476
477
478void acpi_pm_tmr_update(ACPIREGS *ar, bool enable)
479{
480 int64_t expire_time;
481
482
483 if (enable) {
484 expire_time = muldiv64(ar->tmr.overflow_time, NANOSECONDS_PER_SECOND,
485 PM_TIMER_FREQUENCY);
486 timer_mod(ar->tmr.timer, expire_time);
487 } else {
488 timer_del(ar->tmr.timer);
489 }
490}
491
492static inline int64_t acpi_pm_tmr_get_clock(void)
493{
494 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), PM_TIMER_FREQUENCY,
495 NANOSECONDS_PER_SECOND);
496}
497
498void acpi_pm_tmr_calc_overflow_time(ACPIREGS *ar)
499{
500 int64_t d = acpi_pm_tmr_get_clock();
501 ar->tmr.overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
502}
503
504static uint32_t acpi_pm_tmr_get(ACPIREGS *ar)
505{
506 uint32_t d = acpi_pm_tmr_get_clock();
507 return d & 0xffffff;
508}
509
510static void acpi_pm_tmr_timer(void *opaque)
511{
512 ACPIREGS *ar = opaque;
513
514 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_PMTIMER, NULL);
515 ar->tmr.update_sci(ar);
516}
517
518static uint64_t acpi_pm_tmr_read(void *opaque, hwaddr addr, unsigned width)
519{
520 return acpi_pm_tmr_get(opaque);
521}
522
523static void acpi_pm_tmr_write(void *opaque, hwaddr addr, uint64_t val,
524 unsigned width)
525{
526
527}
528
529static const MemoryRegionOps acpi_pm_tmr_ops = {
530 .read = acpi_pm_tmr_read,
531 .write = acpi_pm_tmr_write,
532 .valid.min_access_size = 4,
533 .valid.max_access_size = 4,
534 .endianness = DEVICE_LITTLE_ENDIAN,
535};
536
537void acpi_pm_tmr_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
538 MemoryRegion *parent)
539{
540 ar->tmr.update_sci = update_sci;
541 ar->tmr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, acpi_pm_tmr_timer, ar);
542 memory_region_init_io(&ar->tmr.io, memory_region_owner(parent),
543 &acpi_pm_tmr_ops, ar, "acpi-tmr", 4);
544 memory_region_add_subregion(parent, 8, &ar->tmr.io);
545}
546
547void acpi_pm_tmr_reset(ACPIREGS *ar)
548{
549 ar->tmr.overflow_time = 0;
550 timer_del(ar->tmr.timer);
551}
552
553
554static void acpi_pm1_cnt_write(ACPIREGS *ar, uint16_t val)
555{
556 ar->pm1.cnt.cnt = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
557
558 if (val & ACPI_BITMASK_SLEEP_ENABLE) {
559
560 uint16_t sus_typ = (val >> 10) & 7;
561 switch(sus_typ) {
562 case 0:
563 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
564 break;
565 case 1:
566 qemu_system_suspend_request();
567 break;
568 default:
569 if (sus_typ == ar->pm1.cnt.s4_val) {
570 qapi_event_send_suspend_disk();
571 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
572 }
573 break;
574 }
575 }
576}
577
578void acpi_pm1_cnt_update(ACPIREGS *ar,
579 bool sci_enable, bool sci_disable)
580{
581
582 if (sci_enable) {
583 ar->pm1.cnt.cnt |= ACPI_BITMASK_SCI_ENABLE;
584 } else if (sci_disable) {
585 ar->pm1.cnt.cnt &= ~ACPI_BITMASK_SCI_ENABLE;
586 }
587}
588
589static uint64_t acpi_pm_cnt_read(void *opaque, hwaddr addr, unsigned width)
590{
591 ACPIREGS *ar = opaque;
592 return ar->pm1.cnt.cnt;
593}
594
595static void acpi_pm_cnt_write(void *opaque, hwaddr addr, uint64_t val,
596 unsigned width)
597{
598 acpi_pm1_cnt_write(opaque, val);
599}
600
601static const MemoryRegionOps acpi_pm_cnt_ops = {
602 .read = acpi_pm_cnt_read,
603 .write = acpi_pm_cnt_write,
604 .valid.min_access_size = 2,
605 .valid.max_access_size = 2,
606 .endianness = DEVICE_LITTLE_ENDIAN,
607};
608
609void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent,
610 bool disable_s3, bool disable_s4, uint8_t s4_val)
611{
612 FWCfgState *fw_cfg;
613
614 ar->pm1.cnt.s4_val = s4_val;
615 ar->wakeup.notify = acpi_notify_wakeup;
616 qemu_register_wakeup_notifier(&ar->wakeup);
617
618
619
620
621 qemu_register_wakeup_support();
622
623 memory_region_init_io(&ar->pm1.cnt.io, memory_region_owner(parent),
624 &acpi_pm_cnt_ops, ar, "acpi-cnt", 2);
625 memory_region_add_subregion(parent, 4, &ar->pm1.cnt.io);
626
627 fw_cfg = fw_cfg_find();
628 if (fw_cfg) {
629 uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
630 suspend[3] = 1 | ((!disable_s3) << 7);
631 suspend[4] = s4_val | ((!disable_s4) << 7);
632
633 fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
634 }
635}
636
637void acpi_pm1_cnt_reset(ACPIREGS *ar)
638{
639 ar->pm1.cnt.cnt = 0;
640}
641
642
643void acpi_gpe_init(ACPIREGS *ar, uint8_t len)
644{
645 ar->gpe.len = len;
646
647
648
649
650 ar->gpe.sts = g_malloc0(len);
651 ar->gpe.en = g_malloc0(len);
652}
653
654void acpi_gpe_reset(ACPIREGS *ar)
655{
656 memset(ar->gpe.sts, 0, ar->gpe.len / 2);
657 memset(ar->gpe.en, 0, ar->gpe.len / 2);
658}
659
660static uint8_t *acpi_gpe_ioport_get_ptr(ACPIREGS *ar, uint32_t addr)
661{
662 uint8_t *cur = NULL;
663
664 if (addr < ar->gpe.len / 2) {
665 cur = ar->gpe.sts + addr;
666 } else if (addr < ar->gpe.len) {
667 cur = ar->gpe.en + addr - ar->gpe.len / 2;
668 } else {
669 abort();
670 }
671
672 return cur;
673}
674
675void acpi_gpe_ioport_writeb(ACPIREGS *ar, uint32_t addr, uint32_t val)
676{
677 uint8_t *cur;
678
679 cur = acpi_gpe_ioport_get_ptr(ar, addr);
680 if (addr < ar->gpe.len / 2) {
681
682 *cur = (*cur) & ~val;
683 } else if (addr < ar->gpe.len) {
684
685 *cur = val;
686 } else {
687 abort();
688 }
689}
690
691uint32_t acpi_gpe_ioport_readb(ACPIREGS *ar, uint32_t addr)
692{
693 uint8_t *cur;
694 uint32_t val;
695
696 cur = acpi_gpe_ioport_get_ptr(ar, addr);
697 val = 0;
698 if (cur != NULL) {
699 val = *cur;
700 }
701
702 return val;
703}
704
705void acpi_send_gpe_event(ACPIREGS *ar, qemu_irq irq,
706 AcpiEventStatusBits status)
707{
708 ar->gpe.sts[0] |= status;
709 acpi_update_sci(ar, irq);
710}
711
712void acpi_update_sci(ACPIREGS *regs, qemu_irq irq)
713{
714 int sci_level, pm1a_sts;
715
716 pm1a_sts = acpi_pm1_evt_get_sts(regs);
717
718 sci_level = ((pm1a_sts &
719 regs->pm1.evt.en & ACPI_BITMASK_PM1_COMMON_ENABLED) != 0) ||
720 ((regs->gpe.sts[0] & regs->gpe.en[0]) != 0);
721
722 qemu_set_irq(irq, sci_level);
723
724
725 acpi_pm_tmr_update(regs,
726 (regs->pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
727 !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
728}
729