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21#include "qemu/osdep.h"
22#include "hw/hw.h"
23#include "hw/i386/pc.h"
24#include "hw/isa/apm.h"
25#include "hw/i2c/pm_smbus.h"
26#include "hw/pci/pci.h"
27#include "hw/acpi/acpi.h"
28#include "sysemu/sysemu.h"
29#include "qapi/error.h"
30#include "qemu/range.h"
31#include "exec/address-spaces.h"
32#include "hw/acpi/piix4.h"
33#include "hw/acpi/pcihp.h"
34#include "hw/acpi/cpu_hotplug.h"
35#include "hw/acpi/cpu.h"
36#include "hw/hotplug.h"
37#include "hw/mem/pc-dimm.h"
38#include "hw/acpi/memory_hotplug.h"
39#include "hw/acpi/acpi_dev_interface.h"
40#include "hw/xen/xen.h"
41#include "qom/cpu.h"
42
43
44
45#ifdef DEBUG
46# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
47#else
48# define PIIX4_DPRINTF(format, ...) do { } while (0)
49#endif
50
51#define GPE_BASE 0xafe0
52#define GPE_LEN 4
53
54struct pci_status {
55 uint32_t up;
56 uint32_t down;
57};
58
59typedef struct PIIX4PMState {
60
61 PCIDevice parent_obj;
62
63
64 MemoryRegion io;
65 uint32_t io_base;
66
67 MemoryRegion io_gpe;
68 ACPIREGS ar;
69
70 APMState apm;
71
72 PMSMBus smb;
73 uint32_t smb_io_base;
74
75 qemu_irq irq;
76 qemu_irq smi_irq;
77 int smm_enabled;
78 Notifier machine_ready;
79 Notifier powerdown_notifier;
80
81 AcpiPciHpState acpi_pci_hotplug;
82 bool use_acpi_pci_hotplug;
83
84 uint8_t disable_s3;
85 uint8_t disable_s4;
86 uint8_t s4_val;
87
88 bool cpu_hotplug_legacy;
89 AcpiCpuHotplug gpe_cpu;
90 CPUHotplugState cpuhp_state;
91
92 MemHotplugState acpi_memory_hotplug;
93} PIIX4PMState;
94
95#define TYPE_PIIX4_PM "PIIX4_PM"
96
97#define PIIX4_PM(obj) \
98 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
99
100static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
101 PCIBus *bus, PIIX4PMState *s);
102
103#define ACPI_ENABLE 0xf1
104#define ACPI_DISABLE 0xf0
105
106static void pm_tmr_timer(ACPIREGS *ar)
107{
108 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
109 acpi_update_sci(&s->ar, s->irq);
110}
111
112static void apm_ctrl_changed(uint32_t val, void *arg)
113{
114 PIIX4PMState *s = arg;
115 PCIDevice *d = PCI_DEVICE(s);
116
117
118 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
119 if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
120 return;
121 }
122
123 if (d->config[0x5b] & (1 << 1)) {
124 if (s->smi_irq) {
125 qemu_irq_raise(s->smi_irq);
126 }
127 }
128}
129
130static void pm_io_space_update(PIIX4PMState *s)
131{
132 PCIDevice *d = PCI_DEVICE(s);
133
134 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
135 s->io_base &= 0xffc0;
136
137 memory_region_transaction_begin();
138 memory_region_set_enabled(&s->io, d->config[0x80] & 1);
139 memory_region_set_address(&s->io, s->io_base);
140 memory_region_transaction_commit();
141}
142
143static void smbus_io_space_update(PIIX4PMState *s)
144{
145 PCIDevice *d = PCI_DEVICE(s);
146
147 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
148 s->smb_io_base &= 0xffc0;
149
150 memory_region_transaction_begin();
151 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
152 memory_region_set_address(&s->smb.io, s->smb_io_base);
153 memory_region_transaction_commit();
154}
155
156static void pm_write_config(PCIDevice *d,
157 uint32_t address, uint32_t val, int len)
158{
159 pci_default_write_config(d, address, val, len);
160 if (range_covers_byte(address, len, 0x80) ||
161 ranges_overlap(address, len, 0x40, 4)) {
162 pm_io_space_update((PIIX4PMState *)d);
163 }
164 if (range_covers_byte(address, len, 0xd2) ||
165 ranges_overlap(address, len, 0x90, 4)) {
166 smbus_io_space_update((PIIX4PMState *)d);
167 }
168}
169
170static int vmstate_acpi_post_load(void *opaque, int version_id)
171{
172 PIIX4PMState *s = opaque;
173
174 pm_io_space_update(s);
175 smbus_io_space_update(s);
176 return 0;
177}
178
179#define VMSTATE_GPE_ARRAY(_field, _state) \
180 { \
181 .name = (stringify(_field)), \
182 .version_id = 0, \
183 .info = &vmstate_info_uint16, \
184 .size = sizeof(uint16_t), \
185 .flags = VMS_SINGLE | VMS_POINTER, \
186 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
187 }
188
189static const VMStateDescription vmstate_gpe = {
190 .name = "gpe",
191 .version_id = 1,
192 .minimum_version_id = 1,
193 .fields = (VMStateField[]) {
194 VMSTATE_GPE_ARRAY(sts, ACPIGPE),
195 VMSTATE_GPE_ARRAY(en, ACPIGPE),
196 VMSTATE_END_OF_LIST()
197 }
198};
199
200static const VMStateDescription vmstate_pci_status = {
201 .name = "pci_status",
202 .version_id = 1,
203 .minimum_version_id = 1,
204 .fields = (VMStateField[]) {
205 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
206 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
207 VMSTATE_END_OF_LIST()
208 }
209};
210
211static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
212{
213 PIIX4PMState *s = opaque;
214 int ret, i;
215 uint16_t temp;
216
217 ret = pci_device_load(PCI_DEVICE(s), f);
218 if (ret < 0) {
219 return ret;
220 }
221 qemu_get_be16s(f, &s->ar.pm1.evt.sts);
222 qemu_get_be16s(f, &s->ar.pm1.evt.en);
223 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
224
225 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
226 if (ret) {
227 return ret;
228 }
229
230 timer_get(f, s->ar.tmr.timer);
231 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
232
233 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
234 for (i = 0; i < 3; i++) {
235 qemu_get_be16s(f, &temp);
236 }
237
238 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
239 for (i = 0; i < 3; i++) {
240 qemu_get_be16s(f, &temp);
241 }
242
243 ret = vmstate_load_state(f, &vmstate_pci_status,
244 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
245 return ret;
246}
247
248static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
249{
250 PIIX4PMState *s = opaque;
251 return s->use_acpi_pci_hotplug;
252}
253
254static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
255{
256 PIIX4PMState *s = opaque;
257 return !s->use_acpi_pci_hotplug;
258}
259
260static bool vmstate_test_use_memhp(void *opaque)
261{
262 PIIX4PMState *s = opaque;
263 return s->acpi_memory_hotplug.is_enabled;
264}
265
266static const VMStateDescription vmstate_memhp_state = {
267 .name = "piix4_pm/memhp",
268 .version_id = 1,
269 .minimum_version_id = 1,
270 .minimum_version_id_old = 1,
271 .needed = vmstate_test_use_memhp,
272 .fields = (VMStateField[]) {
273 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
274 VMSTATE_END_OF_LIST()
275 }
276};
277
278static bool vmstate_test_use_cpuhp(void *opaque)
279{
280 PIIX4PMState *s = opaque;
281 return !s->cpu_hotplug_legacy;
282}
283
284static int vmstate_cpuhp_pre_load(void *opaque)
285{
286 Object *obj = OBJECT(opaque);
287 object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort);
288 return 0;
289}
290
291static const VMStateDescription vmstate_cpuhp_state = {
292 .name = "piix4_pm/cpuhp",
293 .version_id = 1,
294 .minimum_version_id = 1,
295 .minimum_version_id_old = 1,
296 .needed = vmstate_test_use_cpuhp,
297 .pre_load = vmstate_cpuhp_pre_load,
298 .fields = (VMStateField[]) {
299 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState),
300 VMSTATE_END_OF_LIST()
301 }
302};
303
304static bool piix4_vmstate_need_smbus(void *opaque, int version_id)
305{
306 return pm_smbus_vmstate_needed();
307}
308
309
310
311
312
313
314
315static const VMStateDescription vmstate_acpi = {
316 .name = "piix4_pm",
317 .version_id = 3,
318 .minimum_version_id = 3,
319 .minimum_version_id_old = 1,
320 .load_state_old = acpi_load_old,
321 .post_load = vmstate_acpi_post_load,
322 .fields = (VMStateField[]) {
323 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
324 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
325 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
326 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
327 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
328 VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3,
329 pmsmb_vmstate, PMSMBus),
330 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
331 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
332 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
333 VMSTATE_STRUCT_TEST(
334 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
335 PIIX4PMState,
336 vmstate_test_no_use_acpi_pci_hotplug,
337 2, vmstate_pci_status,
338 struct AcpiPciHpPciStatus),
339 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
340 vmstate_test_use_acpi_pci_hotplug),
341 VMSTATE_END_OF_LIST()
342 },
343 .subsections = (const VMStateDescription*[]) {
344 &vmstate_memhp_state,
345 &vmstate_cpuhp_state,
346 NULL
347 }
348};
349
350static void piix4_reset(void *opaque)
351{
352 PIIX4PMState *s = opaque;
353 PCIDevice *d = PCI_DEVICE(s);
354 uint8_t *pci_conf = d->config;
355
356 pci_conf[0x58] = 0;
357 pci_conf[0x59] = 0;
358 pci_conf[0x5a] = 0;
359 pci_conf[0x5b] = 0;
360
361 pci_conf[0x40] = 0x01;
362 pci_conf[0x80] = 0;
363
364 if (!s->smm_enabled) {
365
366 pci_conf[0x5B] = 0x02;
367 }
368 pm_io_space_update(s);
369 acpi_pcihp_reset(&s->acpi_pci_hotplug);
370}
371
372static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
373{
374 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
375
376 assert(s != NULL);
377 acpi_pm1_evt_power_down(&s->ar);
378}
379
380static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev,
381 DeviceState *dev, Error **errp)
382{
383 PIIX4PMState *s = PIIX4_PM(hotplug_dev);
384
385 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
386 acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp);
387 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
388 if (!s->acpi_memory_hotplug.is_enabled) {
389 error_setg(errp,
390 "memory hotplug is not enabled: %s.memory-hotplug-support "
391 "is not set", object_get_typename(OBJECT(s)));
392 }
393 } else if (
394 !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
395 error_setg(errp, "acpi: device pre plug request for not supported"
396 " device type: %s", object_get_typename(OBJECT(dev)));
397 }
398}
399
400static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
401 DeviceState *dev, Error **errp)
402{
403 PIIX4PMState *s = PIIX4_PM(hotplug_dev);
404
405 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
406 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
407 nvdimm_acpi_plug_cb(hotplug_dev, dev);
408 } else {
409 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug,
410 dev, errp);
411 }
412 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
413 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp);
414 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
415 if (s->cpu_hotplug_legacy) {
416 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp);
417 } else {
418 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
419 }
420 } else {
421 g_assert_not_reached();
422 }
423}
424
425static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
426 DeviceState *dev, Error **errp)
427{
428 PIIX4PMState *s = PIIX4_PM(hotplug_dev);
429
430 if (s->acpi_memory_hotplug.is_enabled &&
431 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
432 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug,
433 dev, errp);
434 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
435 acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug,
436 dev, errp);
437 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
438 !s->cpu_hotplug_legacy) {
439 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
440 } else {
441 error_setg(errp, "acpi: device unplug request for not supported device"
442 " type: %s", object_get_typename(OBJECT(dev)));
443 }
444}
445
446static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
447 DeviceState *dev, Error **errp)
448{
449 PIIX4PMState *s = PIIX4_PM(hotplug_dev);
450
451 if (s->acpi_memory_hotplug.is_enabled &&
452 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
453 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
455 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev,
456 errp);
457 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
458 !s->cpu_hotplug_legacy) {
459 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
460 } else {
461 error_setg(errp, "acpi: device unplug for not supported device"
462 " type: %s", object_get_typename(OBJECT(dev)));
463 }
464}
465
466static void piix4_pm_machine_ready(Notifier *n, void *opaque)
467{
468 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
469 PCIDevice *d = PCI_DEVICE(s);
470 MemoryRegion *io_as = pci_address_space_io(d);
471 uint8_t *pci_conf;
472
473 pci_conf = d->config;
474 pci_conf[0x5f] = 0x10 |
475 (memory_region_present(io_as, 0x378) ? 0x80 : 0);
476 pci_conf[0x63] = 0x60;
477 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
478 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
479}
480
481static void piix4_pm_add_propeties(PIIX4PMState *s)
482{
483 static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
484 static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
485 static const uint32_t gpe0_blk = GPE_BASE;
486 static const uint32_t gpe0_blk_len = GPE_LEN;
487 static const uint16_t sci_int = 9;
488
489 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
490 &acpi_enable_cmd, NULL);
491 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
492 &acpi_disable_cmd, NULL);
493 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
494 &gpe0_blk, NULL);
495 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
496 &gpe0_blk_len, NULL);
497 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
498 &sci_int, NULL);
499 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
500 &s->io_base, NULL);
501}
502
503static void piix4_pm_realize(PCIDevice *dev, Error **errp)
504{
505 PIIX4PMState *s = PIIX4_PM(dev);
506 uint8_t *pci_conf;
507
508 pci_conf = dev->config;
509 pci_conf[0x06] = 0x80;
510 pci_conf[0x07] = 0x02;
511 pci_conf[0x09] = 0x00;
512 pci_conf[0x3d] = 0x01;
513
514
515 apm_init(dev, &s->apm, apm_ctrl_changed, s);
516
517 if (!s->smm_enabled) {
518
519
520 pci_conf[0x5B] = 0x02;
521 }
522
523
524
525 pci_conf[0x90] = s->smb_io_base | 1;
526 pci_conf[0x91] = s->smb_io_base >> 8;
527 pci_conf[0xd2] = 0x09;
528 pm_smbus_init(DEVICE(dev), &s->smb, true);
529 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
530 memory_region_add_subregion(pci_address_space_io(dev),
531 s->smb_io_base, &s->smb.io);
532
533 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
534 memory_region_set_enabled(&s->io, false);
535 memory_region_add_subregion(pci_address_space_io(dev),
536 0, &s->io);
537
538 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
539 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
540 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val);
541 acpi_gpe_init(&s->ar, GPE_LEN);
542
543 s->powerdown_notifier.notify = piix4_pm_powerdown_req;
544 qemu_register_powerdown_notifier(&s->powerdown_notifier);
545
546 s->machine_ready.notify = piix4_pm_machine_ready;
547 qemu_add_machine_init_done_notifier(&s->machine_ready);
548 qemu_register_reset(piix4_reset, s);
549
550 piix4_acpi_system_hot_add_init(pci_address_space_io(dev),
551 pci_get_bus(dev), s);
552 qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s), &error_abort);
553
554 piix4_pm_add_propeties(s);
555}
556
557Object *piix4_pm_find(void)
558{
559 bool ambig;
560 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
561
562 if (ambig || !o) {
563 return NULL;
564 }
565 return o;
566}
567
568I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
569 qemu_irq sci_irq, qemu_irq smi_irq,
570 int smm_enabled, DeviceState **piix4_pm)
571{
572 DeviceState *dev;
573 PIIX4PMState *s;
574
575 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
576 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
577 if (piix4_pm) {
578 *piix4_pm = dev;
579 }
580
581 s = PIIX4_PM(dev);
582 s->irq = sci_irq;
583 s->smi_irq = smi_irq;
584 s->smm_enabled = smm_enabled;
585 if (xen_enabled()) {
586 s->use_acpi_pci_hotplug = false;
587 }
588
589 qdev_init_nofail(dev);
590
591 return s->smb.smbus;
592}
593
594static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
595{
596 PIIX4PMState *s = opaque;
597 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
598
599 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
600 return val;
601}
602
603static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
604 unsigned width)
605{
606 PIIX4PMState *s = opaque;
607
608 acpi_gpe_ioport_writeb(&s->ar, addr, val);
609 acpi_update_sci(&s->ar, s->irq);
610
611 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
612}
613
614static const MemoryRegionOps piix4_gpe_ops = {
615 .read = gpe_readb,
616 .write = gpe_writeb,
617 .valid.min_access_size = 1,
618 .valid.max_access_size = 4,
619 .impl.min_access_size = 1,
620 .impl.max_access_size = 1,
621 .endianness = DEVICE_LITTLE_ENDIAN,
622};
623
624
625static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp)
626{
627 PIIX4PMState *s = PIIX4_PM(obj);
628
629 return s->cpu_hotplug_legacy;
630}
631
632static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp)
633{
634 PIIX4PMState *s = PIIX4_PM(obj);
635
636 assert(!value);
637 if (s->cpu_hotplug_legacy && value == false) {
638 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state,
639 PIIX4_CPU_HOTPLUG_IO_BASE);
640 }
641 s->cpu_hotplug_legacy = value;
642}
643
644static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
645 PCIBus *bus, PIIX4PMState *s)
646{
647 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
648 "acpi-gpe0", GPE_LEN);
649 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
650
651 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
652 s->use_acpi_pci_hotplug);
653
654 s->cpu_hotplug_legacy = true;
655 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy",
656 piix4_get_cpu_hotplug_legacy,
657 piix4_set_cpu_hotplug_legacy,
658 NULL);
659 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
660 PIIX4_CPU_HOTPLUG_IO_BASE);
661
662 if (s->acpi_memory_hotplug.is_enabled) {
663 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug,
664 ACPI_MEMORY_HOTPLUG_BASE);
665 }
666}
667
668static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
669{
670 PIIX4PMState *s = PIIX4_PM(adev);
671
672 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
673 if (!s->cpu_hotplug_legacy) {
674 acpi_cpu_ospm_status(&s->cpuhp_state, list);
675 }
676}
677
678static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
679{
680 PIIX4PMState *s = PIIX4_PM(adev);
681
682 acpi_send_gpe_event(&s->ar, s->irq, ev);
683}
684
685static Property piix4_pm_properties[] = {
686 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
687 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
688 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
689 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
690 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
691 use_acpi_pci_hotplug, true),
692 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
693 acpi_memory_hotplug.is_enabled, true),
694 DEFINE_PROP_END_OF_LIST(),
695};
696
697static void piix4_pm_class_init(ObjectClass *klass, void *data)
698{
699 DeviceClass *dc = DEVICE_CLASS(klass);
700 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
701 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
702 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
703
704 k->realize = piix4_pm_realize;
705 k->config_write = pm_write_config;
706 k->vendor_id = PCI_VENDOR_ID_INTEL;
707 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
708 k->revision = 0x03;
709 k->class_id = PCI_CLASS_BRIDGE_OTHER;
710 dc->desc = "PM";
711 dc->vmsd = &vmstate_acpi;
712 dc->props = piix4_pm_properties;
713
714
715
716
717 dc->user_creatable = false;
718 dc->hotpluggable = false;
719 hc->pre_plug = piix4_device_pre_plug_cb;
720 hc->plug = piix4_device_plug_cb;
721 hc->unplug_request = piix4_device_unplug_request_cb;
722 hc->unplug = piix4_device_unplug_cb;
723 adevc->ospm_status = piix4_ospm_status;
724 adevc->send_event = piix4_send_gpe;
725 adevc->madt_cpu = pc_madt_cpu_entry;
726}
727
728static const TypeInfo piix4_pm_info = {
729 .name = TYPE_PIIX4_PM,
730 .parent = TYPE_PCI_DEVICE,
731 .instance_size = sizeof(PIIX4PMState),
732 .class_init = piix4_pm_class_init,
733 .interfaces = (InterfaceInfo[]) {
734 { TYPE_HOTPLUG_HANDLER },
735 { TYPE_ACPI_DEVICE_IF },
736 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
737 { }
738 }
739};
740
741static void piix4_pm_register_types(void)
742{
743 type_register_static(&piix4_pm_info);
744}
745
746type_init(piix4_pm_register_types)
747
