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10#include "qemu/osdep.h"
11#include "hw/arm/armv7m.h"
12#include "qapi/error.h"
13#include "qemu-common.h"
14#include "cpu.h"
15#include "hw/sysbus.h"
16#include "hw/arm/arm.h"
17#include "hw/loader.h"
18#include "elf.h"
19#include "sysemu/qtest.h"
20#include "qemu/error-report.h"
21#include "exec/address-spaces.h"
22#include "target/arm/idau.h"
23
24
25
26
27static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
28{
29 return s->base | (offset & 0x1ffffff) >> 5;
30}
31
32static MemTxResult bitband_read(void *opaque, hwaddr offset,
33 uint64_t *data, unsigned size, MemTxAttrs attrs)
34{
35 BitBandState *s = opaque;
36 uint8_t buf[4];
37 MemTxResult res;
38 int bitpos, bit;
39 hwaddr addr;
40
41 assert(size <= 4);
42
43
44 addr = bitband_addr(s, offset) & (-size);
45 res = address_space_read(&s->source_as, addr, attrs, buf, size);
46 if (res) {
47 return res;
48 }
49
50 bitpos = (offset >> 2) & ((size * 8) - 1);
51
52 bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
53 *data = bit;
54 return MEMTX_OK;
55}
56
57static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
58 unsigned size, MemTxAttrs attrs)
59{
60 BitBandState *s = opaque;
61 uint8_t buf[4];
62 MemTxResult res;
63 int bitpos, bit;
64 hwaddr addr;
65
66 assert(size <= 4);
67
68
69 addr = bitband_addr(s, offset) & (-size);
70 res = address_space_read(&s->source_as, addr, attrs, buf, size);
71 if (res) {
72 return res;
73 }
74
75 bitpos = (offset >> 2) & ((size * 8) - 1);
76
77 bit = 1 << (bitpos & 7);
78 if (value & 1) {
79 buf[bitpos >> 3] |= bit;
80 } else {
81 buf[bitpos >> 3] &= ~bit;
82 }
83 return address_space_write(&s->source_as, addr, attrs, buf, size);
84}
85
86static const MemoryRegionOps bitband_ops = {
87 .read_with_attrs = bitband_read,
88 .write_with_attrs = bitband_write,
89 .endianness = DEVICE_NATIVE_ENDIAN,
90 .impl.min_access_size = 1,
91 .impl.max_access_size = 4,
92 .valid.min_access_size = 1,
93 .valid.max_access_size = 4,
94};
95
96static void bitband_init(Object *obj)
97{
98 BitBandState *s = BITBAND(obj);
99 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
100
101 memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
102 "bitband", 0x02000000);
103 sysbus_init_mmio(dev, &s->iomem);
104}
105
106static void bitband_realize(DeviceState *dev, Error **errp)
107{
108 BitBandState *s = BITBAND(dev);
109
110 if (!s->source_memory) {
111 error_setg(errp, "source-memory property not set");
112 return;
113 }
114
115 address_space_init(&s->source_as, s->source_memory, "bitband-source");
116}
117
118
119
120static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
121 0x20000000, 0x40000000
122};
123
124static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
125 0x22000000, 0x42000000
126};
127
128static void armv7m_instance_init(Object *obj)
129{
130 ARMv7MState *s = ARMV7M(obj);
131 int i;
132
133
134
135 memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
136
137 sysbus_init_child_obj(obj, "nvnic", &s->nvic, sizeof(s->nvic), TYPE_NVIC);
138 object_property_add_alias(obj, "num-irq",
139 OBJECT(&s->nvic), "num-irq", &error_abort);
140
141 for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
142 sysbus_init_child_obj(obj, "bitband[*]", &s->bitband[i],
143 sizeof(s->bitband[i]), TYPE_BITBAND);
144 }
145}
146
147static void armv7m_realize(DeviceState *dev, Error **errp)
148{
149 ARMv7MState *s = ARMV7M(dev);
150 SysBusDevice *sbd;
151 Error *err = NULL;
152 int i;
153
154 if (!s->board_memory) {
155 error_setg(errp, "memory property was not set");
156 return;
157 }
158
159 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
160
161 s->cpu = ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu",
162 &err, NULL));
163 if (err != NULL) {
164 error_propagate(errp, err);
165 return;
166 }
167
168 object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
169 &error_abort);
170 if (object_property_find(OBJECT(s->cpu), "idau", NULL)) {
171 object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err);
172 if (err != NULL) {
173 error_propagate(errp, err);
174 return;
175 }
176 }
177 if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) {
178 object_property_set_uint(OBJECT(s->cpu), s->init_svtor,
179 "init-svtor", &err);
180 if (err != NULL) {
181 error_propagate(errp, err);
182 return;
183 }
184 }
185 if (object_property_find(OBJECT(s->cpu), "start-powered-off", NULL)) {
186 object_property_set_bool(OBJECT(s->cpu), s->start_powered_off,
187 "start-powered-off", &err);
188 if (err != NULL) {
189 error_propagate(errp, err);
190 return;
191 }
192 }
193
194
195
196
197
198 s->cpu->env.nvic = &s->nvic;
199 s->nvic.cpu = s->cpu;
200
201 object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
202 if (err != NULL) {
203 error_propagate(errp, err);
204 return;
205 }
206
207
208 object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
209 if (err != NULL) {
210 error_propagate(errp, err);
211 return;
212 }
213
214
215
216
217
218 qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
219 qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
220 qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");
221
222
223 sbd = SYS_BUS_DEVICE(&s->nvic);
224 sysbus_connect_irq(sbd, 0,
225 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
226
227 memory_region_add_subregion(&s->container, 0xe000e000,
228 sysbus_mmio_get_region(sbd, 0));
229
230 if (s->enable_bitband) {
231 for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
232 Object *obj = OBJECT(&s->bitband[i]);
233 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
234
235 object_property_set_int(obj, bitband_input_addr[i], "base", &err);
236 if (err != NULL) {
237 error_propagate(errp, err);
238 return;
239 }
240 object_property_set_link(obj, OBJECT(s->board_memory),
241 "source-memory", &error_abort);
242 object_property_set_bool(obj, true, "realized", &err);
243 if (err != NULL) {
244 error_propagate(errp, err);
245 return;
246 }
247
248 memory_region_add_subregion(&s->container, bitband_output_addr[i],
249 sysbus_mmio_get_region(sbd, 0));
250 }
251 }
252}
253
254static Property armv7m_properties[] = {
255 DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
256 DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
257 MemoryRegion *),
258 DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
259 DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
260 DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false),
261 DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off,
262 false),
263 DEFINE_PROP_END_OF_LIST(),
264};
265
266static void armv7m_class_init(ObjectClass *klass, void *data)
267{
268 DeviceClass *dc = DEVICE_CLASS(klass);
269
270 dc->realize = armv7m_realize;
271 dc->props = armv7m_properties;
272}
273
274static const TypeInfo armv7m_info = {
275 .name = TYPE_ARMV7M,
276 .parent = TYPE_SYS_BUS_DEVICE,
277 .instance_size = sizeof(ARMv7MState),
278 .instance_init = armv7m_instance_init,
279 .class_init = armv7m_class_init,
280};
281
282static void armv7m_reset(void *opaque)
283{
284 ARMCPU *cpu = opaque;
285
286 cpu_reset(CPU(cpu));
287}
288
289void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
290{
291 int image_size;
292 uint64_t entry;
293 uint64_t lowaddr;
294 int big_endian;
295 AddressSpace *as;
296 int asidx;
297 CPUState *cs = CPU(cpu);
298
299#ifdef TARGET_WORDS_BIGENDIAN
300 big_endian = 1;
301#else
302 big_endian = 0;
303#endif
304
305 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
306 asidx = ARMASIdx_S;
307 } else {
308 asidx = ARMASIdx_NS;
309 }
310 as = cpu_get_address_space(cs, asidx);
311
312 if (kernel_filename) {
313 image_size = load_elf_as(kernel_filename, NULL, NULL, NULL,
314 &entry, &lowaddr,
315 NULL, big_endian, EM_ARM, 1, 0, as);
316 if (image_size < 0) {
317 image_size = load_image_targphys_as(kernel_filename, 0,
318 mem_size, as);
319 lowaddr = 0;
320 }
321 if (image_size < 0) {
322 error_report("Could not load kernel '%s'", kernel_filename);
323 exit(1);
324 }
325 }
326
327
328
329
330
331
332
333
334
335 qemu_register_reset(armv7m_reset, cpu);
336}
337
338static Property bitband_properties[] = {
339 DEFINE_PROP_UINT32("base", BitBandState, base, 0),
340 DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,
341 TYPE_MEMORY_REGION, MemoryRegion *),
342 DEFINE_PROP_END_OF_LIST(),
343};
344
345static void bitband_class_init(ObjectClass *klass, void *data)
346{
347 DeviceClass *dc = DEVICE_CLASS(klass);
348
349 dc->realize = bitband_realize;
350 dc->props = bitband_properties;
351}
352
353static const TypeInfo bitband_info = {
354 .name = TYPE_BITBAND,
355 .parent = TYPE_SYS_BUS_DEVICE,
356 .instance_size = sizeof(BitBandState),
357 .instance_init = bitband_init,
358 .class_init = bitband_class_init,
359};
360
361static void armv7m_register_types(void)
362{
363 type_register_static(&bitband_info);
364 type_register_static(&armv7m_info);
365}
366
367type_init(armv7m_register_types)
368