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25#include "qemu/osdep.h"
26#include "qapi/error.h"
27#include "qemu-common.h"
28#include "cpu.h"
29#include "hw/arm/fsl-imx25.h"
30#include "sysemu/sysemu.h"
31#include "exec/address-spaces.h"
32#include "hw/boards.h"
33#include "chardev/char.h"
34
35static void fsl_imx25_init(Object *obj)
36{
37 FslIMX25State *s = FSL_IMX25(obj);
38 int i;
39
40 object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);
41
42 sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
43 TYPE_IMX_AVIC);
44
45 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);
46
47 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
48 sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
49 TYPE_IMX_SERIAL);
50 }
51
52 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
53 sysbus_init_child_obj(obj, "gpt[*]", &s->gpt[i], sizeof(s->gpt[i]),
54 TYPE_IMX25_GPT);
55 }
56
57 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
58 sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
59 TYPE_IMX_EPIT);
60 }
61
62 sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC);
63
64 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
65 sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
66 TYPE_IMX_I2C);
67 }
68
69 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
70 sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
71 TYPE_IMX_GPIO);
72 }
73}
74
75static void fsl_imx25_realize(DeviceState *dev, Error **errp)
76{
77 FslIMX25State *s = FSL_IMX25(dev);
78 uint8_t i;
79 Error *err = NULL;
80
81 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
82 if (err) {
83 error_propagate(errp, err);
84 return;
85 }
86
87 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
88 if (err) {
89 error_propagate(errp, err);
90 return;
91 }
92 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
93 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
94 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
95 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
96 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
97
98 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
99 if (err) {
100 error_propagate(errp, err);
101 return;
102 }
103 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
104
105
106 for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
107 static const struct {
108 hwaddr addr;
109 unsigned int irq;
110 } serial_table[FSL_IMX25_NUM_UARTS] = {
111 { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
112 { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
113 { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
114 { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
115 { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
116 };
117
118 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
119
120 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
121 if (err) {
122 error_propagate(errp, err);
123 return;
124 }
125 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
126 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
127 qdev_get_gpio_in(DEVICE(&s->avic),
128 serial_table[i].irq));
129 }
130
131
132 for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
133 static const struct {
134 hwaddr addr;
135 unsigned int irq;
136 } gpt_table[FSL_IMX25_NUM_GPTS] = {
137 { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
138 { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
139 { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
140 { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
141 };
142
143 s->gpt[i].ccm = IMX_CCM(&s->ccm);
144
145 object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
146 if (err) {
147 error_propagate(errp, err);
148 return;
149 }
150 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
151 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
152 qdev_get_gpio_in(DEVICE(&s->avic),
153 gpt_table[i].irq));
154 }
155
156
157 for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
158 static const struct {
159 hwaddr addr;
160 unsigned int irq;
161 } epit_table[FSL_IMX25_NUM_EPITS] = {
162 { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
163 { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
164 };
165
166 s->epit[i].ccm = IMX_CCM(&s->ccm);
167
168 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
169 if (err) {
170 error_propagate(errp, err);
171 return;
172 }
173 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
174 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
175 qdev_get_gpio_in(DEVICE(&s->avic),
176 epit_table[i].irq));
177 }
178
179 qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
180
181 object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
182 if (err) {
183 error_propagate(errp, err);
184 return;
185 }
186 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
187 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
188 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
189
190
191
192 for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
193 static const struct {
194 hwaddr addr;
195 unsigned int irq;
196 } i2c_table[FSL_IMX25_NUM_I2CS] = {
197 { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
198 { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
199 { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
200 };
201
202 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
203 if (err) {
204 error_propagate(errp, err);
205 return;
206 }
207 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
208 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
209 qdev_get_gpio_in(DEVICE(&s->avic),
210 i2c_table[i].irq));
211 }
212
213
214 for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
215 static const struct {
216 hwaddr addr;
217 unsigned int irq;
218 } gpio_table[FSL_IMX25_NUM_GPIOS] = {
219 { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
220 { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
221 { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
222 { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
223 };
224
225 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
226 if (err) {
227 error_propagate(errp, err);
228 return;
229 }
230 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
231
232 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
233 qdev_get_gpio_in(DEVICE(&s->avic),
234 gpio_table[i].irq));
235 }
236
237
238 memory_region_init_rom(&s->rom[0], NULL,
239 "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
240 if (err) {
241 error_propagate(errp, err);
242 return;
243 }
244 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
245 &s->rom[0]);
246 memory_region_init_rom(&s->rom[1], NULL,
247 "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
248 if (err) {
249 error_propagate(errp, err);
250 return;
251 }
252 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
253 &s->rom[1]);
254
255
256 memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
257 &err);
258 if (err) {
259 error_propagate(errp, err);
260 return;
261 }
262 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
263 &s->iram);
264
265
266 memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",
267 &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
268 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
269 &s->iram_alias);
270}
271
272static void fsl_imx25_class_init(ObjectClass *oc, void *data)
273{
274 DeviceClass *dc = DEVICE_CLASS(oc);
275
276 dc->realize = fsl_imx25_realize;
277 dc->desc = "i.MX25 SOC";
278
279
280
281
282 dc->user_creatable = false;
283}
284
285static const TypeInfo fsl_imx25_type_info = {
286 .name = TYPE_FSL_IMX25,
287 .parent = TYPE_DEVICE,
288 .instance_size = sizeof(FslIMX25State),
289 .instance_init = fsl_imx25_init,
290 .class_init = fsl_imx25_class_init,
291};
292
293static void fsl_imx25_register_types(void)
294{
295 type_register_static(&fsl_imx25_type_info);
296}
297
298type_init(fsl_imx25_register_types)
299
