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31#include "qemu/osdep.h"
32#include "qemu/units.h"
33#include "qapi/error.h"
34#include "hw/sysbus.h"
35#include "hw/arm/arm.h"
36#include "hw/arm/primecell.h"
37#include "hw/arm/virt.h"
38#include "hw/block/flash.h"
39#include "hw/vfio/vfio-calxeda-xgmac.h"
40#include "hw/vfio/vfio-amd-xgbe.h"
41#include "hw/display/ramfb.h"
42#include "net/net.h"
43#include "sysemu/device_tree.h"
44#include "sysemu/numa.h"
45#include "sysemu/sysemu.h"
46#include "sysemu/kvm.h"
47#include "hw/loader.h"
48#include "exec/address-spaces.h"
49#include "qemu/bitops.h"
50#include "qemu/error-report.h"
51#include "hw/pci-host/gpex.h"
52#include "hw/arm/sysbus-fdt.h"
53#include "hw/platform-bus.h"
54#include "hw/arm/fdt.h"
55#include "hw/intc/arm_gic.h"
56#include "hw/intc/arm_gicv3_common.h"
57#include "kvm_arm.h"
58#include "hw/firmware/smbios.h"
59#include "qapi/visitor.h"
60#include "standard-headers/linux/input.h"
61#include "hw/arm/smmuv3.h"
62#include "hw/acpi/acpi.h"
63#include "target/arm/internals.h"
64
65#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
66 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
67 void *data) \
68 { \
69 MachineClass *mc = MACHINE_CLASS(oc); \
70 virt_machine_##major##_##minor##_options(mc); \
71 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
72 if (latest) { \
73 mc->alias = "virt"; \
74 } \
75 } \
76 static const TypeInfo machvirt_##major##_##minor##_info = { \
77 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
78 .parent = TYPE_VIRT_MACHINE, \
79 .class_init = virt_##major##_##minor##_class_init, \
80 }; \
81 static void machvirt_machine_##major##_##minor##_init(void) \
82 { \
83 type_register_static(&machvirt_##major##_##minor##_info); \
84 } \
85 type_init(machvirt_machine_##major##_##minor##_init);
86
87#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
88 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
89#define DEFINE_VIRT_MACHINE(major, minor) \
90 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
91
92
93
94#define NUM_IRQS 256
95
96#define PLATFORM_BUS_NUM_IRQS 64
97
98
99#define LEGACY_RAMLIMIT_GB 255
100#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
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113
114static const MemMapEntry base_memmap[] = {
115
116 [VIRT_FLASH] = { 0, 0x08000000 },
117 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
118
119 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
120 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
121 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
122 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
123 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
124
125 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
126
127 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
128 [VIRT_UART] = { 0x09000000, 0x00001000 },
129 [VIRT_RTC] = { 0x09010000, 0x00001000 },
130 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
131 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
132 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
133 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
134 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
135
136 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
137 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
138 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
139 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
140 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
141
142 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
143};
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154
155static MemMapEntry extended_memmap[] = {
156
157 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
158 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
159
160 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
161};
162
163static const int a15irqmap[] = {
164 [VIRT_UART] = 1,
165 [VIRT_RTC] = 2,
166 [VIRT_PCIE] = 3,
167 [VIRT_GPIO] = 7,
168 [VIRT_SECURE_UART] = 8,
169 [VIRT_MMIO] = 16,
170 [VIRT_GIC_V2M] = 48,
171 [VIRT_SMMU] = 74,
172 [VIRT_PLATFORM_BUS] = 112,
173};
174
175static const char *valid_cpus[] = {
176 ARM_CPU_TYPE_NAME("cortex-a15"),
177 ARM_CPU_TYPE_NAME("cortex-a53"),
178 ARM_CPU_TYPE_NAME("cortex-a57"),
179 ARM_CPU_TYPE_NAME("cortex-a72"),
180 ARM_CPU_TYPE_NAME("host"),
181 ARM_CPU_TYPE_NAME("max"),
182};
183
184static bool cpu_type_valid(const char *cpu)
185{
186 int i;
187
188 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
189 if (strcmp(cpu, valid_cpus[i]) == 0) {
190 return true;
191 }
192 }
193 return false;
194}
195
196static void create_fdt(VirtMachineState *vms)
197{
198 void *fdt = create_device_tree(&vms->fdt_size);
199
200 if (!fdt) {
201 error_report("create_device_tree() failed");
202 exit(1);
203 }
204
205 vms->fdt = fdt;
206
207
208 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
209 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
210 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
211
212
213 qemu_fdt_add_subnode(fdt, "/chosen");
214
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220 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
221 qemu_fdt_add_subnode(fdt, "/apb-pclk");
222 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
223 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
224 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
225 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
226 "clk24mhz");
227 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
228
229 if (have_numa_distance) {
230 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
231 uint32_t *matrix = g_malloc0(size);
232 int idx, i, j;
233
234 for (i = 0; i < nb_numa_nodes; i++) {
235 for (j = 0; j < nb_numa_nodes; j++) {
236 idx = (i * nb_numa_nodes + j) * 3;
237 matrix[idx + 0] = cpu_to_be32(i);
238 matrix[idx + 1] = cpu_to_be32(j);
239 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
240 }
241 }
242
243 qemu_fdt_add_subnode(fdt, "/distance-map");
244 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
245 "numa-distance-map-v1");
246 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
247 matrix, size);
248 g_free(matrix);
249 }
250}
251
252static void fdt_add_timer_nodes(const VirtMachineState *vms)
253{
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271
272 ARMCPU *armcpu;
273 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
274 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
275
276 if (vmc->claim_edge_triggered_timers) {
277 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
278 }
279
280 if (vms->gic_version == 2) {
281 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
282 GIC_FDT_IRQ_PPI_CPU_WIDTH,
283 (1 << vms->smp_cpus) - 1);
284 }
285
286 qemu_fdt_add_subnode(vms->fdt, "/timer");
287
288 armcpu = ARM_CPU(qemu_get_cpu(0));
289 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
290 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
291 qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
292 compat, sizeof(compat));
293 } else {
294 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
295 "arm,armv7-timer");
296 }
297 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
298 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
299 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
300 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
301 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
302 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
303}
304
305static void fdt_add_cpu_nodes(const VirtMachineState *vms)
306{
307 int cpu;
308 int addr_cells = 1;
309 const MachineState *ms = MACHINE(vms);
310
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323
324 for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
325 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
326
327 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
328 addr_cells = 2;
329 break;
330 }
331 }
332
333 qemu_fdt_add_subnode(vms->fdt, "/cpus");
334 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
335 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
336
337 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
338 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
339 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
340 CPUState *cs = CPU(armcpu);
341
342 qemu_fdt_add_subnode(vms->fdt, nodename);
343 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
344 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
345 armcpu->dtb_compatible);
346
347 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
348 && vms->smp_cpus > 1) {
349 qemu_fdt_setprop_string(vms->fdt, nodename,
350 "enable-method", "psci");
351 }
352
353 if (addr_cells == 2) {
354 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
355 armcpu->mp_affinity);
356 } else {
357 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
358 armcpu->mp_affinity);
359 }
360
361 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
362 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
363 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
364 }
365
366 g_free(nodename);
367 }
368}
369
370static void fdt_add_its_gic_node(VirtMachineState *vms)
371{
372 char *nodename;
373
374 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
375 nodename = g_strdup_printf("/intc/its@%" PRIx64,
376 vms->memmap[VIRT_GIC_ITS].base);
377 qemu_fdt_add_subnode(vms->fdt, nodename);
378 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
379 "arm,gic-v3-its");
380 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
381 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
382 2, vms->memmap[VIRT_GIC_ITS].base,
383 2, vms->memmap[VIRT_GIC_ITS].size);
384 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
385 g_free(nodename);
386}
387
388static void fdt_add_v2m_gic_node(VirtMachineState *vms)
389{
390 char *nodename;
391
392 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
393 vms->memmap[VIRT_GIC_V2M].base);
394 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
395 qemu_fdt_add_subnode(vms->fdt, nodename);
396 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
397 "arm,gic-v2m-frame");
398 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
399 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
400 2, vms->memmap[VIRT_GIC_V2M].base,
401 2, vms->memmap[VIRT_GIC_V2M].size);
402 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
403 g_free(nodename);
404}
405
406static void fdt_add_gic_node(VirtMachineState *vms)
407{
408 char *nodename;
409
410 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
411 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
412
413 nodename = g_strdup_printf("/intc@%" PRIx64,
414 vms->memmap[VIRT_GIC_DIST].base);
415 qemu_fdt_add_subnode(vms->fdt, nodename);
416 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3);
417 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0);
418 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
419 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
420 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
421 if (vms->gic_version == 3) {
422 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
423
424 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
425 "arm,gic-v3");
426
427 qemu_fdt_setprop_cell(vms->fdt, nodename,
428 "#redistributor-regions", nb_redist_regions);
429
430 if (nb_redist_regions == 1) {
431 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
432 2, vms->memmap[VIRT_GIC_DIST].base,
433 2, vms->memmap[VIRT_GIC_DIST].size,
434 2, vms->memmap[VIRT_GIC_REDIST].base,
435 2, vms->memmap[VIRT_GIC_REDIST].size);
436 } else {
437 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
438 2, vms->memmap[VIRT_GIC_DIST].base,
439 2, vms->memmap[VIRT_GIC_DIST].size,
440 2, vms->memmap[VIRT_GIC_REDIST].base,
441 2, vms->memmap[VIRT_GIC_REDIST].size,
442 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
443 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
444 }
445
446 if (vms->virt) {
447 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
448 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
449 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
450 }
451 } else {
452
453 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
454 "arm,cortex-a15-gic");
455 if (!vms->virt) {
456 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
457 2, vms->memmap[VIRT_GIC_DIST].base,
458 2, vms->memmap[VIRT_GIC_DIST].size,
459 2, vms->memmap[VIRT_GIC_CPU].base,
460 2, vms->memmap[VIRT_GIC_CPU].size);
461 } else {
462 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
463 2, vms->memmap[VIRT_GIC_DIST].base,
464 2, vms->memmap[VIRT_GIC_DIST].size,
465 2, vms->memmap[VIRT_GIC_CPU].base,
466 2, vms->memmap[VIRT_GIC_CPU].size,
467 2, vms->memmap[VIRT_GIC_HYP].base,
468 2, vms->memmap[VIRT_GIC_HYP].size,
469 2, vms->memmap[VIRT_GIC_VCPU].base,
470 2, vms->memmap[VIRT_GIC_VCPU].size);
471 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
472 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
473 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
474 }
475 }
476
477 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle);
478 g_free(nodename);
479}
480
481static void fdt_add_pmu_nodes(const VirtMachineState *vms)
482{
483 CPUState *cpu;
484 ARMCPU *armcpu;
485 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
486
487 CPU_FOREACH(cpu) {
488 armcpu = ARM_CPU(cpu);
489 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
490 return;
491 }
492 if (kvm_enabled()) {
493 if (kvm_irqchip_in_kernel()) {
494 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
495 }
496 kvm_arm_pmu_init(cpu);
497 }
498 }
499
500 if (vms->gic_version == 2) {
501 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
502 GIC_FDT_IRQ_PPI_CPU_WIDTH,
503 (1 << vms->smp_cpus) - 1);
504 }
505
506 armcpu = ARM_CPU(qemu_get_cpu(0));
507 qemu_fdt_add_subnode(vms->fdt, "/pmu");
508 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
509 const char compat[] = "arm,armv8-pmuv3";
510 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
511 compat, sizeof(compat));
512 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
513 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
514 }
515}
516
517static void create_its(VirtMachineState *vms, DeviceState *gicdev)
518{
519 const char *itsclass = its_class_name();
520 DeviceState *dev;
521
522 if (!itsclass) {
523
524 return;
525 }
526
527 dev = qdev_create(NULL, itsclass);
528
529 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
530 &error_abort);
531 qdev_init_nofail(dev);
532 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
533
534 fdt_add_its_gic_node(vms);
535}
536
537static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
538{
539 int i;
540 int irq = vms->irqmap[VIRT_GIC_V2M];
541 DeviceState *dev;
542
543 dev = qdev_create(NULL, "arm-gicv2m");
544 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
545 qdev_prop_set_uint32(dev, "base-spi", irq);
546 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
547 qdev_init_nofail(dev);
548
549 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
550 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
551 }
552
553 fdt_add_v2m_gic_node(vms);
554}
555
556static void create_gic(VirtMachineState *vms, qemu_irq *pic)
557{
558
559 DeviceState *gicdev;
560 SysBusDevice *gicbusdev;
561 const char *gictype;
562 int type = vms->gic_version, i;
563 uint32_t nb_redist_regions = 0;
564
565 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
566
567 gicdev = qdev_create(NULL, gictype);
568 qdev_prop_set_uint32(gicdev, "revision", type);
569 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
570
571
572
573 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
574 if (!kvm_irqchip_in_kernel()) {
575 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
576 }
577
578 if (type == 3) {
579 uint32_t redist0_capacity =
580 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
581 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
582
583 nb_redist_regions = virt_gicv3_redist_region_count(vms);
584
585 qdev_prop_set_uint32(gicdev, "len-redist-region-count",
586 nb_redist_regions);
587 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
588
589 if (nb_redist_regions == 2) {
590 uint32_t redist1_capacity =
591 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
592
593 qdev_prop_set_uint32(gicdev, "redist-region-count[1]",
594 MIN(smp_cpus - redist0_count, redist1_capacity));
595 }
596 } else {
597 if (!kvm_irqchip_in_kernel()) {
598 qdev_prop_set_bit(gicdev, "has-virtualization-extensions",
599 vms->virt);
600 }
601 }
602 qdev_init_nofail(gicdev);
603 gicbusdev = SYS_BUS_DEVICE(gicdev);
604 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
605 if (type == 3) {
606 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
607 if (nb_redist_regions == 2) {
608 sysbus_mmio_map(gicbusdev, 2,
609 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
610 }
611 } else {
612 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
613 if (vms->virt) {
614 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
615 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
616 }
617 }
618
619
620
621
622
623 for (i = 0; i < smp_cpus; i++) {
624 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
625 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
626 int irq;
627
628
629
630 const int timer_irq[] = {
631 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
632 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
633 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
634 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
635 };
636
637 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
638 qdev_connect_gpio_out(cpudev, irq,
639 qdev_get_gpio_in(gicdev,
640 ppibase + timer_irq[irq]));
641 }
642
643 if (type == 3) {
644 qemu_irq irq = qdev_get_gpio_in(gicdev,
645 ppibase + ARCH_GIC_MAINT_IRQ);
646 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
647 0, irq);
648 } else if (vms->virt) {
649 qemu_irq irq = qdev_get_gpio_in(gicdev,
650 ppibase + ARCH_GIC_MAINT_IRQ);
651 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
652 }
653
654 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
655 qdev_get_gpio_in(gicdev, ppibase
656 + VIRTUAL_PMU_IRQ));
657
658 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
659 sysbus_connect_irq(gicbusdev, i + smp_cpus,
660 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
661 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
662 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
663 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
664 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
665 }
666
667 for (i = 0; i < NUM_IRQS; i++) {
668 pic[i] = qdev_get_gpio_in(gicdev, i);
669 }
670
671 fdt_add_gic_node(vms);
672
673 if (type == 3 && vms->its) {
674 create_its(vms, gicdev);
675 } else if (type == 2) {
676 create_v2m(vms, pic);
677 }
678}
679
680static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart,
681 MemoryRegion *mem, Chardev *chr)
682{
683 char *nodename;
684 hwaddr base = vms->memmap[uart].base;
685 hwaddr size = vms->memmap[uart].size;
686 int irq = vms->irqmap[uart];
687 const char compat[] = "arm,pl011\0arm,primecell";
688 const char clocknames[] = "uartclk\0apb_pclk";
689 DeviceState *dev = qdev_create(NULL, "pl011");
690 SysBusDevice *s = SYS_BUS_DEVICE(dev);
691
692 qdev_prop_set_chr(dev, "chardev", chr);
693 qdev_init_nofail(dev);
694 memory_region_add_subregion(mem, base,
695 sysbus_mmio_get_region(s, 0));
696 sysbus_connect_irq(s, 0, pic[irq]);
697
698 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
699 qemu_fdt_add_subnode(vms->fdt, nodename);
700
701 qemu_fdt_setprop(vms->fdt, nodename, "compatible",
702 compat, sizeof(compat));
703 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
704 2, base, 2, size);
705 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
706 GIC_FDT_IRQ_TYPE_SPI, irq,
707 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
708 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
709 vms->clock_phandle, vms->clock_phandle);
710 qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
711 clocknames, sizeof(clocknames));
712
713 if (uart == VIRT_UART) {
714 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
715 } else {
716
717 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
718 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
719
720 qemu_fdt_add_subnode(vms->fdt, "/secure-chosen");
721 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
722 nodename);
723 }
724
725 g_free(nodename);
726}
727
728static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
729{
730 char *nodename;
731 hwaddr base = vms->memmap[VIRT_RTC].base;
732 hwaddr size = vms->memmap[VIRT_RTC].size;
733 int irq = vms->irqmap[VIRT_RTC];
734 const char compat[] = "arm,pl031\0arm,primecell";
735
736 sysbus_create_simple("pl031", base, pic[irq]);
737
738 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
739 qemu_fdt_add_subnode(vms->fdt, nodename);
740 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
741 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
742 2, base, 2, size);
743 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
744 GIC_FDT_IRQ_TYPE_SPI, irq,
745 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
746 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
747 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
748 g_free(nodename);
749}
750
751static DeviceState *gpio_key_dev;
752static void virt_powerdown_req(Notifier *n, void *opaque)
753{
754
755 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
756}
757
758static Notifier virt_system_powerdown_notifier = {
759 .notify = virt_powerdown_req
760};
761
762static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
763{
764 char *nodename;
765 DeviceState *pl061_dev;
766 hwaddr base = vms->memmap[VIRT_GPIO].base;
767 hwaddr size = vms->memmap[VIRT_GPIO].size;
768 int irq = vms->irqmap[VIRT_GPIO];
769 const char compat[] = "arm,pl061\0arm,primecell";
770
771 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
772
773 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
774 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
775 qemu_fdt_add_subnode(vms->fdt, nodename);
776 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
777 2, base, 2, size);
778 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
779 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
780 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
781 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
782 GIC_FDT_IRQ_TYPE_SPI, irq,
783 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
784 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
785 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
786 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
787
788 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
789 qdev_get_gpio_in(pl061_dev, 3));
790 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
791 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
792 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
793 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
794
795 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
796 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
797 "label", "GPIO Key Poweroff");
798 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
799 KEY_POWER);
800 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
801 "gpios", phandle, 3, 0);
802
803
804 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
805
806 g_free(nodename);
807}
808
809static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
810{
811 int i;
812 hwaddr size = vms->memmap[VIRT_MMIO].size;
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
842 int irq = vms->irqmap[VIRT_MMIO] + i;
843 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
844
845 sysbus_create_simple("virtio-mmio", base, pic[irq]);
846 }
847
848
849
850
851
852
853
854
855 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
856 char *nodename;
857 int irq = vms->irqmap[VIRT_MMIO] + i;
858 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
859
860 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
861 qemu_fdt_add_subnode(vms->fdt, nodename);
862 qemu_fdt_setprop_string(vms->fdt, nodename,
863 "compatible", "virtio,mmio");
864 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
865 2, base, 2, size);
866 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
867 GIC_FDT_IRQ_TYPE_SPI, irq,
868 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
869 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
870 g_free(nodename);
871 }
872}
873
874static void create_one_flash(const char *name, hwaddr flashbase,
875 hwaddr flashsize, const char *file,
876 MemoryRegion *sysmem)
877{
878
879
880
881 DriveInfo *dinfo = drive_get_next(IF_PFLASH);
882 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
883 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
884 const uint64_t sectorlength = 256 * 1024;
885
886 if (dinfo) {
887 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
888 &error_abort);
889 }
890
891 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength);
892 qdev_prop_set_uint64(dev, "sector-length", sectorlength);
893 qdev_prop_set_uint8(dev, "width", 4);
894 qdev_prop_set_uint8(dev, "device-width", 2);
895 qdev_prop_set_bit(dev, "big-endian", false);
896 qdev_prop_set_uint16(dev, "id0", 0x89);
897 qdev_prop_set_uint16(dev, "id1", 0x18);
898 qdev_prop_set_uint16(dev, "id2", 0x00);
899 qdev_prop_set_uint16(dev, "id3", 0x00);
900 qdev_prop_set_string(dev, "name", name);
901 qdev_init_nofail(dev);
902
903 memory_region_add_subregion(sysmem, flashbase,
904 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
905
906 if (file) {
907 char *fn;
908 int image_size;
909
910 if (drive_get(IF_PFLASH, 0, 0)) {
911 error_report("The contents of the first flash device may be "
912 "specified with -bios or with -drive if=pflash... "
913 "but you cannot use both options at once");
914 exit(1);
915 }
916 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file);
917 if (!fn) {
918 error_report("Could not find ROM image '%s'", file);
919 exit(1);
920 }
921 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0));
922 g_free(fn);
923 if (image_size < 0) {
924 error_report("Could not load ROM image '%s'", file);
925 exit(1);
926 }
927 }
928}
929
930static void create_flash(const VirtMachineState *vms,
931 MemoryRegion *sysmem,
932 MemoryRegion *secure_sysmem)
933{
934
935
936
937
938
939
940
941
942 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
943 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
944 char *nodename;
945
946 create_one_flash("virt.flash0", flashbase, flashsize,
947 bios_name, secure_sysmem);
948 create_one_flash("virt.flash1", flashbase + flashsize, flashsize,
949 NULL, sysmem);
950
951 if (sysmem == secure_sysmem) {
952
953 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
954 qemu_fdt_add_subnode(vms->fdt, nodename);
955 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
956 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
957 2, flashbase, 2, flashsize,
958 2, flashbase + flashsize, 2, flashsize);
959 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
960 g_free(nodename);
961 } else {
962
963
964
965 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
966 qemu_fdt_add_subnode(vms->fdt, nodename);
967 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
968 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
969 2, flashbase, 2, flashsize);
970 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
971 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
972 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
973 g_free(nodename);
974
975 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
976 qemu_fdt_add_subnode(vms->fdt, nodename);
977 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
978 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
979 2, flashbase + flashsize, 2, flashsize);
980 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
981 g_free(nodename);
982 }
983}
984
985static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
986{
987 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
988 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
989 FWCfgState *fw_cfg;
990 char *nodename;
991
992 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
993 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
994
995 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
996 qemu_fdt_add_subnode(vms->fdt, nodename);
997 qemu_fdt_setprop_string(vms->fdt, nodename,
998 "compatible", "qemu,fw-cfg-mmio");
999 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1000 2, base, 2, size);
1001 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1002 g_free(nodename);
1003 return fw_cfg;
1004}
1005
1006static void create_pcie_irq_map(const VirtMachineState *vms,
1007 uint32_t gic_phandle,
1008 int first_irq, const char *nodename)
1009{
1010 int devfn, pin;
1011 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1012 uint32_t *irq_map = full_irq_map;
1013
1014 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1015 for (pin = 0; pin < 4; pin++) {
1016 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1017 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1018 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1019 int i;
1020
1021 uint32_t map[] = {
1022 devfn << 8, 0, 0,
1023 pin + 1,
1024 gic_phandle, 0, 0, irq_type, irq_nr, irq_level };
1025
1026
1027 for (i = 0; i < 10; i++) {
1028 irq_map[i] = cpu_to_be32(map[i]);
1029 }
1030 irq_map += 10;
1031 }
1032 }
1033
1034 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
1035 full_irq_map, sizeof(full_irq_map));
1036
1037 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
1038 0x1800, 0, 0,
1039 0x7 );
1040}
1041
1042static void create_smmu(const VirtMachineState *vms, qemu_irq *pic,
1043 PCIBus *bus)
1044{
1045 char *node;
1046 const char compat[] = "arm,smmu-v3";
1047 int irq = vms->irqmap[VIRT_SMMU];
1048 int i;
1049 hwaddr base = vms->memmap[VIRT_SMMU].base;
1050 hwaddr size = vms->memmap[VIRT_SMMU].size;
1051 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1052 DeviceState *dev;
1053
1054 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1055 return;
1056 }
1057
1058 dev = qdev_create(NULL, "arm-smmuv3");
1059
1060 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
1061 &error_abort);
1062 qdev_init_nofail(dev);
1063 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1064 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1065 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1066 }
1067
1068 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1069 qemu_fdt_add_subnode(vms->fdt, node);
1070 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1071 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
1072
1073 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
1074 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1075 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1076 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1077 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1078
1079 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
1080 sizeof(irq_names));
1081
1082 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
1083 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
1084 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
1085
1086 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1087
1088 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1089 g_free(node);
1090}
1091
1092static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
1093{
1094 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1095 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1096 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1097 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1098 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1099 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1100 hwaddr base_ecam, size_ecam;
1101 hwaddr base = base_mmio;
1102 int nr_pcie_buses;
1103 int irq = vms->irqmap[VIRT_PCIE];
1104 MemoryRegion *mmio_alias;
1105 MemoryRegion *mmio_reg;
1106 MemoryRegion *ecam_alias;
1107 MemoryRegion *ecam_reg;
1108 DeviceState *dev;
1109 char *nodename;
1110 int i, ecam_id;
1111 PCIHostState *pci;
1112
1113 dev = qdev_create(NULL, TYPE_GPEX_HOST);
1114 qdev_init_nofail(dev);
1115
1116 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1117 base_ecam = vms->memmap[ecam_id].base;
1118 size_ecam = vms->memmap[ecam_id].size;
1119 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1120
1121 ecam_alias = g_new0(MemoryRegion, 1);
1122 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1123 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1124 ecam_reg, 0, size_ecam);
1125 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1126
1127
1128
1129
1130
1131
1132 mmio_alias = g_new0(MemoryRegion, 1);
1133 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1134 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1135 mmio_reg, base_mmio, size_mmio);
1136 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1137
1138 if (vms->highmem) {
1139
1140 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1141
1142 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1143 mmio_reg, base_mmio_high, size_mmio_high);
1144 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1145 high_mmio_alias);
1146 }
1147
1148
1149 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1150
1151 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1152 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1153 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1154 }
1155
1156 pci = PCI_HOST_BRIDGE(dev);
1157 if (pci->bus) {
1158 for (i = 0; i < nb_nics; i++) {
1159 NICInfo *nd = &nd_table[i];
1160
1161 if (!nd->model) {
1162 nd->model = g_strdup("virtio");
1163 }
1164
1165 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1166 }
1167 }
1168
1169 nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1170 qemu_fdt_add_subnode(vms->fdt, nodename);
1171 qemu_fdt_setprop_string(vms->fdt, nodename,
1172 "compatible", "pci-host-ecam-generic");
1173 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
1174 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
1175 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
1176 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0);
1177 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
1178 nr_pcie_buses - 1);
1179 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1180
1181 if (vms->msi_phandle) {
1182 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
1183 vms->msi_phandle);
1184 }
1185
1186 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1187 2, base_ecam, 2, size_ecam);
1188
1189 if (vms->highmem) {
1190 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1191 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1192 2, base_pio, 2, size_pio,
1193 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1194 2, base_mmio, 2, size_mmio,
1195 1, FDT_PCI_RANGE_MMIO_64BIT,
1196 2, base_mmio_high,
1197 2, base_mmio_high, 2, size_mmio_high);
1198 } else {
1199 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1200 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1201 2, base_pio, 2, size_pio,
1202 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1203 2, base_mmio, 2, size_mmio);
1204 }
1205
1206 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
1207 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
1208
1209 if (vms->iommu) {
1210 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1211
1212 create_smmu(vms, pic, pci->bus);
1213
1214 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
1215 0x0, vms->iommu_phandle, 0x0, 0x10000);
1216 }
1217
1218 g_free(nodename);
1219}
1220
1221static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic)
1222{
1223 DeviceState *dev;
1224 SysBusDevice *s;
1225 int i;
1226 MemoryRegion *sysmem = get_system_memory();
1227
1228 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
1229 dev->id = TYPE_PLATFORM_BUS_DEVICE;
1230 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1231 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1232 qdev_init_nofail(dev);
1233 vms->platform_bus_dev = dev;
1234
1235 s = SYS_BUS_DEVICE(dev);
1236 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1237 int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1238 sysbus_connect_irq(s, i, pic[irqn]);
1239 }
1240
1241 memory_region_add_subregion(sysmem,
1242 vms->memmap[VIRT_PLATFORM_BUS].base,
1243 sysbus_mmio_get_region(s, 0));
1244}
1245
1246static void create_secure_ram(VirtMachineState *vms,
1247 MemoryRegion *secure_sysmem)
1248{
1249 MemoryRegion *secram = g_new(MemoryRegion, 1);
1250 char *nodename;
1251 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1252 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1253
1254 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1255 &error_fatal);
1256 memory_region_add_subregion(secure_sysmem, base, secram);
1257
1258 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1259 qemu_fdt_add_subnode(vms->fdt, nodename);
1260 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
1261 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
1262 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1263 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1264
1265 g_free(nodename);
1266}
1267
1268static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1269{
1270 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1271 bootinfo);
1272
1273 *fdt_size = board->fdt_size;
1274 return board->fdt;
1275}
1276
1277static void virt_build_smbios(VirtMachineState *vms)
1278{
1279 MachineClass *mc = MACHINE_GET_CLASS(vms);
1280 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1281 uint8_t *smbios_tables, *smbios_anchor;
1282 size_t smbios_tables_len, smbios_anchor_len;
1283 const char *product = "QEMU Virtual Machine";
1284
1285 if (kvm_enabled()) {
1286 product = "KVM Virtual Machine";
1287 }
1288
1289 smbios_set_defaults("QEMU", product,
1290 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1291 true, SMBIOS_ENTRY_POINT_30);
1292
1293 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len,
1294 &smbios_anchor, &smbios_anchor_len);
1295
1296 if (smbios_anchor) {
1297 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1298 smbios_tables, smbios_tables_len);
1299 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1300 smbios_anchor, smbios_anchor_len);
1301 }
1302}
1303
1304static
1305void virt_machine_done(Notifier *notifier, void *data)
1306{
1307 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1308 machine_done);
1309 ARMCPU *cpu = ARM_CPU(first_cpu);
1310 struct arm_boot_info *info = &vms->bootinfo;
1311 AddressSpace *as = arm_boot_address_space(cpu, info);
1312
1313
1314
1315
1316
1317
1318
1319
1320 if (info->dtb_filename == NULL) {
1321 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc",
1322 vms->memmap[VIRT_PLATFORM_BUS].base,
1323 vms->memmap[VIRT_PLATFORM_BUS].size,
1324 vms->irqmap[VIRT_PLATFORM_BUS]);
1325 }
1326 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
1327 exit(1);
1328 }
1329
1330 virt_acpi_setup(vms);
1331 virt_build_smbios(vms);
1332}
1333
1334static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1335{
1336 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1337 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1338
1339 if (!vmc->disallow_affinity_adjustment) {
1340
1341
1342
1343
1344
1345
1346
1347
1348 if (vms->gic_version == 3) {
1349 clustersz = GICV3_TARGETLIST_BITS;
1350 } else {
1351 clustersz = GIC_TARGETLIST_BITS;
1352 }
1353 }
1354 return arm_cpu_mp_affinity(idx, clustersz);
1355}
1356
1357static void virt_set_memmap(VirtMachineState *vms)
1358{
1359 MachineState *ms = MACHINE(vms);
1360 hwaddr base, device_memory_base, device_memory_size;
1361 int i;
1362
1363 vms->memmap = extended_memmap;
1364
1365 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1366 vms->memmap[i] = base_memmap[i];
1367 }
1368
1369 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1370 error_report("unsupported number of memory slots: %"PRIu64,
1371 ms->ram_slots);
1372 exit(EXIT_FAILURE);
1373 }
1374
1375
1376
1377
1378
1379
1380
1381
1382 device_memory_base =
1383 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1384 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1385
1386
1387 base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1388 if (base < device_memory_base) {
1389 error_report("maxmem/slots too huge");
1390 exit(EXIT_FAILURE);
1391 }
1392 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1393 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1394 }
1395
1396 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1397 hwaddr size = extended_memmap[i].size;
1398
1399 base = ROUND_UP(base, size);
1400 vms->memmap[i].base = base;
1401 vms->memmap[i].size = size;
1402 base += size;
1403 }
1404 vms->highest_gpa = base - 1;
1405 if (device_memory_size > 0) {
1406 ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1407 ms->device_memory->base = device_memory_base;
1408 memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1409 "device-memory", device_memory_size);
1410 }
1411}
1412
1413static void machvirt_init(MachineState *machine)
1414{
1415 VirtMachineState *vms = VIRT_MACHINE(machine);
1416 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1417 MachineClass *mc = MACHINE_GET_CLASS(machine);
1418 const CPUArchIdList *possible_cpus;
1419 qemu_irq pic[NUM_IRQS];
1420 MemoryRegion *sysmem = get_system_memory();
1421 MemoryRegion *secure_sysmem = NULL;
1422 int n, virt_max_cpus;
1423 MemoryRegion *ram = g_new(MemoryRegion, 1);
1424 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
1425 bool aarch64 = true;
1426
1427
1428
1429
1430
1431 if (!vms->memmap) {
1432 virt_set_memmap(vms);
1433 }
1434
1435
1436
1437
1438 if (vms->gic_version <= 0) {
1439
1440 if (!kvm_enabled()) {
1441 if (vms->gic_version == 0) {
1442 error_report("gic-version=host requires KVM");
1443 exit(1);
1444 } else {
1445
1446 vms->gic_version = 3;
1447 }
1448 } else {
1449 vms->gic_version = kvm_arm_vgic_probe();
1450 if (!vms->gic_version) {
1451 error_report(
1452 "Unable to determine GIC version supported by host");
1453 exit(1);
1454 }
1455 }
1456 }
1457
1458 if (!cpu_type_valid(machine->cpu_type)) {
1459 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1460 exit(1);
1461 }
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473 if (vms->secure && firmware_loaded) {
1474 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1475 } else if (vms->virt) {
1476 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1477 } else {
1478 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1479 }
1480
1481
1482
1483
1484 if (vms->gic_version == 3) {
1485 virt_max_cpus =
1486 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1487 virt_max_cpus +=
1488 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1489 } else {
1490 virt_max_cpus = GIC_NCPU;
1491 }
1492
1493 if (max_cpus > virt_max_cpus) {
1494 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1495 "supported by machine 'mach-virt' (%d)",
1496 max_cpus, virt_max_cpus);
1497 exit(1);
1498 }
1499
1500 vms->smp_cpus = smp_cpus;
1501
1502 if (vms->virt && kvm_enabled()) {
1503 error_report("mach-virt: KVM does not support providing "
1504 "Virtualization extensions to the guest CPU");
1505 exit(1);
1506 }
1507
1508 if (vms->secure) {
1509 if (kvm_enabled()) {
1510 error_report("mach-virt: KVM does not support Security extensions");
1511 exit(1);
1512 }
1513
1514
1515
1516
1517
1518
1519 secure_sysmem = g_new(MemoryRegion, 1);
1520 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1521 UINT64_MAX);
1522 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1523 }
1524
1525 create_fdt(vms);
1526
1527 possible_cpus = mc->possible_cpu_arch_ids(machine);
1528 for (n = 0; n < possible_cpus->len; n++) {
1529 Object *cpuobj;
1530 CPUState *cs;
1531
1532 if (n >= smp_cpus) {
1533 break;
1534 }
1535
1536 cpuobj = object_new(possible_cpus->cpus[n].type);
1537 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
1538 "mp-affinity", NULL);
1539
1540 cs = CPU(cpuobj);
1541 cs->cpu_index = n;
1542
1543 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1544 &error_fatal);
1545
1546 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1547
1548 if (!vms->secure) {
1549 object_property_set_bool(cpuobj, false, "has_el3", NULL);
1550 }
1551
1552 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) {
1553 object_property_set_bool(cpuobj, false, "has_el2", NULL);
1554 }
1555
1556 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1557 object_property_set_int(cpuobj, vms->psci_conduit,
1558 "psci-conduit", NULL);
1559
1560
1561 if (n > 0) {
1562 object_property_set_bool(cpuobj, true,
1563 "start-powered-off", NULL);
1564 }
1565 }
1566
1567 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
1568 object_property_set_bool(cpuobj, false, "pmu", NULL);
1569 }
1570
1571 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
1572 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base,
1573 "reset-cbar", &error_abort);
1574 }
1575
1576 object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
1577 &error_abort);
1578 if (vms->secure) {
1579 object_property_set_link(cpuobj, OBJECT(secure_sysmem),
1580 "secure-memory", &error_abort);
1581 }
1582
1583 object_property_set_bool(cpuobj, true, "realized", &error_fatal);
1584 object_unref(cpuobj);
1585 }
1586 fdt_add_timer_nodes(vms);
1587 fdt_add_cpu_nodes(vms);
1588
1589 if (!kvm_enabled()) {
1590 ARMCPU *cpu = ARM_CPU(first_cpu);
1591 bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
1592
1593 if (aarch64 && vms->highmem) {
1594 int requested_pa_size, pamax = arm_pamax(cpu);
1595
1596 requested_pa_size = 64 - clz64(vms->highest_gpa);
1597 if (pamax < requested_pa_size) {
1598 error_report("VCPU supports less PA bits (%d) than requested "
1599 "by the memory map (%d)", pamax, requested_pa_size);
1600 exit(1);
1601 }
1602 }
1603 }
1604
1605 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
1606 machine->ram_size);
1607 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
1608 if (machine->device_memory) {
1609 memory_region_add_subregion(sysmem, machine->device_memory->base,
1610 &machine->device_memory->mr);
1611 }
1612
1613 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);
1614
1615 create_gic(vms, pic);
1616
1617 fdt_add_pmu_nodes(vms);
1618
1619 create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0));
1620
1621 if (vms->secure) {
1622 create_secure_ram(vms, secure_sysmem);
1623 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
1624 }
1625
1626 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
1627
1628 create_rtc(vms, pic);
1629
1630 create_pcie(vms, pic);
1631
1632 create_gpio(vms, pic);
1633
1634
1635
1636
1637
1638 create_virtio_devices(vms, pic);
1639
1640 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
1641 rom_set_fw(vms->fw_cfg);
1642
1643 create_platform_bus(vms, pic);
1644
1645 vms->bootinfo.ram_size = machine->ram_size;
1646 vms->bootinfo.kernel_filename = machine->kernel_filename;
1647 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline;
1648 vms->bootinfo.initrd_filename = machine->initrd_filename;
1649 vms->bootinfo.nb_cpus = smp_cpus;
1650 vms->bootinfo.board_id = -1;
1651 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
1652 vms->bootinfo.get_dtb = machvirt_dtb;
1653 vms->bootinfo.skip_dtb_autoload = true;
1654 vms->bootinfo.firmware_loaded = firmware_loaded;
1655 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo);
1656
1657 vms->machine_done.notify = virt_machine_done;
1658 qemu_add_machine_init_done_notifier(&vms->machine_done);
1659}
1660
1661static bool virt_get_secure(Object *obj, Error **errp)
1662{
1663 VirtMachineState *vms = VIRT_MACHINE(obj);
1664
1665 return vms->secure;
1666}
1667
1668static void virt_set_secure(Object *obj, bool value, Error **errp)
1669{
1670 VirtMachineState *vms = VIRT_MACHINE(obj);
1671
1672 vms->secure = value;
1673}
1674
1675static bool virt_get_virt(Object *obj, Error **errp)
1676{
1677 VirtMachineState *vms = VIRT_MACHINE(obj);
1678
1679 return vms->virt;
1680}
1681
1682static void virt_set_virt(Object *obj, bool value, Error **errp)
1683{
1684 VirtMachineState *vms = VIRT_MACHINE(obj);
1685
1686 vms->virt = value;
1687}
1688
1689static bool virt_get_highmem(Object *obj, Error **errp)
1690{
1691 VirtMachineState *vms = VIRT_MACHINE(obj);
1692
1693 return vms->highmem;
1694}
1695
1696static void virt_set_highmem(Object *obj, bool value, Error **errp)
1697{
1698 VirtMachineState *vms = VIRT_MACHINE(obj);
1699
1700 vms->highmem = value;
1701}
1702
1703static bool virt_get_its(Object *obj, Error **errp)
1704{
1705 VirtMachineState *vms = VIRT_MACHINE(obj);
1706
1707 return vms->its;
1708}
1709
1710static void virt_set_its(Object *obj, bool value, Error **errp)
1711{
1712 VirtMachineState *vms = VIRT_MACHINE(obj);
1713
1714 vms->its = value;
1715}
1716
1717static char *virt_get_gic_version(Object *obj, Error **errp)
1718{
1719 VirtMachineState *vms = VIRT_MACHINE(obj);
1720 const char *val = vms->gic_version == 3 ? "3" : "2";
1721
1722 return g_strdup(val);
1723}
1724
1725static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
1726{
1727 VirtMachineState *vms = VIRT_MACHINE(obj);
1728
1729 if (!strcmp(value, "3")) {
1730 vms->gic_version = 3;
1731 } else if (!strcmp(value, "2")) {
1732 vms->gic_version = 2;
1733 } else if (!strcmp(value, "host")) {
1734 vms->gic_version = 0;
1735 } else if (!strcmp(value, "max")) {
1736 vms->gic_version = -1;
1737 } else {
1738 error_setg(errp, "Invalid gic-version value");
1739 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
1740 }
1741}
1742
1743static char *virt_get_iommu(Object *obj, Error **errp)
1744{
1745 VirtMachineState *vms = VIRT_MACHINE(obj);
1746
1747 switch (vms->iommu) {
1748 case VIRT_IOMMU_NONE:
1749 return g_strdup("none");
1750 case VIRT_IOMMU_SMMUV3:
1751 return g_strdup("smmuv3");
1752 default:
1753 g_assert_not_reached();
1754 }
1755}
1756
1757static void virt_set_iommu(Object *obj, const char *value, Error **errp)
1758{
1759 VirtMachineState *vms = VIRT_MACHINE(obj);
1760
1761 if (!strcmp(value, "smmuv3")) {
1762 vms->iommu = VIRT_IOMMU_SMMUV3;
1763 } else if (!strcmp(value, "none")) {
1764 vms->iommu = VIRT_IOMMU_NONE;
1765 } else {
1766 error_setg(errp, "Invalid iommu value");
1767 error_append_hint(errp, "Valid values are none, smmuv3.\n");
1768 }
1769}
1770
1771static CpuInstanceProperties
1772virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
1773{
1774 MachineClass *mc = MACHINE_GET_CLASS(ms);
1775 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1776
1777 assert(cpu_index < possible_cpus->len);
1778 return possible_cpus->cpus[cpu_index].props;
1779}
1780
1781static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
1782{
1783 return idx % nb_numa_nodes;
1784}
1785
1786static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
1787{
1788 int n;
1789 VirtMachineState *vms = VIRT_MACHINE(ms);
1790
1791 if (ms->possible_cpus) {
1792 assert(ms->possible_cpus->len == max_cpus);
1793 return ms->possible_cpus;
1794 }
1795
1796 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1797 sizeof(CPUArchId) * max_cpus);
1798 ms->possible_cpus->len = max_cpus;
1799 for (n = 0; n < ms->possible_cpus->len; n++) {
1800 ms->possible_cpus->cpus[n].type = ms->cpu_type;
1801 ms->possible_cpus->cpus[n].arch_id =
1802 virt_cpu_mp_affinity(vms, n);
1803 ms->possible_cpus->cpus[n].props.has_thread_id = true;
1804 ms->possible_cpus->cpus[n].props.thread_id = n;
1805 }
1806 return ms->possible_cpus;
1807}
1808
1809static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1810 DeviceState *dev, Error **errp)
1811{
1812 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
1813
1814 if (vms->platform_bus_dev) {
1815 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1816 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
1817 SYS_BUS_DEVICE(dev));
1818 }
1819 }
1820}
1821
1822static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1823 DeviceState *dev)
1824{
1825 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1826 return HOTPLUG_HANDLER(machine);
1827 }
1828
1829 return NULL;
1830}
1831
1832
1833
1834
1835
1836static int virt_kvm_type(MachineState *ms, const char *type_str)
1837{
1838 VirtMachineState *vms = VIRT_MACHINE(ms);
1839 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);
1840 int requested_pa_size;
1841
1842
1843 virt_set_memmap(vms);
1844
1845 requested_pa_size = 64 - clz64(vms->highest_gpa);
1846
1847 if (requested_pa_size > max_vm_pa_size) {
1848 error_report("-m and ,maxmem option values "
1849 "require an IPA range (%d bits) larger than "
1850 "the one supported by the host (%d bits)",
1851 requested_pa_size, max_vm_pa_size);
1852 exit(1);
1853 }
1854
1855
1856
1857
1858
1859 return requested_pa_size > 40 ? requested_pa_size : 0;
1860}
1861
1862static void virt_machine_class_init(ObjectClass *oc, void *data)
1863{
1864 MachineClass *mc = MACHINE_CLASS(oc);
1865 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1866
1867 mc->init = machvirt_init;
1868
1869
1870
1871
1872 mc->max_cpus = 512;
1873 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
1874 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
1875 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1876 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
1877 mc->block_default_type = IF_VIRTIO;
1878 mc->no_cdrom = 1;
1879 mc->pci_allow_0_address = true;
1880
1881 mc->minimum_page_bits = 12;
1882 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
1883 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1884 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
1885 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
1886 mc->kvm_type = virt_kvm_type;
1887 assert(!mc->get_hotplug_handler);
1888 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1889 hc->plug = virt_machine_device_plug_cb;
1890}
1891
1892static void virt_instance_init(Object *obj)
1893{
1894 VirtMachineState *vms = VIRT_MACHINE(obj);
1895 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1896
1897
1898
1899
1900
1901 vms->secure = false;
1902 object_property_add_bool(obj, "secure", virt_get_secure,
1903 virt_set_secure, NULL);
1904 object_property_set_description(obj, "secure",
1905 "Set on/off to enable/disable the ARM "
1906 "Security Extensions (TrustZone)",
1907 NULL);
1908
1909
1910 vms->virt = false;
1911 object_property_add_bool(obj, "virtualization", virt_get_virt,
1912 virt_set_virt, NULL);
1913 object_property_set_description(obj, "virtualization",
1914 "Set on/off to enable/disable emulating a "
1915 "guest CPU which implements the ARM "
1916 "Virtualization Extensions",
1917 NULL);
1918
1919
1920 vms->highmem = true;
1921 object_property_add_bool(obj, "highmem", virt_get_highmem,
1922 virt_set_highmem, NULL);
1923 object_property_set_description(obj, "highmem",
1924 "Set on/off to enable/disable using "
1925 "physical address space above 32 bits",
1926 NULL);
1927
1928 vms->gic_version = 2;
1929 object_property_add_str(obj, "gic-version", virt_get_gic_version,
1930 virt_set_gic_version, NULL);
1931 object_property_set_description(obj, "gic-version",
1932 "Set GIC version. "
1933 "Valid values are 2, 3 and host", NULL);
1934
1935 vms->highmem_ecam = !vmc->no_highmem_ecam;
1936
1937 if (vmc->no_its) {
1938 vms->its = false;
1939 } else {
1940
1941 vms->its = true;
1942 object_property_add_bool(obj, "its", virt_get_its,
1943 virt_set_its, NULL);
1944 object_property_set_description(obj, "its",
1945 "Set on/off to enable/disable "
1946 "ITS instantiation",
1947 NULL);
1948 }
1949
1950
1951 vms->iommu = VIRT_IOMMU_NONE;
1952 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL);
1953 object_property_set_description(obj, "iommu",
1954 "Set the IOMMU type. "
1955 "Valid values are none and smmuv3",
1956 NULL);
1957
1958 vms->irqmap = a15irqmap;
1959}
1960
1961static const TypeInfo virt_machine_info = {
1962 .name = TYPE_VIRT_MACHINE,
1963 .parent = TYPE_MACHINE,
1964 .abstract = true,
1965 .instance_size = sizeof(VirtMachineState),
1966 .class_size = sizeof(VirtMachineClass),
1967 .class_init = virt_machine_class_init,
1968 .instance_init = virt_instance_init,
1969 .interfaces = (InterfaceInfo[]) {
1970 { TYPE_HOTPLUG_HANDLER },
1971 { }
1972 },
1973};
1974
1975static void machvirt_machine_init(void)
1976{
1977 type_register_static(&virt_machine_info);
1978}
1979type_init(machvirt_machine_init);
1980
1981static void virt_machine_4_0_options(MachineClass *mc)
1982{
1983}
1984DEFINE_VIRT_MACHINE_AS_LATEST(4, 0)
1985
1986static void virt_machine_3_1_options(MachineClass *mc)
1987{
1988 virt_machine_4_0_options(mc);
1989 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
1990}
1991DEFINE_VIRT_MACHINE(3, 1)
1992
1993static void virt_machine_3_0_options(MachineClass *mc)
1994{
1995 virt_machine_3_1_options(mc);
1996 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
1997}
1998DEFINE_VIRT_MACHINE(3, 0)
1999
2000static void virt_machine_2_12_options(MachineClass *mc)
2001{
2002 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2003
2004 virt_machine_3_0_options(mc);
2005 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
2006 vmc->no_highmem_ecam = true;
2007 mc->max_cpus = 255;
2008}
2009DEFINE_VIRT_MACHINE(2, 12)
2010
2011static void virt_machine_2_11_options(MachineClass *mc)
2012{
2013 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2014
2015 virt_machine_2_12_options(mc);
2016 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
2017 vmc->smbios_old_sys_ver = true;
2018}
2019DEFINE_VIRT_MACHINE(2, 11)
2020
2021static void virt_machine_2_10_options(MachineClass *mc)
2022{
2023 virt_machine_2_11_options(mc);
2024 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
2025
2026 mc->ignore_memory_transaction_failures = true;
2027}
2028DEFINE_VIRT_MACHINE(2, 10)
2029
2030static void virt_machine_2_9_options(MachineClass *mc)
2031{
2032 virt_machine_2_10_options(mc);
2033 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
2034}
2035DEFINE_VIRT_MACHINE(2, 9)
2036
2037static void virt_machine_2_8_options(MachineClass *mc)
2038{
2039 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2040
2041 virt_machine_2_9_options(mc);
2042 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
2043
2044
2045
2046 vmc->claim_edge_triggered_timers = true;
2047}
2048DEFINE_VIRT_MACHINE(2, 8)
2049
2050static void virt_machine_2_7_options(MachineClass *mc)
2051{
2052 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2053
2054 virt_machine_2_8_options(mc);
2055 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
2056
2057 vmc->no_its = true;
2058
2059 mc->minimum_page_bits = 0;
2060}
2061DEFINE_VIRT_MACHINE(2, 7)
2062
2063static void virt_machine_2_6_options(MachineClass *mc)
2064{
2065 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2066
2067 virt_machine_2_7_options(mc);
2068 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
2069 vmc->disallow_affinity_adjustment = true;
2070
2071 vmc->no_pmu = true;
2072}
2073DEFINE_VIRT_MACHINE(2, 6)
2074