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23#include "qemu/osdep.h"
24#include "qapi/error.h"
25#include "qapi/qmp/qnum.h"
26#include "acpi-build.h"
27#include "qemu-common.h"
28#include "qemu/bitmap.h"
29#include "qemu/error-report.h"
30#include "hw/pci/pci.h"
31#include "qom/cpu.h"
32#include "target/i386/cpu.h"
33#include "hw/misc/pvpanic.h"
34#include "hw/timer/hpet.h"
35#include "hw/acpi/acpi-defs.h"
36#include "hw/acpi/acpi.h"
37#include "hw/acpi/cpu.h"
38#include "hw/nvram/fw_cfg.h"
39#include "hw/acpi/bios-linker-loader.h"
40#include "hw/loader.h"
41#include "hw/isa/isa.h"
42#include "hw/block/fdc.h"
43#include "hw/acpi/memory_hotplug.h"
44#include "sysemu/tpm.h"
45#include "hw/acpi/tpm.h"
46#include "hw/acpi/vmgenid.h"
47#include "sysemu/tpm_backend.h"
48#include "hw/timer/mc146818rtc_regs.h"
49#include "hw/mem/memory-device.h"
50#include "sysemu/numa.h"
51
52
53#include "hw/acpi/piix4.h"
54#include "hw/acpi/pcihp.h"
55#include "hw/i386/ich9.h"
56#include "hw/pci/pci_bus.h"
57#include "hw/pci-host/q35.h"
58#include "hw/i386/x86-iommu.h"
59
60#include "hw/acpi/aml-build.h"
61
62#include "qom/qom-qobject.h"
63#include "hw/i386/amd_iommu.h"
64#include "hw/i386/intel_iommu.h"
65
66#include "hw/acpi/ipmi.h"
67
68
69
70
71
72
73#define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
74#define ACPI_BUILD_ALIGN_SIZE 0x1000
75
76#define ACPI_BUILD_TABLE_SIZE 0x20000
77
78
79#ifdef DEBUG_ACPI_BUILD
80#define ACPI_BUILD_DPRINTF(fmt, ...) \
81 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
82#else
83#define ACPI_BUILD_DPRINTF(fmt, ...)
84#endif
85
86
87#define ACPI_BUILD_IOAPIC_ID 0x0
88
89typedef struct AcpiMcfgInfo {
90 uint64_t mcfg_base;
91 uint32_t mcfg_size;
92} AcpiMcfgInfo;
93
94typedef struct AcpiPmInfo {
95 bool s3_disabled;
96 bool s4_disabled;
97 bool pcihp_bridge_en;
98 uint8_t s4_val;
99 AcpiFadtData fadt;
100 uint16_t cpu_hp_io_base;
101 uint16_t pcihp_io_base;
102 uint16_t pcihp_io_len;
103} AcpiPmInfo;
104
105typedef struct AcpiMiscInfo {
106 bool is_piix4;
107 bool has_hpet;
108 TPMVersion tpm_version;
109 const unsigned char *dsdt_code;
110 unsigned dsdt_size;
111 uint16_t pvpanic_port;
112 uint16_t applesmc_io_base;
113} AcpiMiscInfo;
114
115typedef struct AcpiBuildPciBusHotplugState {
116 GArray *device_table;
117 GArray *notify_table;
118 struct AcpiBuildPciBusHotplugState *parent;
119 bool pcihp_bridge_en;
120} AcpiBuildPciBusHotplugState;
121
122typedef struct FwCfgTPMConfig {
123 uint32_t tpmppi_address;
124 uint8_t tpm_version;
125 uint8_t tpmppi_version;
126} QEMU_PACKED FwCfgTPMConfig;
127
128static void init_common_fadt_data(Object *o, AcpiFadtData *data)
129{
130 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
131 AmlAddressSpace as = AML_AS_SYSTEM_IO;
132 AcpiFadtData fadt = {
133 .rev = 3,
134 .flags =
135 (1 << ACPI_FADT_F_WBINVD) |
136 (1 << ACPI_FADT_F_PROC_C1) |
137 (1 << ACPI_FADT_F_SLP_BUTTON) |
138 (1 << ACPI_FADT_F_RTC_S4) |
139 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
140
141
142
143
144 ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
145 .int_model = 1 ,
146 .rtc_century = RTC_CENTURY,
147 .plvl2_lat = 0xfff ,
148 .plvl3_lat = 0xfff ,
149 .smi_cmd = ACPI_PORT_SMI_CMD,
150 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
151 .acpi_enable_cmd =
152 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
153 .acpi_disable_cmd =
154 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
155 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
156 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
157 .address = io + 0x04 },
158 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
159 .gpe0_blk = { .space_id = as, .bit_width =
160 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
161 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
162 },
163 };
164 *data = fadt;
165}
166
167static void acpi_get_pm_info(AcpiPmInfo *pm)
168{
169 Object *piix = piix4_pm_find();
170 Object *lpc = ich9_lpc_find();
171 Object *obj = piix ? piix : lpc;
172 QObject *o;
173 pm->cpu_hp_io_base = 0;
174 pm->pcihp_io_base = 0;
175 pm->pcihp_io_len = 0;
176
177 init_common_fadt_data(obj, &pm->fadt);
178 if (piix) {
179
180 pm->fadt.rev = 1;
181 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
182 pm->pcihp_io_base =
183 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
184 pm->pcihp_io_len =
185 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
186 }
187 if (lpc) {
188 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
189 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
190 pm->fadt.reset_reg = r;
191 pm->fadt.reset_val = 0xf;
192 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
193 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
194 }
195 assert(obj);
196
197
198
199 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
200
201
202 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
203 if (o) {
204 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
205 } else {
206 pm->s3_disabled = false;
207 }
208 qobject_unref(o);
209 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
210 if (o) {
211 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
212 } else {
213 pm->s4_disabled = false;
214 }
215 qobject_unref(o);
216 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
217 if (o) {
218 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
219 } else {
220 pm->s4_val = false;
221 }
222 qobject_unref(o);
223
224 pm->pcihp_bridge_en =
225 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
226 NULL);
227}
228
229static void acpi_get_misc_info(AcpiMiscInfo *info)
230{
231 Object *piix = piix4_pm_find();
232 Object *lpc = ich9_lpc_find();
233 assert(!!piix != !!lpc);
234
235 if (piix) {
236 info->is_piix4 = true;
237 }
238 if (lpc) {
239 info->is_piix4 = false;
240 }
241
242 info->has_hpet = hpet_find();
243 info->tpm_version = tpm_get_version(tpm_find());
244 info->pvpanic_port = pvpanic_port();
245 info->applesmc_io_base = applesmc_port();
246}
247
248
249
250
251
252static Object *acpi_get_i386_pci_host(void)
253{
254 PCIHostState *host;
255
256 host = OBJECT_CHECK(PCIHostState,
257 object_resolve_path("/machine/i440fx", NULL),
258 TYPE_PCI_HOST_BRIDGE);
259 if (!host) {
260 host = OBJECT_CHECK(PCIHostState,
261 object_resolve_path("/machine/q35", NULL),
262 TYPE_PCI_HOST_BRIDGE);
263 }
264
265 return OBJECT(host);
266}
267
268static void acpi_get_pci_holes(Range *hole, Range *hole64)
269{
270 Object *pci_host;
271
272 pci_host = acpi_get_i386_pci_host();
273 g_assert(pci_host);
274
275 range_set_bounds1(hole,
276 object_property_get_uint(pci_host,
277 PCI_HOST_PROP_PCI_HOLE_START,
278 NULL),
279 object_property_get_uint(pci_host,
280 PCI_HOST_PROP_PCI_HOLE_END,
281 NULL));
282 range_set_bounds1(hole64,
283 object_property_get_uint(pci_host,
284 PCI_HOST_PROP_PCI_HOLE64_START,
285 NULL),
286 object_property_get_uint(pci_host,
287 PCI_HOST_PROP_PCI_HOLE64_END,
288 NULL));
289}
290
291static void acpi_align_size(GArray *blob, unsigned align)
292{
293
294
295
296 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
297}
298
299
300static void
301build_facs(GArray *table_data)
302{
303 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
304 memcpy(&facs->signature, "FACS", 4);
305 facs->length = cpu_to_le32(sizeof(*facs));
306}
307
308void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
309 const CPUArchIdList *apic_ids, GArray *entry)
310{
311 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
312
313
314
315
316
317
318
319 if (apic_id < 255) {
320 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
321
322 apic->type = ACPI_APIC_PROCESSOR;
323 apic->length = sizeof(*apic);
324 apic->processor_id = uid;
325 apic->local_apic_id = apic_id;
326 if (apic_ids->cpus[uid].cpu != NULL) {
327 apic->flags = cpu_to_le32(1);
328 } else {
329 apic->flags = cpu_to_le32(0);
330 }
331 } else {
332 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
333
334 apic->type = ACPI_APIC_LOCAL_X2APIC;
335 apic->length = sizeof(*apic);
336 apic->uid = cpu_to_le32(uid);
337 apic->x2apic_id = cpu_to_le32(apic_id);
338 if (apic_ids->cpus[uid].cpu != NULL) {
339 apic->flags = cpu_to_le32(1);
340 } else {
341 apic->flags = cpu_to_le32(0);
342 }
343 }
344}
345
346static void
347build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
348{
349 MachineClass *mc = MACHINE_GET_CLASS(pcms);
350 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
351 int madt_start = table_data->len;
352 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
353 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
354 bool x2apic_mode = false;
355
356 AcpiMultipleApicTable *madt;
357 AcpiMadtIoApic *io_apic;
358 AcpiMadtIntsrcovr *intsrcovr;
359 int i;
360
361 madt = acpi_data_push(table_data, sizeof *madt);
362 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
363 madt->flags = cpu_to_le32(1);
364
365 for (i = 0; i < apic_ids->len; i++) {
366 adevc->madt_cpu(adev, i, apic_ids, table_data);
367 if (apic_ids->cpus[i].arch_id > 254) {
368 x2apic_mode = true;
369 }
370 }
371
372 io_apic = acpi_data_push(table_data, sizeof *io_apic);
373 io_apic->type = ACPI_APIC_IO;
374 io_apic->length = sizeof(*io_apic);
375 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
376 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
377 io_apic->interrupt = cpu_to_le32(0);
378
379 if (pcms->apic_xrupt_override) {
380 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
381 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
382 intsrcovr->length = sizeof(*intsrcovr);
383 intsrcovr->source = 0;
384 intsrcovr->gsi = cpu_to_le32(2);
385 intsrcovr->flags = cpu_to_le16(0);
386 }
387 for (i = 1; i < 16; i++) {
388#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
389 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
390
391 continue;
392 }
393 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
394 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
395 intsrcovr->length = sizeof(*intsrcovr);
396 intsrcovr->source = i;
397 intsrcovr->gsi = cpu_to_le32(i);
398 intsrcovr->flags = cpu_to_le16(0xd);
399 }
400
401 if (x2apic_mode) {
402 AcpiMadtLocalX2ApicNmi *local_nmi;
403
404 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
405 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
406 local_nmi->length = sizeof(*local_nmi);
407 local_nmi->uid = 0xFFFFFFFF;
408 local_nmi->flags = cpu_to_le16(0);
409 local_nmi->lint = 1;
410 } else {
411 AcpiMadtLocalNmi *local_nmi;
412
413 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
414 local_nmi->type = ACPI_APIC_LOCAL_NMI;
415 local_nmi->length = sizeof(*local_nmi);
416 local_nmi->processor_id = 0xff;
417 local_nmi->flags = cpu_to_le16(0);
418 local_nmi->lint = 1;
419 }
420
421 build_header(linker, table_data,
422 (void *)(table_data->data + madt_start), "APIC",
423 table_data->len - madt_start, 1, NULL, NULL);
424}
425
426static void build_append_pcihp_notify_entry(Aml *method, int slot)
427{
428 Aml *if_ctx;
429 int32_t devfn = PCI_DEVFN(slot, 0);
430
431 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
432 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
433 aml_append(method, if_ctx);
434}
435
436static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
437 bool pcihp_bridge_en)
438{
439 Aml *dev, *notify_method = NULL, *method;
440 QObject *bsel;
441 PCIBus *sec;
442 int i;
443
444 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
445 if (bsel) {
446 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
447
448 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
449 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
450 }
451
452 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
453 DeviceClass *dc;
454 PCIDeviceClass *pc;
455 PCIDevice *pdev = bus->devices[i];
456 int slot = PCI_SLOT(i);
457 bool hotplug_enabled_dev;
458 bool bridge_in_acpi;
459
460 if (!pdev) {
461 if (bsel) {
462 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
463 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
464 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
465 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
466 aml_append(method,
467 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
468 );
469 aml_append(dev, method);
470 aml_append(parent_scope, dev);
471
472 build_append_pcihp_notify_entry(notify_method, slot);
473 }
474 continue;
475 }
476
477 pc = PCI_DEVICE_GET_CLASS(pdev);
478 dc = DEVICE_GET_CLASS(pdev);
479
480
481
482
483
484
485 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
486 !DEVICE(pdev)->hotplugged;
487
488 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
489
490 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
491 continue;
492 }
493
494
495 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
496 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
497
498 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
499
500 int s3d;
501
502 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
503 s3d = 3;
504 } else {
505 s3d = 0;
506 }
507
508 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
509 aml_append(method, aml_return(aml_int(0)));
510 aml_append(dev, method);
511
512 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
513 aml_append(method, aml_return(aml_int(0)));
514 aml_append(dev, method);
515
516 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
517 aml_append(method, aml_return(aml_int(s3d)));
518 aml_append(dev, method);
519 } else if (hotplug_enabled_dev) {
520
521 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
522
523 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
524 aml_append(method,
525 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
526 );
527 aml_append(dev, method);
528
529 if (bsel) {
530 build_append_pcihp_notify_entry(notify_method, slot);
531 }
532 } else if (bridge_in_acpi) {
533
534
535
536
537 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
538
539 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
540 }
541
542 aml_append(parent_scope, dev);
543 }
544
545 if (bsel) {
546 aml_append(parent_scope, notify_method);
547 }
548
549
550
551
552 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
553
554
555 if (bsel) {
556 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
557
558 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
559 aml_append(method,
560 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) )
561 );
562 aml_append(method,
563 aml_call2("DVNT", aml_name("PCID"), aml_int(3))
564 );
565 }
566
567
568 if (pcihp_bridge_en) {
569 QLIST_FOREACH(sec, &bus->child, sibling) {
570 int32_t devfn = sec->parent_dev->devfn;
571
572 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
573 continue;
574 }
575
576 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
577 }
578 }
579 aml_append(parent_scope, method);
580 qobject_unref(bsel);
581}
582
583
584
585
586
587
588
589static Aml *build_prt_entry(const char *link_name)
590{
591 Aml *a_zero = aml_int(0);
592 Aml *pkg = aml_package(4);
593 aml_append(pkg, a_zero);
594 aml_append(pkg, a_zero);
595 aml_append(pkg, aml_name("%s", link_name));
596 aml_append(pkg, a_zero);
597 return pkg;
598}
599
600
601
602
603
604
605
606static Aml *initialize_route(Aml *route, const char *link_name,
607 Aml *lnk_idx, int idx)
608{
609 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
610 Aml *pkg = build_prt_entry(link_name);
611
612 aml_append(if_ctx, aml_store(pkg, route));
613
614 return if_ctx;
615}
616
617
618
619
620
621
622
623
624
625
626
627static Aml *build_prt(bool is_pci0_prt)
628{
629 Aml *method, *while_ctx, *pin, *res;
630
631 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
632 res = aml_local(0);
633 pin = aml_local(1);
634 aml_append(method, aml_store(aml_package(128), res));
635 aml_append(method, aml_store(aml_int(0), pin));
636
637
638 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
639 {
640 Aml *slot = aml_local(2);
641 Aml *lnk_idx = aml_local(3);
642 Aml *route = aml_local(4);
643
644
645 aml_append(while_ctx,
646 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
647
648 aml_append(while_ctx,
649 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
650 lnk_idx));
651
652
653 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
654 if (is_pci0_prt) {
655 Aml *if_device_1, *if_pin_4, *else_pin_4;
656
657
658 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
659 {
660 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
661 {
662 aml_append(if_pin_4,
663 aml_store(build_prt_entry("LNKS"), route));
664 }
665 aml_append(if_device_1, if_pin_4);
666 else_pin_4 = aml_else();
667 {
668 aml_append(else_pin_4,
669 aml_store(build_prt_entry("LNKA"), route));
670 }
671 aml_append(if_device_1, else_pin_4);
672 }
673 aml_append(while_ctx, if_device_1);
674 } else {
675 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
676 }
677 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
678 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
679
680
681 aml_append(while_ctx,
682 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
683 NULL),
684 aml_index(route, aml_int(0))));
685
686 aml_append(while_ctx,
687 aml_store(aml_and(pin, aml_int(3), NULL),
688 aml_index(route, aml_int(1))));
689
690 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
691
692 aml_append(while_ctx, aml_increment(pin));
693 }
694 aml_append(method, while_ctx);
695
696 aml_append(method, aml_return(res));
697
698 return method;
699}
700
701typedef struct CrsRangeEntry {
702 uint64_t base;
703 uint64_t limit;
704} CrsRangeEntry;
705
706static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
707{
708 CrsRangeEntry *entry;
709
710 entry = g_malloc(sizeof(*entry));
711 entry->base = base;
712 entry->limit = limit;
713
714 g_ptr_array_add(ranges, entry);
715}
716
717static void crs_range_free(gpointer data)
718{
719 CrsRangeEntry *entry = (CrsRangeEntry *)data;
720 g_free(entry);
721}
722
723typedef struct CrsRangeSet {
724 GPtrArray *io_ranges;
725 GPtrArray *mem_ranges;
726 GPtrArray *mem_64bit_ranges;
727 } CrsRangeSet;
728
729static void crs_range_set_init(CrsRangeSet *range_set)
730{
731 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
732 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
733 range_set->mem_64bit_ranges =
734 g_ptr_array_new_with_free_func(crs_range_free);
735}
736
737static void crs_range_set_free(CrsRangeSet *range_set)
738{
739 g_ptr_array_free(range_set->io_ranges, true);
740 g_ptr_array_free(range_set->mem_ranges, true);
741 g_ptr_array_free(range_set->mem_64bit_ranges, true);
742}
743
744static gint crs_range_compare(gconstpointer a, gconstpointer b)
745{
746 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
747 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
748
749 if (entry_a->base < entry_b->base) {
750 return -1;
751 } else if (entry_a->base > entry_b->base) {
752 return 1;
753 } else {
754 return 0;
755 }
756}
757
758
759
760
761
762
763
764static void crs_replace_with_free_ranges(GPtrArray *ranges,
765 uint64_t start, uint64_t end)
766{
767 GPtrArray *free_ranges = g_ptr_array_new();
768 uint64_t free_base = start;
769 int i;
770
771 g_ptr_array_sort(ranges, crs_range_compare);
772 for (i = 0; i < ranges->len; i++) {
773 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
774
775 if (free_base < used->base) {
776 crs_range_insert(free_ranges, free_base, used->base - 1);
777 }
778
779 free_base = used->limit + 1;
780 }
781
782 if (free_base < end) {
783 crs_range_insert(free_ranges, free_base, end);
784 }
785
786 g_ptr_array_set_size(ranges, 0);
787 for (i = 0; i < free_ranges->len; i++) {
788 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
789 }
790
791 g_ptr_array_free(free_ranges, true);
792}
793
794
795
796
797
798static void crs_range_merge(GPtrArray *range)
799{
800 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
801 CrsRangeEntry *entry;
802 uint64_t range_base, range_limit;
803 int i;
804
805 if (!range->len) {
806 return;
807 }
808
809 g_ptr_array_sort(range, crs_range_compare);
810
811 entry = g_ptr_array_index(range, 0);
812 range_base = entry->base;
813 range_limit = entry->limit;
814 for (i = 1; i < range->len; i++) {
815 entry = g_ptr_array_index(range, i);
816 if (entry->base - 1 == range_limit) {
817 range_limit = entry->limit;
818 } else {
819 crs_range_insert(tmp, range_base, range_limit);
820 range_base = entry->base;
821 range_limit = entry->limit;
822 }
823 }
824 crs_range_insert(tmp, range_base, range_limit);
825
826 g_ptr_array_set_size(range, 0);
827 for (i = 0; i < tmp->len; i++) {
828 entry = g_ptr_array_index(tmp, i);
829 crs_range_insert(range, entry->base, entry->limit);
830 }
831 g_ptr_array_free(tmp, true);
832}
833
834static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
835{
836 Aml *crs = aml_resource_template();
837 CrsRangeSet temp_range_set;
838 CrsRangeEntry *entry;
839 uint8_t max_bus = pci_bus_num(host->bus);
840 uint8_t type;
841 int devfn;
842 int i;
843
844 crs_range_set_init(&temp_range_set);
845 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
846 uint64_t range_base, range_limit;
847 PCIDevice *dev = host->bus->devices[devfn];
848
849 if (!dev) {
850 continue;
851 }
852
853 for (i = 0; i < PCI_NUM_REGIONS; i++) {
854 PCIIORegion *r = &dev->io_regions[i];
855
856 range_base = r->addr;
857 range_limit = r->addr + r->size - 1;
858
859
860
861
862
863 if (!range_base || range_base > range_limit) {
864 continue;
865 }
866
867 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
868 crs_range_insert(temp_range_set.io_ranges,
869 range_base, range_limit);
870 } else {
871 crs_range_insert(temp_range_set.mem_ranges,
872 range_base, range_limit);
873 }
874 }
875
876 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
877 if (type == PCI_HEADER_TYPE_BRIDGE) {
878 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
879 if (subordinate > max_bus) {
880 max_bus = subordinate;
881 }
882
883 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
884 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
885
886
887
888
889
890 if (range_base && range_base <= range_limit) {
891 crs_range_insert(temp_range_set.io_ranges,
892 range_base, range_limit);
893 }
894
895 range_base =
896 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
897 range_limit =
898 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
899
900
901
902
903
904 if (range_base && range_base <= range_limit) {
905 uint64_t length = range_limit - range_base + 1;
906 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
907 crs_range_insert(temp_range_set.mem_ranges,
908 range_base, range_limit);
909 } else {
910 crs_range_insert(temp_range_set.mem_64bit_ranges,
911 range_base, range_limit);
912 }
913 }
914
915 range_base =
916 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
917 range_limit =
918 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
919
920
921
922
923
924 if (range_base && range_base <= range_limit) {
925 uint64_t length = range_limit - range_base + 1;
926 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
927 crs_range_insert(temp_range_set.mem_ranges,
928 range_base, range_limit);
929 } else {
930 crs_range_insert(temp_range_set.mem_64bit_ranges,
931 range_base, range_limit);
932 }
933 }
934 }
935 }
936
937 crs_range_merge(temp_range_set.io_ranges);
938 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
939 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
940 aml_append(crs,
941 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
942 AML_POS_DECODE, AML_ENTIRE_RANGE,
943 0, entry->base, entry->limit, 0,
944 entry->limit - entry->base + 1));
945 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
946 }
947
948 crs_range_merge(temp_range_set.mem_ranges);
949 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
950 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
951 aml_append(crs,
952 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
953 AML_MAX_FIXED, AML_NON_CACHEABLE,
954 AML_READ_WRITE,
955 0, entry->base, entry->limit, 0,
956 entry->limit - entry->base + 1));
957 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
958 }
959
960 crs_range_merge(temp_range_set.mem_64bit_ranges);
961 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
962 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
963 aml_append(crs,
964 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
965 AML_MAX_FIXED, AML_NON_CACHEABLE,
966 AML_READ_WRITE,
967 0, entry->base, entry->limit, 0,
968 entry->limit - entry->base + 1));
969 crs_range_insert(range_set->mem_64bit_ranges,
970 entry->base, entry->limit);
971 }
972
973 crs_range_set_free(&temp_range_set);
974
975 aml_append(crs,
976 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
977 0,
978 pci_bus_num(host->bus),
979 max_bus,
980 0,
981 max_bus - pci_bus_num(host->bus) + 1));
982
983 return crs;
984}
985
986static void build_hpet_aml(Aml *table)
987{
988 Aml *crs;
989 Aml *field;
990 Aml *method;
991 Aml *if_ctx;
992 Aml *scope = aml_scope("_SB");
993 Aml *dev = aml_device("HPET");
994 Aml *zero = aml_int(0);
995 Aml *id = aml_local(0);
996 Aml *period = aml_local(1);
997
998 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
999 aml_append(dev, aml_name_decl("_UID", zero));
1000
1001 aml_append(dev,
1002 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1003 HPET_LEN));
1004 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1005 aml_append(field, aml_named_field("VEND", 32));
1006 aml_append(field, aml_named_field("PRD", 32));
1007 aml_append(dev, field);
1008
1009 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1010 aml_append(method, aml_store(aml_name("VEND"), id));
1011 aml_append(method, aml_store(aml_name("PRD"), period));
1012 aml_append(method, aml_shiftright(id, aml_int(16), id));
1013 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1014 aml_equal(id, aml_int(0xffff))));
1015 {
1016 aml_append(if_ctx, aml_return(zero));
1017 }
1018 aml_append(method, if_ctx);
1019
1020 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1021 aml_lgreater(period, aml_int(100000000))));
1022 {
1023 aml_append(if_ctx, aml_return(zero));
1024 }
1025 aml_append(method, if_ctx);
1026
1027 aml_append(method, aml_return(aml_int(0x0F)));
1028 aml_append(dev, method);
1029
1030 crs = aml_resource_template();
1031 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1032 aml_append(dev, aml_name_decl("_CRS", crs));
1033
1034 aml_append(scope, dev);
1035 aml_append(table, scope);
1036}
1037
1038static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1039{
1040 Aml *dev, *fdi;
1041 uint8_t maxc, maxh, maxs;
1042
1043 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1044
1045 dev = aml_device("FLP%c", 'A' + idx);
1046
1047 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1048
1049 fdi = aml_package(16);
1050 aml_append(fdi, aml_int(idx));
1051 aml_append(fdi,
1052 aml_int(cmos_get_fd_drive_type(type)));
1053
1054
1055
1056
1057 aml_append(fdi, aml_int(maxc));
1058 aml_append(fdi, aml_int(maxs));
1059 aml_append(fdi, aml_int(maxh));
1060
1061
1062
1063
1064 aml_append(fdi, aml_int(0xAF));
1065 aml_append(fdi, aml_int(0x02));
1066 aml_append(fdi, aml_int(0x25));
1067 aml_append(fdi, aml_int(0x02));
1068 aml_append(fdi, aml_int(0x12));
1069 aml_append(fdi, aml_int(0x1B));
1070 aml_append(fdi, aml_int(0xFF));
1071 aml_append(fdi, aml_int(0x6C));
1072 aml_append(fdi, aml_int(0xF6));
1073 aml_append(fdi, aml_int(0x0F));
1074 aml_append(fdi, aml_int(0x08));
1075
1076 aml_append(dev, aml_name_decl("_FDI", fdi));
1077 return dev;
1078}
1079
1080static Aml *build_fdc_device_aml(ISADevice *fdc)
1081{
1082 int i;
1083 Aml *dev;
1084 Aml *crs;
1085
1086#define ACPI_FDE_MAX_FD 4
1087 uint32_t fde_buf[5] = {
1088 0, 0, 0, 0,
1089 cpu_to_le32(2)
1090 };
1091
1092 dev = aml_device("FDC0");
1093 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1094
1095 crs = aml_resource_template();
1096 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1097 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1098 aml_append(crs, aml_irq_no_flags(6));
1099 aml_append(crs,
1100 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1101 aml_append(dev, aml_name_decl("_CRS", crs));
1102
1103 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1104 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1105
1106 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1107 fde_buf[i] = cpu_to_le32(1);
1108 aml_append(dev, build_fdinfo_aml(i, type));
1109 }
1110 }
1111 aml_append(dev, aml_name_decl("_FDE",
1112 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1113
1114 return dev;
1115}
1116
1117static Aml *build_rtc_device_aml(void)
1118{
1119 Aml *dev;
1120 Aml *crs;
1121
1122 dev = aml_device("RTC");
1123 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1124 crs = aml_resource_template();
1125 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1126 aml_append(crs, aml_irq_no_flags(8));
1127 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1128 aml_append(dev, aml_name_decl("_CRS", crs));
1129
1130 return dev;
1131}
1132
1133static Aml *build_kbd_device_aml(void)
1134{
1135 Aml *dev;
1136 Aml *crs;
1137 Aml *method;
1138
1139 dev = aml_device("KBD");
1140 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1141
1142 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1143 aml_append(method, aml_return(aml_int(0x0f)));
1144 aml_append(dev, method);
1145
1146 crs = aml_resource_template();
1147 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1148 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1149 aml_append(crs, aml_irq_no_flags(1));
1150 aml_append(dev, aml_name_decl("_CRS", crs));
1151
1152 return dev;
1153}
1154
1155static Aml *build_mouse_device_aml(void)
1156{
1157 Aml *dev;
1158 Aml *crs;
1159 Aml *method;
1160
1161 dev = aml_device("MOU");
1162 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1163
1164 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1165 aml_append(method, aml_return(aml_int(0x0f)));
1166 aml_append(dev, method);
1167
1168 crs = aml_resource_template();
1169 aml_append(crs, aml_irq_no_flags(12));
1170 aml_append(dev, aml_name_decl("_CRS", crs));
1171
1172 return dev;
1173}
1174
1175static Aml *build_lpt_device_aml(void)
1176{
1177 Aml *dev;
1178 Aml *crs;
1179 Aml *method;
1180 Aml *if_ctx;
1181 Aml *else_ctx;
1182 Aml *zero = aml_int(0);
1183 Aml *is_present = aml_local(0);
1184
1185 dev = aml_device("LPT");
1186 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1187
1188 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1189 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1190 if_ctx = aml_if(aml_equal(is_present, zero));
1191 {
1192 aml_append(if_ctx, aml_return(aml_int(0x00)));
1193 }
1194 aml_append(method, if_ctx);
1195 else_ctx = aml_else();
1196 {
1197 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1198 }
1199 aml_append(method, else_ctx);
1200 aml_append(dev, method);
1201
1202 crs = aml_resource_template();
1203 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1204 aml_append(crs, aml_irq_no_flags(7));
1205 aml_append(dev, aml_name_decl("_CRS", crs));
1206
1207 return dev;
1208}
1209
1210static Aml *build_com_device_aml(uint8_t uid)
1211{
1212 Aml *dev;
1213 Aml *crs;
1214 Aml *method;
1215 Aml *if_ctx;
1216 Aml *else_ctx;
1217 Aml *zero = aml_int(0);
1218 Aml *is_present = aml_local(0);
1219 const char *enabled_field = "CAEN";
1220 uint8_t irq = 4;
1221 uint16_t io_port = 0x03F8;
1222
1223 assert(uid == 1 || uid == 2);
1224 if (uid == 2) {
1225 enabled_field = "CBEN";
1226 irq = 3;
1227 io_port = 0x02F8;
1228 }
1229
1230 dev = aml_device("COM%d", uid);
1231 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1232 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1233
1234 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1235 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1236 if_ctx = aml_if(aml_equal(is_present, zero));
1237 {
1238 aml_append(if_ctx, aml_return(aml_int(0x00)));
1239 }
1240 aml_append(method, if_ctx);
1241 else_ctx = aml_else();
1242 {
1243 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1244 }
1245 aml_append(method, else_ctx);
1246 aml_append(dev, method);
1247
1248 crs = aml_resource_template();
1249 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1250 aml_append(crs, aml_irq_no_flags(irq));
1251 aml_append(dev, aml_name_decl("_CRS", crs));
1252
1253 return dev;
1254}
1255
1256static void build_isa_devices_aml(Aml *table)
1257{
1258 ISADevice *fdc = pc_find_fdc0();
1259 bool ambiguous;
1260
1261 Aml *scope = aml_scope("_SB.PCI0.ISA");
1262 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1263
1264 aml_append(scope, build_rtc_device_aml());
1265 aml_append(scope, build_kbd_device_aml());
1266 aml_append(scope, build_mouse_device_aml());
1267 if (fdc) {
1268 aml_append(scope, build_fdc_device_aml(fdc));
1269 }
1270 aml_append(scope, build_lpt_device_aml());
1271 aml_append(scope, build_com_device_aml(1));
1272 aml_append(scope, build_com_device_aml(2));
1273
1274 if (ambiguous) {
1275 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1276 } else if (!obj) {
1277 error_report("No ISA bus, unable to define IPMI ACPI data");
1278 } else {
1279 build_acpi_ipmi_devices(scope, BUS(obj));
1280 }
1281
1282 aml_append(table, scope);
1283}
1284
1285static void build_dbg_aml(Aml *table)
1286{
1287 Aml *field;
1288 Aml *method;
1289 Aml *while_ctx;
1290 Aml *scope = aml_scope("\\");
1291 Aml *buf = aml_local(0);
1292 Aml *len = aml_local(1);
1293 Aml *idx = aml_local(2);
1294
1295 aml_append(scope,
1296 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1297 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1298 aml_append(field, aml_named_field("DBGB", 8));
1299 aml_append(scope, field);
1300
1301 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1302
1303 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1304 aml_append(method, aml_to_buffer(buf, buf));
1305 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1306 aml_append(method, aml_store(aml_int(0), idx));
1307
1308 while_ctx = aml_while(aml_lless(idx, len));
1309 aml_append(while_ctx,
1310 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1311 aml_append(while_ctx, aml_increment(idx));
1312 aml_append(method, while_ctx);
1313
1314 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1315 aml_append(scope, method);
1316
1317 aml_append(table, scope);
1318}
1319
1320static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1321{
1322 Aml *dev;
1323 Aml *crs;
1324 Aml *method;
1325 uint32_t irqs[] = {5, 10, 11};
1326
1327 dev = aml_device("%s", name);
1328 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1329 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1330
1331 crs = aml_resource_template();
1332 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1333 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1334 aml_append(dev, aml_name_decl("_PRS", crs));
1335
1336 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1337 aml_append(method, aml_return(aml_call1("IQST", reg)));
1338 aml_append(dev, method);
1339
1340 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1341 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1342 aml_append(dev, method);
1343
1344 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1345 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1346 aml_append(dev, method);
1347
1348 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1349 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1350 aml_append(method, aml_store(aml_name("PRRI"), reg));
1351 aml_append(dev, method);
1352
1353 return dev;
1354 }
1355
1356static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1357{
1358 Aml *dev;
1359 Aml *crs;
1360 Aml *method;
1361 uint32_t irqs;
1362
1363 dev = aml_device("%s", name);
1364 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1365 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1366
1367 crs = aml_resource_template();
1368 irqs = gsi;
1369 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1370 AML_SHARED, &irqs, 1));
1371 aml_append(dev, aml_name_decl("_PRS", crs));
1372
1373 aml_append(dev, aml_name_decl("_CRS", crs));
1374
1375
1376
1377
1378 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1379 aml_append(dev, method);
1380
1381 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1382 aml_append(dev, method);
1383
1384 return dev;
1385}
1386
1387
1388static Aml *build_iqcr_method(bool is_piix4)
1389{
1390 Aml *if_ctx;
1391 uint32_t irqs;
1392 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1393 Aml *crs = aml_resource_template();
1394
1395 irqs = 0;
1396 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1397 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1398 aml_append(method, aml_name_decl("PRR0", crs));
1399
1400 aml_append(method,
1401 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1402
1403 if (is_piix4) {
1404 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1405 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1406 aml_append(method, if_ctx);
1407 } else {
1408 aml_append(method,
1409 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1410 aml_name("PRRI")));
1411 }
1412
1413 aml_append(method, aml_return(aml_name("PRR0")));
1414 return method;
1415}
1416
1417
1418static Aml *build_irq_status_method(void)
1419{
1420 Aml *if_ctx;
1421 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1422
1423 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1424 aml_append(if_ctx, aml_return(aml_int(0x09)));
1425 aml_append(method, if_ctx);
1426 aml_append(method, aml_return(aml_int(0x0B)));
1427 return method;
1428}
1429
1430static void build_piix4_pci0_int(Aml *table)
1431{
1432 Aml *dev;
1433 Aml *crs;
1434 Aml *field;
1435 Aml *method;
1436 uint32_t irqs;
1437 Aml *sb_scope = aml_scope("_SB");
1438 Aml *pci0_scope = aml_scope("PCI0");
1439
1440 aml_append(pci0_scope, build_prt(true));
1441 aml_append(sb_scope, pci0_scope);
1442
1443 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1444 aml_append(field, aml_named_field("PRQ0", 8));
1445 aml_append(field, aml_named_field("PRQ1", 8));
1446 aml_append(field, aml_named_field("PRQ2", 8));
1447 aml_append(field, aml_named_field("PRQ3", 8));
1448 aml_append(sb_scope, field);
1449
1450 aml_append(sb_scope, build_irq_status_method());
1451 aml_append(sb_scope, build_iqcr_method(true));
1452
1453 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1454 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1455 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1456 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1457
1458 dev = aml_device("LNKS");
1459 {
1460 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1461 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1462
1463 crs = aml_resource_template();
1464 irqs = 9;
1465 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1466 AML_ACTIVE_HIGH, AML_SHARED,
1467 &irqs, 1));
1468 aml_append(dev, aml_name_decl("_PRS", crs));
1469
1470
1471
1472
1473
1474 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1475 aml_append(method, aml_return(aml_int(0x0b)));
1476 aml_append(dev, method);
1477
1478 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1479 aml_append(dev, method);
1480
1481 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1482 aml_append(method, aml_return(aml_name("_PRS")));
1483 aml_append(dev, method);
1484
1485 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1486 aml_append(dev, method);
1487 }
1488 aml_append(sb_scope, dev);
1489
1490 aml_append(table, sb_scope);
1491}
1492
1493static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1494{
1495 int i;
1496 int head;
1497 Aml *pkg;
1498 char base = name[3] < 'E' ? 'A' : 'E';
1499 char *s = g_strdup(name);
1500 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1501
1502 assert(strlen(s) == 4);
1503
1504 head = name[3] - base;
1505 for (i = 0; i < 4; i++) {
1506 if (head + i > 3) {
1507 head = i * -1;
1508 }
1509 s[3] = base + head + i;
1510 pkg = aml_package(4);
1511 aml_append(pkg, a_nr);
1512 aml_append(pkg, aml_int(i));
1513 aml_append(pkg, aml_name("%s", s));
1514 aml_append(pkg, aml_int(0));
1515 aml_append(ctx, pkg);
1516 }
1517 g_free(s);
1518}
1519
1520static Aml *build_q35_routing_table(const char *str)
1521{
1522 int i;
1523 Aml *pkg;
1524 char *name = g_strdup_printf("%s ", str);
1525
1526 pkg = aml_package(128);
1527 for (i = 0; i < 0x18; i++) {
1528 name[3] = 'E' + (i & 0x3);
1529 append_q35_prt_entry(pkg, i, name);
1530 }
1531
1532 name[3] = 'E';
1533 append_q35_prt_entry(pkg, 0x18, name);
1534
1535
1536 for (i = 0x0019; i < 0x1e; i++) {
1537 name[3] = 'A';
1538 append_q35_prt_entry(pkg, i, name);
1539 }
1540
1541
1542 name[3] = 'E';
1543 append_q35_prt_entry(pkg, 0x1e, name);
1544 name[3] = 'A';
1545 append_q35_prt_entry(pkg, 0x1f, name);
1546
1547 g_free(name);
1548 return pkg;
1549}
1550
1551static void build_q35_pci0_int(Aml *table)
1552{
1553 Aml *field;
1554 Aml *method;
1555 Aml *sb_scope = aml_scope("_SB");
1556 Aml *pci0_scope = aml_scope("PCI0");
1557
1558
1559 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1560 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1561 {
1562 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1563 }
1564 aml_append(table, method);
1565
1566 aml_append(pci0_scope,
1567 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1568 aml_append(pci0_scope,
1569 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1570
1571 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1572 {
1573 Aml *if_ctx;
1574 Aml *else_ctx;
1575
1576
1577
1578
1579
1580 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1581 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1582 aml_append(method, if_ctx);
1583 else_ctx = aml_else();
1584 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1585 aml_append(method, else_ctx);
1586 }
1587 aml_append(pci0_scope, method);
1588 aml_append(sb_scope, pci0_scope);
1589
1590 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1591 aml_append(field, aml_named_field("PRQA", 8));
1592 aml_append(field, aml_named_field("PRQB", 8));
1593 aml_append(field, aml_named_field("PRQC", 8));
1594 aml_append(field, aml_named_field("PRQD", 8));
1595 aml_append(field, aml_reserved_field(0x20));
1596 aml_append(field, aml_named_field("PRQE", 8));
1597 aml_append(field, aml_named_field("PRQF", 8));
1598 aml_append(field, aml_named_field("PRQG", 8));
1599 aml_append(field, aml_named_field("PRQH", 8));
1600 aml_append(sb_scope, field);
1601
1602 aml_append(sb_scope, build_irq_status_method());
1603 aml_append(sb_scope, build_iqcr_method(false));
1604
1605 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1606 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1607 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1608 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1609 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1610 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1611 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1612 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1613
1614 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1615 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1616 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1617 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1618 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1619 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1620 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1621 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1622
1623 aml_append(table, sb_scope);
1624}
1625
1626static void build_q35_isa_bridge(Aml *table)
1627{
1628 Aml *dev;
1629 Aml *scope;
1630 Aml *field;
1631
1632 scope = aml_scope("_SB.PCI0");
1633 dev = aml_device("ISA");
1634 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1635
1636
1637 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1638 aml_int(0x60), 0x0C));
1639
1640 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1641 aml_int(0x80), 0x02));
1642 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1643 aml_append(field, aml_named_field("COMA", 3));
1644 aml_append(field, aml_reserved_field(1));
1645 aml_append(field, aml_named_field("COMB", 3));
1646 aml_append(field, aml_reserved_field(1));
1647 aml_append(field, aml_named_field("LPTD", 2));
1648 aml_append(dev, field);
1649
1650 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1651 aml_int(0x82), 0x02));
1652
1653 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1654 aml_append(field, aml_named_field("CAEN", 1));
1655 aml_append(field, aml_named_field("CBEN", 1));
1656 aml_append(field, aml_named_field("LPEN", 1));
1657 aml_append(dev, field);
1658
1659 aml_append(scope, dev);
1660 aml_append(table, scope);
1661}
1662
1663static void build_piix4_pm(Aml *table)
1664{
1665 Aml *dev;
1666 Aml *scope;
1667
1668 scope = aml_scope("_SB.PCI0");
1669 dev = aml_device("PX13");
1670 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1671
1672 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1673 aml_int(0x00), 0xff));
1674 aml_append(scope, dev);
1675 aml_append(table, scope);
1676}
1677
1678static void build_piix4_isa_bridge(Aml *table)
1679{
1680 Aml *dev;
1681 Aml *scope;
1682 Aml *field;
1683
1684 scope = aml_scope("_SB.PCI0");
1685 dev = aml_device("ISA");
1686 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1687
1688
1689 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1690 aml_int(0x60), 0x04));
1691
1692 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1693
1694 aml_append(field, aml_reserved_field(0x2f8));
1695 aml_append(field, aml_reserved_field(7));
1696 aml_append(field, aml_named_field("LPEN", 1));
1697
1698 aml_append(field, aml_reserved_field(0x38));
1699 aml_append(field, aml_reserved_field(3));
1700 aml_append(field, aml_named_field("CAEN", 1));
1701 aml_append(field, aml_reserved_field(3));
1702 aml_append(field, aml_named_field("CBEN", 1));
1703 aml_append(dev, field);
1704
1705 aml_append(scope, dev);
1706 aml_append(table, scope);
1707}
1708
1709static void build_piix4_pci_hotplug(Aml *table)
1710{
1711 Aml *scope;
1712 Aml *field;
1713 Aml *method;
1714
1715 scope = aml_scope("_SB.PCI0");
1716
1717 aml_append(scope,
1718 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1719 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1720 aml_append(field, aml_named_field("PCIU", 32));
1721 aml_append(field, aml_named_field("PCID", 32));
1722 aml_append(scope, field);
1723
1724 aml_append(scope,
1725 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1726 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1727 aml_append(field, aml_named_field("B0EJ", 32));
1728 aml_append(scope, field);
1729
1730 aml_append(scope,
1731 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1732 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1733 aml_append(field, aml_named_field("BNUM", 32));
1734 aml_append(scope, field);
1735
1736 aml_append(scope, aml_mutex("BLCK", 0));
1737
1738 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1739 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1740 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1741 aml_append(method,
1742 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1743 aml_append(method, aml_release(aml_name("BLCK")));
1744 aml_append(method, aml_return(aml_int(0)));
1745 aml_append(scope, method);
1746
1747 aml_append(table, scope);
1748}
1749
1750static Aml *build_q35_osc_method(void)
1751{
1752 Aml *if_ctx;
1753 Aml *if_ctx2;
1754 Aml *else_ctx;
1755 Aml *method;
1756 Aml *a_cwd1 = aml_name("CDW1");
1757 Aml *a_ctrl = aml_local(0);
1758
1759 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1760 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1761
1762 if_ctx = aml_if(aml_equal(
1763 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1764 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1765 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1766
1767 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1768
1769
1770
1771
1772
1773 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1774
1775 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1776
1777 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1778 aml_append(if_ctx, if_ctx2);
1779
1780 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1781
1782 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1783 aml_append(if_ctx, if_ctx2);
1784
1785
1786 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1787 aml_append(method, if_ctx);
1788
1789 else_ctx = aml_else();
1790
1791 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1792 aml_append(method, else_ctx);
1793
1794 aml_append(method, aml_return(aml_arg(3)));
1795 return method;
1796}
1797
1798static void
1799build_dsdt(GArray *table_data, BIOSLinker *linker,
1800 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1801 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1802{
1803 CrsRangeEntry *entry;
1804 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1805 CrsRangeSet crs_range_set;
1806 PCMachineState *pcms = PC_MACHINE(machine);
1807 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1808 uint32_t nr_mem = machine->ram_slots;
1809 int root_bus_limit = 0xFF;
1810 PCIBus *bus = NULL;
1811 TPMIf *tpm = tpm_find();
1812 int i;
1813
1814 dsdt = init_aml_allocator();
1815
1816
1817 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1818
1819 build_dbg_aml(dsdt);
1820 if (misc->is_piix4) {
1821 sb_scope = aml_scope("_SB");
1822 dev = aml_device("PCI0");
1823 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1824 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1825 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1826 aml_append(sb_scope, dev);
1827 aml_append(dsdt, sb_scope);
1828
1829 build_hpet_aml(dsdt);
1830 build_piix4_pm(dsdt);
1831 build_piix4_isa_bridge(dsdt);
1832 build_isa_devices_aml(dsdt);
1833 build_piix4_pci_hotplug(dsdt);
1834 build_piix4_pci0_int(dsdt);
1835 } else {
1836 sb_scope = aml_scope("_SB");
1837 dev = aml_device("PCI0");
1838 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1839 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1840 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1841 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1842 aml_append(dev, build_q35_osc_method());
1843 aml_append(sb_scope, dev);
1844 aml_append(dsdt, sb_scope);
1845
1846 build_hpet_aml(dsdt);
1847 build_q35_isa_bridge(dsdt);
1848 build_isa_devices_aml(dsdt);
1849 build_q35_pci0_int(dsdt);
1850 }
1851
1852 if (pcmc->legacy_cpu_hotplug) {
1853 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1854 } else {
1855 CPUHotplugFeatures opts = {
1856 .acpi_1_compatible = true, .has_legacy_cphp = true
1857 };
1858 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1859 "\\_SB.PCI0", "\\_GPE._E02");
1860 }
1861 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03");
1862
1863 scope = aml_scope("_GPE");
1864 {
1865 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1866
1867 if (misc->is_piix4) {
1868 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1869 aml_append(method,
1870 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1871 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1872 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1873 aml_append(scope, method);
1874 }
1875
1876 if (machine->nvdimms_state->is_enabled) {
1877 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1878 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1879 aml_int(0x80)));
1880 aml_append(scope, method);
1881 }
1882 }
1883 aml_append(dsdt, scope);
1884
1885 crs_range_set_init(&crs_range_set);
1886 bus = PC_MACHINE(machine)->bus;
1887 if (bus) {
1888 QLIST_FOREACH(bus, &bus->child, sibling) {
1889 uint8_t bus_num = pci_bus_num(bus);
1890 uint8_t numa_node = pci_bus_numa_node(bus);
1891
1892
1893 if (!pci_bus_is_root(bus)) {
1894 continue;
1895 }
1896
1897 if (bus_num < root_bus_limit) {
1898 root_bus_limit = bus_num - 1;
1899 }
1900
1901 scope = aml_scope("\\_SB");
1902 dev = aml_device("PC%.02X", bus_num);
1903 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1904 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1905 if (pci_bus_is_express(bus)) {
1906 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1907 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1908 aml_append(dev, build_q35_osc_method());
1909 } else {
1910 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1911 }
1912
1913 if (numa_node != NUMA_NODE_UNASSIGNED) {
1914 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1915 }
1916
1917 aml_append(dev, build_prt(false));
1918 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1919 aml_append(dev, aml_name_decl("_CRS", crs));
1920 aml_append(scope, dev);
1921 aml_append(dsdt, scope);
1922 }
1923 }
1924
1925 scope = aml_scope("\\_SB.PCI0");
1926
1927 crs = aml_resource_template();
1928 aml_append(crs,
1929 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1930 0x0000, 0x0, root_bus_limit,
1931 0x0000, root_bus_limit + 1));
1932 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1933
1934 aml_append(crs,
1935 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1936 AML_POS_DECODE, AML_ENTIRE_RANGE,
1937 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1938
1939 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1940 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1941 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1942 aml_append(crs,
1943 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1944 AML_POS_DECODE, AML_ENTIRE_RANGE,
1945 0x0000, entry->base, entry->limit,
1946 0x0000, entry->limit - entry->base + 1));
1947 }
1948
1949 aml_append(crs,
1950 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1951 AML_CACHEABLE, AML_READ_WRITE,
1952 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1953
1954 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1955 range_lob(pci_hole),
1956 range_upb(pci_hole));
1957 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1958 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1959 aml_append(crs,
1960 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1961 AML_NON_CACHEABLE, AML_READ_WRITE,
1962 0, entry->base, entry->limit,
1963 0, entry->limit - entry->base + 1));
1964 }
1965
1966 if (!range_is_empty(pci_hole64)) {
1967 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1968 range_lob(pci_hole64),
1969 range_upb(pci_hole64));
1970 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1971 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1972 aml_append(crs,
1973 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1974 AML_MAX_FIXED,
1975 AML_CACHEABLE, AML_READ_WRITE,
1976 0, entry->base, entry->limit,
1977 0, entry->limit - entry->base + 1));
1978 }
1979 }
1980
1981 if (TPM_IS_TIS(tpm_find())) {
1982 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1983 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1984 }
1985 aml_append(scope, aml_name_decl("_CRS", crs));
1986
1987
1988 dev = aml_device("GPE0");
1989 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1990 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1991
1992 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1993 crs = aml_resource_template();
1994 aml_append(crs,
1995 aml_io(
1996 AML_DECODE16,
1997 pm->fadt.gpe0_blk.address,
1998 pm->fadt.gpe0_blk.address,
1999 1,
2000 pm->fadt.gpe0_blk.bit_width / 8)
2001 );
2002 aml_append(dev, aml_name_decl("_CRS", crs));
2003 aml_append(scope, dev);
2004
2005 crs_range_set_free(&crs_range_set);
2006
2007
2008 if (pm->pcihp_io_len) {
2009 dev = aml_device("PHPR");
2010 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2011 aml_append(dev,
2012 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2013
2014 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2015 crs = aml_resource_template();
2016 aml_append(crs,
2017 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2018 pm->pcihp_io_len)
2019 );
2020 aml_append(dev, aml_name_decl("_CRS", crs));
2021 aml_append(scope, dev);
2022 }
2023 aml_append(dsdt, scope);
2024
2025
2026 scope = aml_scope("\\");
2027 if (!pm->s3_disabled) {
2028 pkg = aml_package(4);
2029 aml_append(pkg, aml_int(1));
2030 aml_append(pkg, aml_int(1));
2031 aml_append(pkg, aml_int(0));
2032 aml_append(pkg, aml_int(0));
2033 aml_append(scope, aml_name_decl("_S3", pkg));
2034 }
2035
2036 if (!pm->s4_disabled) {
2037 pkg = aml_package(4);
2038 aml_append(pkg, aml_int(pm->s4_val));
2039
2040 aml_append(pkg, aml_int(pm->s4_val));
2041 aml_append(pkg, aml_int(0));
2042 aml_append(pkg, aml_int(0));
2043 aml_append(scope, aml_name_decl("_S4", pkg));
2044 }
2045
2046 pkg = aml_package(4);
2047 aml_append(pkg, aml_int(0));
2048 aml_append(pkg, aml_int(0));
2049 aml_append(pkg, aml_int(0));
2050 aml_append(pkg, aml_int(0));
2051 aml_append(scope, aml_name_decl("_S5", pkg));
2052 aml_append(dsdt, scope);
2053
2054
2055 {
2056
2057
2058
2059
2060 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2061 "dma_enabled", NULL) ?
2062 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2063 FW_CFG_CTL_SIZE;
2064
2065 scope = aml_scope("\\_SB.PCI0");
2066 dev = aml_device("FWCF");
2067
2068 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2069
2070
2071 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2072
2073 crs = aml_resource_template();
2074 aml_append(crs,
2075 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2076 );
2077 aml_append(dev, aml_name_decl("_CRS", crs));
2078
2079 aml_append(scope, dev);
2080 aml_append(dsdt, scope);
2081 }
2082
2083 if (misc->applesmc_io_base) {
2084 scope = aml_scope("\\_SB.PCI0.ISA");
2085 dev = aml_device("SMC");
2086
2087 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2088
2089 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2090
2091 crs = aml_resource_template();
2092 aml_append(crs,
2093 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2094 0x01, APPLESMC_MAX_DATA_LENGTH)
2095 );
2096 aml_append(crs, aml_irq_no_flags(6));
2097 aml_append(dev, aml_name_decl("_CRS", crs));
2098
2099 aml_append(scope, dev);
2100 aml_append(dsdt, scope);
2101 }
2102
2103 if (misc->pvpanic_port) {
2104 scope = aml_scope("\\_SB.PCI0.ISA");
2105
2106 dev = aml_device("PEVT");
2107 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2108
2109 crs = aml_resource_template();
2110 aml_append(crs,
2111 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2112 );
2113 aml_append(dev, aml_name_decl("_CRS", crs));
2114
2115 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2116 aml_int(misc->pvpanic_port), 1));
2117 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2118 aml_append(field, aml_named_field("PEPT", 8));
2119 aml_append(dev, field);
2120
2121
2122 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2123
2124 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2125 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2126 aml_append(method, aml_return(aml_local(0)));
2127 aml_append(dev, method);
2128
2129 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2130 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2131 aml_append(dev, method);
2132
2133 aml_append(scope, dev);
2134 aml_append(dsdt, scope);
2135 }
2136
2137 sb_scope = aml_scope("\\_SB");
2138 {
2139 Object *pci_host;
2140 PCIBus *bus = NULL;
2141
2142 pci_host = acpi_get_i386_pci_host();
2143 if (pci_host) {
2144 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2145 }
2146
2147 if (bus) {
2148 Aml *scope = aml_scope("PCI0");
2149
2150 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2151
2152 if (TPM_IS_TIS(tpm)) {
2153 if (misc->tpm_version == TPM_VERSION_2_0) {
2154 dev = aml_device("TPM");
2155 aml_append(dev, aml_name_decl("_HID",
2156 aml_string("MSFT0101")));
2157 } else {
2158 dev = aml_device("ISA.TPM");
2159 aml_append(dev, aml_name_decl("_HID",
2160 aml_eisaid("PNP0C31")));
2161 }
2162
2163 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2164 crs = aml_resource_template();
2165 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2166 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2167
2168
2169
2170
2171
2172
2173 aml_append(dev, aml_name_decl("_CRS", crs));
2174
2175 tpm_build_ppi_acpi(tpm, dev);
2176
2177 aml_append(scope, dev);
2178 }
2179
2180 aml_append(sb_scope, scope);
2181 }
2182 }
2183
2184 if (TPM_IS_CRB(tpm)) {
2185 dev = aml_device("TPM");
2186 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
2187 crs = aml_resource_template();
2188 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
2189 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
2190 aml_append(dev, aml_name_decl("_CRS", crs));
2191
2192 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
2193 aml_append(method, aml_return(aml_int(0x0f)));
2194 aml_append(dev, method);
2195
2196 tpm_build_ppi_acpi(tpm, dev);
2197
2198 aml_append(sb_scope, dev);
2199 }
2200
2201 aml_append(dsdt, sb_scope);
2202
2203
2204 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2205 build_header(linker, table_data,
2206 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2207 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2208 free_aml_allocator();
2209}
2210
2211static void
2212build_hpet(GArray *table_data, BIOSLinker *linker)
2213{
2214 Acpi20Hpet *hpet;
2215
2216 hpet = acpi_data_push(table_data, sizeof(*hpet));
2217
2218
2219
2220 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2221 hpet->addr.address = cpu_to_le64(HPET_BASE);
2222 build_header(linker, table_data,
2223 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2224}
2225
2226static void
2227build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2228{
2229 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2230 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2231 unsigned log_addr_offset =
2232 (char *)&tcpa->log_area_start_address - table_data->data;
2233
2234 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2235 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2236 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2237
2238 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2239 false );
2240
2241
2242 bios_linker_loader_add_pointer(linker,
2243 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2244 ACPI_BUILD_TPMLOG_FILE, 0);
2245
2246 build_header(linker, table_data,
2247 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2248}
2249
2250static void
2251build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2252{
2253 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2254 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
2255 unsigned log_addr_offset =
2256 (char *)&tpm2_ptr->log_area_start_address - table_data->data;
2257
2258 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2259 if (TPM_IS_TIS(tpm_find())) {
2260 tpm2_ptr->control_area_address = cpu_to_le64(0);
2261 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2262 } else if (TPM_IS_CRB(tpm_find())) {
2263 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
2264 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
2265 } else {
2266 g_warn_if_reached();
2267 }
2268
2269 tpm2_ptr->log_area_minimum_length =
2270 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2271
2272
2273 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2274 log_addr_offset, log_addr_size,
2275 ACPI_BUILD_TPMLOG_FILE, 0);
2276 build_header(linker, table_data,
2277 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2278}
2279
2280#define HOLE_640K_START (640 * KiB)
2281#define HOLE_640K_END (1 * MiB)
2282
2283static void
2284build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2285{
2286 AcpiSystemResourceAffinityTable *srat;
2287 AcpiSratMemoryAffinity *numamem;
2288
2289 int i;
2290 int srat_start, numa_start, slots;
2291 uint64_t mem_len, mem_base, next_base;
2292 MachineClass *mc = MACHINE_GET_CLASS(machine);
2293 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2294 PCMachineState *pcms = PC_MACHINE(machine);
2295 ram_addr_t hotplugabble_address_space_size =
2296 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
2297 NULL);
2298
2299 srat_start = table_data->len;
2300
2301 srat = acpi_data_push(table_data, sizeof *srat);
2302 srat->reserved1 = cpu_to_le32(1);
2303
2304 for (i = 0; i < apic_ids->len; i++) {
2305 int node_id = apic_ids->cpus[i].props.node_id;
2306 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2307
2308 if (apic_id < 255) {
2309 AcpiSratProcessorAffinity *core;
2310
2311 core = acpi_data_push(table_data, sizeof *core);
2312 core->type = ACPI_SRAT_PROCESSOR_APIC;
2313 core->length = sizeof(*core);
2314 core->local_apic_id = apic_id;
2315 core->proximity_lo = node_id;
2316 memset(core->proximity_hi, 0, 3);
2317 core->local_sapic_eid = 0;
2318 core->flags = cpu_to_le32(1);
2319 } else {
2320 AcpiSratProcessorX2ApicAffinity *core;
2321
2322 core = acpi_data_push(table_data, sizeof *core);
2323 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2324 core->length = sizeof(*core);
2325 core->x2apic_id = cpu_to_le32(apic_id);
2326 core->proximity_domain = cpu_to_le32(node_id);
2327 core->flags = cpu_to_le32(1);
2328 }
2329 }
2330
2331
2332
2333
2334
2335 next_base = 0;
2336 numa_start = table_data->len;
2337
2338 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2339 mem_base = next_base;
2340 mem_len = pcms->node_mem[i - 1];
2341 next_base = mem_base + mem_len;
2342
2343
2344 if (mem_base <= HOLE_640K_START &&
2345 next_base > HOLE_640K_START) {
2346 mem_len -= next_base - HOLE_640K_START;
2347 if (mem_len > 0) {
2348 numamem = acpi_data_push(table_data, sizeof *numamem);
2349 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2350 MEM_AFFINITY_ENABLED);
2351 }
2352
2353
2354 if (next_base <= HOLE_640K_END) {
2355 next_base = HOLE_640K_END;
2356 continue;
2357 }
2358 mem_base = HOLE_640K_END;
2359 mem_len = next_base - HOLE_640K_END;
2360 }
2361
2362
2363 if (mem_base <= pcms->below_4g_mem_size &&
2364 next_base > pcms->below_4g_mem_size) {
2365 mem_len -= next_base - pcms->below_4g_mem_size;
2366 if (mem_len > 0) {
2367 numamem = acpi_data_push(table_data, sizeof *numamem);
2368 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2369 MEM_AFFINITY_ENABLED);
2370 }
2371 mem_base = 1ULL << 32;
2372 mem_len = next_base - pcms->below_4g_mem_size;
2373 next_base = mem_base + mem_len;
2374 }
2375
2376 if (mem_len > 0) {
2377 numamem = acpi_data_push(table_data, sizeof *numamem);
2378 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2379 MEM_AFFINITY_ENABLED);
2380 }
2381 }
2382 slots = (table_data->len - numa_start) / sizeof *numamem;
2383 for (; slots < pcms->numa_nodes + 2; slots++) {
2384 numamem = acpi_data_push(table_data, sizeof *numamem);
2385 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2386 }
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396 if (hotplugabble_address_space_size) {
2397 numamem = acpi_data_push(table_data, sizeof *numamem);
2398 build_srat_memory(numamem, machine->device_memory->base,
2399 hotplugabble_address_space_size, pcms->numa_nodes - 1,
2400 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2401 }
2402
2403 build_header(linker, table_data,
2404 (void *)(table_data->data + srat_start),
2405 "SRAT",
2406 table_data->len - srat_start, 1, NULL, NULL);
2407}
2408
2409static void
2410build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2411{
2412 AcpiTableMcfg *mcfg;
2413 const char *sig;
2414 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2415
2416 mcfg = acpi_data_push(table_data, len);
2417 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2418
2419 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2420 mcfg->allocation[0].start_bus_number = 0;
2421 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2422
2423
2424
2425
2426
2427
2428
2429 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2430
2431 sig = "QEMU";
2432 } else {
2433 sig = "MCFG";
2434 }
2435 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2436}
2437
2438
2439
2440
2441
2442static void
2443build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2444{
2445 int dmar_start = table_data->len;
2446
2447 AcpiTableDmar *dmar;
2448 AcpiDmarHardwareUnit *drhd;
2449 AcpiDmarRootPortATS *atsr;
2450 uint8_t dmar_flags = 0;
2451 X86IOMMUState *iommu = x86_iommu_get_default();
2452 AcpiDmarDeviceScope *scope = NULL;
2453
2454 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2455 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2456
2457 assert(iommu);
2458 if (x86_iommu_ir_supported(iommu)) {
2459 dmar_flags |= 0x1;
2460 }
2461
2462 dmar = acpi_data_push(table_data, sizeof(*dmar));
2463 dmar->host_address_width = intel_iommu->aw_bits - 1;
2464 dmar->flags = dmar_flags;
2465
2466
2467 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2468 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2469 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2470 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2471 drhd->pci_segment = cpu_to_le16(0);
2472 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2473
2474
2475
2476 scope = &drhd->scope[0];
2477 scope->entry_type = 0x03;
2478 scope->length = ioapic_scope_size;
2479 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2480 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2481 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2482 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2483
2484 if (iommu->dt_supported) {
2485 atsr = acpi_data_push(table_data, sizeof(*atsr));
2486 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2487 atsr->length = cpu_to_le16(sizeof(*atsr));
2488 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2489 atsr->pci_segment = cpu_to_le16(0);
2490 }
2491
2492 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2493 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2494}
2495
2496
2497
2498
2499#define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2500
2501static void
2502build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2503{
2504 int ivhd_table_len = 28;
2505 int iommu_start = table_data->len;
2506 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2507
2508
2509 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2510
2511
2512
2513 build_append_int_noprefix(table_data, 40UL << 8, 4);
2514
2515 build_append_int_noprefix(table_data, 0, 8);
2516
2517
2518 build_append_int_noprefix(table_data, 0x10, 1);
2519
2520 build_append_int_noprefix(table_data,
2521 (1UL << 0) |
2522 (1UL << 4) |
2523 (1UL << 6) |
2524 (1UL << 7),
2525 1);
2526
2527
2528
2529
2530
2531 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2532 ivhd_table_len += 8;
2533 }
2534
2535 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2536
2537 build_append_int_noprefix(table_data, s->devid, 2);
2538
2539 build_append_int_noprefix(table_data, s->capab_offset, 2);
2540
2541 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2542
2543 build_append_int_noprefix(table_data, 0, 2);
2544
2545 build_append_int_noprefix(table_data, 0, 2);
2546
2547 build_append_int_noprefix(table_data,
2548 (48UL << 30) |
2549 (48UL << 28) |
2550 (1UL << 2) |
2551 (1UL << 6),
2552 4);
2553
2554
2555
2556
2557
2558 build_append_int_noprefix(table_data, 0x0000001, 4);
2559
2560
2561
2562
2563
2564
2565
2566
2567 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2568 build_append_int_noprefix(table_data,
2569 (0x1ull << 56) |
2570 (IOAPIC_SB_DEVID << 40) |
2571 0x48,
2572 8);
2573 }
2574
2575 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2576 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2577}
2578
2579typedef
2580struct AcpiBuildState {
2581
2582 MemoryRegion *table_mr;
2583
2584 uint8_t patched;
2585 void *rsdp;
2586 MemoryRegion *rsdp_mr;
2587 MemoryRegion *linker_mr;
2588} AcpiBuildState;
2589
2590static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2591{
2592 Object *pci_host;
2593 QObject *o;
2594
2595 pci_host = acpi_get_i386_pci_host();
2596 g_assert(pci_host);
2597
2598 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2599 if (!o) {
2600 return false;
2601 }
2602 mcfg->mcfg_base = qnum_get_uint(qobject_to(QNum, o));
2603 qobject_unref(o);
2604
2605 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2606 assert(o);
2607 mcfg->mcfg_size = qnum_get_uint(qobject_to(QNum, o));
2608 qobject_unref(o);
2609 return true;
2610}
2611
2612static
2613void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2614{
2615 PCMachineState *pcms = PC_MACHINE(machine);
2616 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2617 GArray *table_offsets;
2618 unsigned facs, dsdt, rsdt, fadt;
2619 AcpiPmInfo pm;
2620 AcpiMiscInfo misc;
2621 AcpiMcfgInfo mcfg;
2622 Range pci_hole, pci_hole64;
2623 uint8_t *u;
2624 size_t aml_len = 0;
2625 GArray *tables_blob = tables->table_data;
2626 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2627 Object *vmgenid_dev;
2628
2629 acpi_get_pm_info(&pm);
2630 acpi_get_misc_info(&misc);
2631 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2632 acpi_get_slic_oem(&slic_oem);
2633
2634 table_offsets = g_array_new(false, true ,
2635 sizeof(uint32_t));
2636 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2637
2638 bios_linker_loader_alloc(tables->linker,
2639 ACPI_BUILD_TABLE_FILE, tables_blob,
2640 64 ,
2641 false );
2642
2643
2644
2645
2646
2647
2648 facs = tables_blob->len;
2649 build_facs(tables_blob);
2650
2651
2652 dsdt = tables_blob->len;
2653 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2654 &pci_hole, &pci_hole64, machine);
2655
2656
2657
2658
2659 aml_len += tables_blob->len - dsdt;
2660
2661
2662 fadt = tables_blob->len;
2663 acpi_add_table(table_offsets, tables_blob);
2664 pm.fadt.facs_tbl_offset = &facs;
2665 pm.fadt.dsdt_tbl_offset = &dsdt;
2666 pm.fadt.xdsdt_tbl_offset = &dsdt;
2667 build_fadt(tables_blob, tables->linker, &pm.fadt,
2668 slic_oem.id, slic_oem.table_id);
2669 aml_len += tables_blob->len - fadt;
2670
2671 acpi_add_table(table_offsets, tables_blob);
2672 build_madt(tables_blob, tables->linker, pcms);
2673
2674 vmgenid_dev = find_vmgenid_dev();
2675 if (vmgenid_dev) {
2676 acpi_add_table(table_offsets, tables_blob);
2677 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2678 tables->vmgenid, tables->linker);
2679 }
2680
2681 if (misc.has_hpet) {
2682 acpi_add_table(table_offsets, tables_blob);
2683 build_hpet(tables_blob, tables->linker);
2684 }
2685 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2686 acpi_add_table(table_offsets, tables_blob);
2687 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2688
2689 if (misc.tpm_version == TPM_VERSION_2_0) {
2690 acpi_add_table(table_offsets, tables_blob);
2691 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
2692 }
2693 }
2694 if (pcms->numa_nodes) {
2695 acpi_add_table(table_offsets, tables_blob);
2696 build_srat(tables_blob, tables->linker, machine);
2697 if (have_numa_distance) {
2698 acpi_add_table(table_offsets, tables_blob);
2699 build_slit(tables_blob, tables->linker);
2700 }
2701 }
2702 if (acpi_get_mcfg(&mcfg)) {
2703 acpi_add_table(table_offsets, tables_blob);
2704 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2705 }
2706 if (x86_iommu_get_default()) {
2707 IommuType IOMMUType = x86_iommu_get_type();
2708 if (IOMMUType == TYPE_AMD) {
2709 acpi_add_table(table_offsets, tables_blob);
2710 build_amd_iommu(tables_blob, tables->linker);
2711 } else if (IOMMUType == TYPE_INTEL) {
2712 acpi_add_table(table_offsets, tables_blob);
2713 build_dmar_q35(tables_blob, tables->linker);
2714 }
2715 }
2716 if (machine->nvdimms_state->is_enabled) {
2717 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2718 machine->nvdimms_state, machine->ram_slots);
2719 }
2720
2721
2722 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2723 unsigned len = acpi_table_len(u);
2724
2725 acpi_add_table(table_offsets, tables_blob);
2726 g_array_append_vals(tables_blob, u, len);
2727 }
2728
2729
2730 rsdt = tables_blob->len;
2731 build_rsdt(tables_blob, tables->linker, table_offsets,
2732 slic_oem.id, slic_oem.table_id);
2733
2734
2735 {
2736 AcpiRsdpData rsdp_data = {
2737 .revision = 0,
2738 .oem_id = ACPI_BUILD_APPNAME6,
2739 .xsdt_tbl_offset = NULL,
2740 .rsdt_tbl_offset = &rsdt,
2741 };
2742 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2743 if (!pcmc->rsdp_in_ram) {
2744
2745
2746
2747
2748
2749
2750
2751 build_append_int_noprefix(tables->rsdp, 0, 16);
2752 }
2753 }
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772 if (pcmc->legacy_acpi_table_size) {
2773
2774
2775
2776 int legacy_aml_len =
2777 pcmc->legacy_acpi_table_size +
2778 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit;
2779 int legacy_table_size =
2780 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2781 ACPI_BUILD_ALIGN_SIZE);
2782 if (tables_blob->len > legacy_table_size) {
2783
2784 warn_report("ACPI table size %u exceeds %d bytes,"
2785 " migration may not work",
2786 tables_blob->len, legacy_table_size);
2787 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2788 " or PCI bridges.");
2789 }
2790 g_array_set_size(tables_blob, legacy_table_size);
2791 } else {
2792
2793 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2794
2795 warn_report("ACPI table size %u exceeds %d bytes,"
2796 " migration may not work",
2797 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2798 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2799 " or PCI bridges.");
2800 }
2801 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2802 }
2803
2804 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2805
2806
2807 g_array_free(table_offsets, true);
2808}
2809
2810static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2811{
2812 uint32_t size = acpi_data_len(data);
2813
2814
2815 memory_region_ram_resize(mr, size, &error_abort);
2816
2817 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2818 memory_region_set_dirty(mr, 0, size);
2819}
2820
2821static void acpi_build_update(void *build_opaque)
2822{
2823 AcpiBuildState *build_state = build_opaque;
2824 AcpiBuildTables tables;
2825
2826
2827 if (!build_state || build_state->patched) {
2828 return;
2829 }
2830 build_state->patched = 1;
2831
2832 acpi_build_tables_init(&tables);
2833
2834 acpi_build(&tables, MACHINE(qdev_get_machine()));
2835
2836 acpi_ram_update(build_state->table_mr, tables.table_data);
2837
2838 if (build_state->rsdp) {
2839 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2840 } else {
2841 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2842 }
2843
2844 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2845 acpi_build_tables_cleanup(&tables, true);
2846}
2847
2848static void acpi_build_reset(void *build_opaque)
2849{
2850 AcpiBuildState *build_state = build_opaque;
2851 build_state->patched = 0;
2852}
2853
2854static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2855 GArray *blob, const char *name,
2856 uint64_t max_size)
2857{
2858 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2859 name, acpi_build_update, build_state, NULL, true);
2860}
2861
2862static const VMStateDescription vmstate_acpi_build = {
2863 .name = "acpi_build",
2864 .version_id = 1,
2865 .minimum_version_id = 1,
2866 .fields = (VMStateField[]) {
2867 VMSTATE_UINT8(patched, AcpiBuildState),
2868 VMSTATE_END_OF_LIST()
2869 },
2870};
2871
2872void acpi_setup(void)
2873{
2874 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2875 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2876 AcpiBuildTables tables;
2877 AcpiBuildState *build_state;
2878 Object *vmgenid_dev;
2879 TPMIf *tpm;
2880 static FwCfgTPMConfig tpm_config;
2881
2882 if (!pcms->fw_cfg) {
2883 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2884 return;
2885 }
2886
2887 if (!pcms->acpi_build_enabled) {
2888 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2889 return;
2890 }
2891
2892 if (!acpi_enabled) {
2893 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2894 return;
2895 }
2896
2897 build_state = g_malloc0(sizeof *build_state);
2898
2899 acpi_build_tables_init(&tables);
2900 acpi_build(&tables, MACHINE(pcms));
2901
2902
2903 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2904 ACPI_BUILD_TABLE_FILE,
2905 ACPI_BUILD_TABLE_MAX_SIZE);
2906 assert(build_state->table_mr != NULL);
2907
2908 build_state->linker_mr =
2909 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2910 "etc/table-loader", 0);
2911
2912 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2913 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2914
2915 tpm = tpm_find();
2916 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2917 tpm_config = (FwCfgTPMConfig) {
2918 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2919 .tpm_version = tpm_get_version(tpm),
2920 .tpmppi_version = TPM_PPI_VERSION_1_30
2921 };
2922 fw_cfg_add_file(pcms->fw_cfg, "etc/tpm/config",
2923 &tpm_config, sizeof tpm_config);
2924 }
2925
2926 vmgenid_dev = find_vmgenid_dev();
2927 if (vmgenid_dev) {
2928 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg,
2929 tables.vmgenid);
2930 }
2931
2932 if (!pcmc->rsdp_in_ram) {
2933
2934
2935
2936
2937
2938 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2939
2940 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2941 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2942 acpi_build_update, NULL, build_state,
2943 build_state->rsdp, rsdp_size, true);
2944 build_state->rsdp_mr = NULL;
2945 } else {
2946 build_state->rsdp = NULL;
2947 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2948 ACPI_BUILD_RSDP_FILE, 0);
2949 }
2950
2951 qemu_register_reset(acpi_build_reset, build_state);
2952 acpi_build_reset(build_state);
2953 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2954
2955
2956
2957
2958 acpi_build_tables_cleanup(&tables, false);
2959}
2960