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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/pci/pci.h"
28#include "hw/isa/isa.h"
29#include "sysemu/sysemu.h"
30#include "sysemu/dma.h"
31
32#include "hw/ide/pci.h"
33#include "trace.h"
34
35
36#define CFR 0x50
37#define CFR_INTR_CH0 0x04
38#define CNTRL 0x51
39#define CNTRL_EN_CH0 0x04
40#define CNTRL_EN_CH1 0x08
41#define ARTTIM23 0x57
42#define ARTTIM23_INTR_CH1 0x10
43#define MRDMODE 0x71
44#define MRDMODE_INTR_CH0 0x04
45#define MRDMODE_INTR_CH1 0x08
46#define MRDMODE_BLK_CH0 0x10
47#define MRDMODE_BLK_CH1 0x20
48#define UDIDETCR0 0x73
49#define UDIDETCR1 0x7B
50
51static void cmd646_update_irq(PCIDevice *pd);
52
53static void cmd646_update_dma_interrupts(PCIDevice *pd)
54{
55
56 if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
57 pd->config[CFR] |= CFR_INTR_CH0;
58 } else {
59 pd->config[CFR] &= ~CFR_INTR_CH0;
60 }
61
62 if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
63 pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
64 } else {
65 pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
66 }
67}
68
69static void cmd646_update_udma_interrupts(PCIDevice *pd)
70{
71
72 if (pd->config[CFR] & CFR_INTR_CH0) {
73 pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
74 } else {
75 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
76 }
77
78 if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
79 pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
80 } else {
81 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
82 }
83}
84
85static uint64_t bmdma_read(void *opaque, hwaddr addr,
86 unsigned size)
87{
88 BMDMAState *bm = opaque;
89 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
90 uint32_t val;
91
92 if (size != 1) {
93 return ((uint64_t)1 << (size * 8)) - 1;
94 }
95
96 switch(addr & 3) {
97 case 0:
98 val = bm->cmd;
99 break;
100 case 1:
101 val = pci_dev->config[MRDMODE];
102 break;
103 case 2:
104 val = bm->status;
105 break;
106 case 3:
107 if (bm == &bm->pci_dev->bmdma[0]) {
108 val = pci_dev->config[UDIDETCR0];
109 } else {
110 val = pci_dev->config[UDIDETCR1];
111 }
112 break;
113 default:
114 val = 0xff;
115 break;
116 }
117
118 trace_bmdma_read_cmd646(addr, val);
119 return val;
120}
121
122static void bmdma_write(void *opaque, hwaddr addr,
123 uint64_t val, unsigned size)
124{
125 BMDMAState *bm = opaque;
126 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
127
128 if (size != 1) {
129 return;
130 }
131
132 trace_bmdma_write_cmd646(addr, val);
133 switch(addr & 3) {
134 case 0:
135 bmdma_cmd_writeb(bm, val);
136 break;
137 case 1:
138 pci_dev->config[MRDMODE] =
139 (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
140 cmd646_update_dma_interrupts(pci_dev);
141 cmd646_update_irq(pci_dev);
142 break;
143 case 2:
144 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
145 break;
146 case 3:
147 if (bm == &bm->pci_dev->bmdma[0]) {
148 pci_dev->config[UDIDETCR0] = val;
149 } else {
150 pci_dev->config[UDIDETCR1] = val;
151 }
152 break;
153 }
154}
155
156static const MemoryRegionOps cmd646_bmdma_ops = {
157 .read = bmdma_read,
158 .write = bmdma_write,
159};
160
161static void bmdma_setup_bar(PCIIDEState *d)
162{
163 BMDMAState *bm;
164 int i;
165
166 memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
167 for(i = 0;i < 2; i++) {
168 bm = &d->bmdma[i];
169 memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
170 "cmd646-bmdma-bus", 4);
171 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
172 memory_region_init_io(&bm->addr_ioport, OBJECT(d),
173 &bmdma_addr_ioport_ops, bm,
174 "cmd646-bmdma-ioport", 4);
175 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
176 }
177}
178
179static void cmd646_update_irq(PCIDevice *pd)
180{
181 int pci_level;
182
183 pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
184 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
185 ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
186 !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
187 pci_set_irq(pd, pci_level);
188}
189
190
191static void cmd646_set_irq(void *opaque, int channel, int level)
192{
193 PCIIDEState *d = opaque;
194 PCIDevice *pd = PCI_DEVICE(d);
195 int irq_mask;
196
197 irq_mask = MRDMODE_INTR_CH0 << channel;
198 if (level) {
199 pd->config[MRDMODE] |= irq_mask;
200 } else {
201 pd->config[MRDMODE] &= ~irq_mask;
202 }
203 cmd646_update_dma_interrupts(pd);
204 cmd646_update_irq(pd);
205}
206
207static void cmd646_reset(void *opaque)
208{
209 PCIIDEState *d = opaque;
210 unsigned int i;
211
212 for (i = 0; i < 2; i++) {
213 ide_bus_reset(&d->bus[i]);
214 }
215}
216
217static uint32_t cmd646_pci_config_read(PCIDevice *d,
218 uint32_t address, int len)
219{
220 return pci_default_read_config(d, address, len);
221}
222
223static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
224 int l)
225{
226 uint32_t i;
227
228 pci_default_write_config(d, addr, val, l);
229
230 for (i = addr; i < addr + l; i++) {
231 switch (i) {
232 case CFR:
233 case ARTTIM23:
234 cmd646_update_udma_interrupts(d);
235 break;
236 case MRDMODE:
237 cmd646_update_dma_interrupts(d);
238 break;
239 }
240 }
241
242 cmd646_update_irq(d);
243}
244
245
246static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
247{
248 PCIIDEState *d = PCI_IDE(dev);
249 uint8_t *pci_conf = dev->config;
250 qemu_irq *irq;
251 int i;
252
253 pci_conf[PCI_CLASS_PROG] = 0x8f;
254
255 pci_conf[CNTRL] = CNTRL_EN_CH0;
256 if (d->secondary) {
257
258 pci_conf[CNTRL] |= CNTRL_EN_CH1;
259 }
260
261
262 dev->wmask[CFR] = 0x0;
263 dev->w1cmask[CFR] = CFR_INTR_CH0;
264 dev->wmask[ARTTIM23] = 0x0;
265 dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
266 dev->wmask[MRDMODE] = 0x0;
267 dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;
268
269 memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
270 &d->bus[0], "cmd646-data0", 8);
271 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);
272
273 memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
274 &d->bus[0], "cmd646-cmd0", 4);
275 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);
276
277 memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
278 &d->bus[1], "cmd646-data1", 8);
279 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
280
281 memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
282 &d->bus[1], "cmd646-cmd1", 4);
283 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
284
285 bmdma_setup_bar(d);
286 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
287
288
289 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
290
291 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
292 for (i = 0; i < 2; i++) {
293 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
294 ide_init2(&d->bus[i], irq[i]);
295
296 bmdma_init(&d->bus[i], &d->bmdma[i], d);
297 d->bmdma[i].bus = &d->bus[i];
298 ide_register_restart_cb(&d->bus[i]);
299 }
300
301 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
302 qemu_register_reset(cmd646_reset, d);
303}
304
305static void pci_cmd646_ide_exitfn(PCIDevice *dev)
306{
307 PCIIDEState *d = PCI_IDE(dev);
308 unsigned i;
309
310 for (i = 0; i < 2; ++i) {
311 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
312 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
313 }
314}
315
316void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
317 int secondary_ide_enabled)
318{
319 PCIDevice *dev;
320
321 dev = pci_create(bus, -1, "cmd646-ide");
322 qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
323 qdev_init_nofail(&dev->qdev);
324
325 pci_ide_create_devs(dev, hd_table);
326}
327
328static Property cmd646_ide_properties[] = {
329 DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
330 DEFINE_PROP_END_OF_LIST(),
331};
332
333static void cmd646_ide_class_init(ObjectClass *klass, void *data)
334{
335 DeviceClass *dc = DEVICE_CLASS(klass);
336 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
337
338 k->realize = pci_cmd646_ide_realize;
339 k->exit = pci_cmd646_ide_exitfn;
340 k->vendor_id = PCI_VENDOR_ID_CMD;
341 k->device_id = PCI_DEVICE_ID_CMD_646;
342 k->revision = 0x07;
343 k->class_id = PCI_CLASS_STORAGE_IDE;
344 k->config_read = cmd646_pci_config_read;
345 k->config_write = cmd646_pci_config_write;
346 dc->props = cmd646_ide_properties;
347 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
348}
349
350static const TypeInfo cmd646_ide_info = {
351 .name = "cmd646-ide",
352 .parent = TYPE_PCI_IDE,
353 .class_init = cmd646_ide_class_init,
354};
355
356static void cmd646_ide_register_types(void)
357{
358 type_register_static(&cmd646_ide_info);
359}
360
361type_init(cmd646_ide_register_types)
362
