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11
12#include "qemu/osdep.h"
13#include "qemu/log.h"
14#include "trace.h"
15#include "gicv3_internal.h"
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32typedef uint32_t maskfn(GICv3State *s, int irq);
33
34static uint32_t mask_nsacr_ge1(GICv3State *s, int irq)
35{
36
37 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1];
38
39 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16];
40 raw_nsacr = (raw_nsacr >> 1) | raw_nsacr;
41 return half_unshuffle64(raw_nsacr);
42}
43
44static uint32_t mask_nsacr_ge2(GICv3State *s, int irq)
45{
46
47 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1];
48
49 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16];
50 raw_nsacr = raw_nsacr >> 1;
51 return half_unshuffle64(raw_nsacr);
52}
53
54
55
56
57
58
59static uint32_t mask_group_and_nsacr(GICv3State *s, MemTxAttrs attrs,
60 maskfn *maskfn, int irq)
61{
62
63
64
65
66 uint32_t mask;
67
68 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
69
70
71
72 mask = *gic_bmp_ptr32(s->group, irq);
73 if (maskfn) {
74 mask |= maskfn(s, irq);
75 }
76 return mask;
77 }
78 return 0xFFFFFFFFU;
79}
80
81static int gicd_ns_access(GICv3State *s, int irq)
82{
83
84
85
86 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
87 return 0;
88 }
89 return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2);
90}
91
92static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
93 uint32_t *bmp,
94 maskfn *maskfn,
95 int offset, uint32_t val)
96{
97
98
99
100
101
102
103
104
105
106 int irq = offset * 8;
107
108 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
109 return;
110 }
111 val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
112 *gic_bmp_ptr32(bmp, irq) |= val;
113 gicv3_update(s, irq, 32);
114}
115
116static void gicd_write_clear_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
117 uint32_t *bmp,
118 maskfn *maskfn,
119 int offset, uint32_t val)
120{
121
122
123
124
125
126
127
128
129
130 int irq = offset * 8;
131
132 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
133 return;
134 }
135 val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
136 *gic_bmp_ptr32(bmp, irq) &= ~val;
137 gicv3_update(s, irq, 32);
138}
139
140static uint32_t gicd_read_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
141 uint32_t *bmp,
142 maskfn *maskfn,
143 int offset)
144{
145
146
147
148
149
150
151
152
153 int irq = offset * 8;
154 uint32_t val;
155
156 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
157 return 0;
158 }
159 val = *gic_bmp_ptr32(bmp, irq);
160 if (bmp == s->pending) {
161
162
163
164
165 uint32_t edge = *gic_bmp_ptr32(s->edge_trigger, irq);
166 uint32_t level = *gic_bmp_ptr32(s->level, irq);
167 val |= (~edge & level);
168 }
169 val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
170 return val;
171}
172
173static uint8_t gicd_read_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq)
174{
175
176
177
178
179 uint32_t prio;
180
181 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
182 return 0;
183 }
184
185 prio = s->gicd_ipriority[irq];
186
187 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
188 if (!gicv3_gicd_group_test(s, irq)) {
189
190 return 0;
191 }
192
193 prio = (prio << 1) & 0xff;
194 }
195 return prio;
196}
197
198static void gicd_write_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq,
199 uint8_t value)
200{
201
202
203
204
205 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
206 return;
207 }
208
209 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
210 if (!gicv3_gicd_group_test(s, irq)) {
211
212 return;
213 }
214
215 value = 0x80 | (value >> 1);
216 }
217 s->gicd_ipriority[irq] = value;
218}
219
220static uint64_t gicd_read_irouter(GICv3State *s, MemTxAttrs attrs, int irq)
221{
222
223
224
225 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
226 return 0;
227 }
228
229 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
230
231 if (!gicv3_gicd_group_test(s, irq)) {
232 if (gicd_ns_access(s, irq) != 3) {
233 return 0;
234 }
235 }
236 }
237
238 return s->gicd_irouter[irq];
239}
240
241static void gicd_write_irouter(GICv3State *s, MemTxAttrs attrs, int irq,
242 uint64_t val)
243{
244
245
246
247 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
248 return;
249 }
250
251 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
252
253 if (!gicv3_gicd_group_test(s, irq)) {
254 if (gicd_ns_access(s, irq) != 3) {
255 return;
256 }
257 }
258 }
259
260 s->gicd_irouter[irq] = val;
261 gicv3_cache_target_cpustate(s, irq);
262 gicv3_update(s, irq, 1);
263}
264
265static MemTxResult gicd_readb(GICv3State *s, hwaddr offset,
266 uint64_t *data, MemTxAttrs attrs)
267{
268
269 switch (offset) {
270 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
271 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
272 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
273
274
275
276 return MEMTX_OK;
277 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
278 *data = gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR);
279 return MEMTX_OK;
280 default:
281 return MEMTX_ERROR;
282 }
283}
284
285static MemTxResult gicd_writeb(GICv3State *s, hwaddr offset,
286 uint64_t value, MemTxAttrs attrs)
287{
288
289 switch (offset) {
290 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
291 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
292 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
293
294
295
296 return MEMTX_OK;
297 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
298 {
299 int irq = offset - GICD_IPRIORITYR;
300
301 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
302 return MEMTX_OK;
303 }
304 gicd_write_ipriorityr(s, attrs, irq, value);
305 gicv3_update(s, irq, 1);
306 return MEMTX_OK;
307 }
308 default:
309 return MEMTX_ERROR;
310 }
311}
312
313static MemTxResult gicd_readw(GICv3State *s, hwaddr offset,
314 uint64_t *data, MemTxAttrs attrs)
315{
316
317
318
319
320
321
322 return MEMTX_ERROR;
323}
324
325static MemTxResult gicd_writew(GICv3State *s, hwaddr offset,
326 uint64_t value, MemTxAttrs attrs)
327{
328
329
330
331
332
333
334 return MEMTX_ERROR;
335}
336
337static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
338 uint64_t *data, MemTxAttrs attrs)
339{
340
341
342
343
344
345 switch (offset) {
346 case GICD_CTLR:
347 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
348
349
350
351
352
353
354
355
356
357
358
359
360 *data = s->gicd_ctlr & (GICD_CTLR_ARE_S |
361 GICD_CTLR_EN_GRP1NS |
362 GICD_CTLR_RWP);
363 } else {
364 *data = s->gicd_ctlr;
365 }
366 return MEMTX_OK;
367 case GICD_TYPER:
368 {
369
370
371
372
373
374
375
376
377
378
379
380 int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1;
381
382 *data = (1 << 25) | (1 << 24) | (s->security_extn << 10) |
383 (0xf << 19) | itlinesnumber;
384 return MEMTX_OK;
385 }
386 case GICD_IIDR:
387
388
389
390 *data = gicv3_iidr();
391 return MEMTX_OK;
392 case GICD_STATUSR:
393
394
395
396 *data = 0;
397 return MEMTX_OK;
398 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f:
399 {
400 int irq;
401
402 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
403 *data = 0;
404 return MEMTX_OK;
405 }
406
407 irq = (offset - GICD_IGROUPR) * 8;
408 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
409 *data = 0;
410 return MEMTX_OK;
411 }
412 *data = *gic_bmp_ptr32(s->group, irq);
413 return MEMTX_OK;
414 }
415 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f:
416 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL,
417 offset - GICD_ISENABLER);
418 return MEMTX_OK;
419 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f:
420 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL,
421 offset - GICD_ICENABLER);
422 return MEMTX_OK;
423 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f:
424 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1,
425 offset - GICD_ISPENDR);
426 return MEMTX_OK;
427 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f:
428 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2,
429 offset - GICD_ICPENDR);
430 return MEMTX_OK;
431 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f:
432 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2,
433 offset - GICD_ISACTIVER);
434 return MEMTX_OK;
435 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f:
436 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2,
437 offset - GICD_ICACTIVER);
438 return MEMTX_OK;
439 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
440 {
441 int i, irq = offset - GICD_IPRIORITYR;
442 uint32_t value = 0;
443
444 for (i = irq + 3; i >= irq; i--) {
445 value <<= 8;
446 value |= gicd_read_ipriorityr(s, attrs, i);
447 }
448 *data = value;
449 return MEMTX_OK;
450 }
451 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
452
453 *data = 0;
454 return MEMTX_OK;
455 case GICD_ICFGR ... GICD_ICFGR + 0xff:
456 {
457
458 int irq = (offset - GICD_ICFGR) * 4;
459 uint32_t value = 0;
460
461 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
462 *data = 0;
463 return MEMTX_OK;
464 }
465
466
467
468
469
470 value = *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f);
471 value &= mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f);
472 value = extract32(value, (irq & 0x1f) ? 16 : 0, 16);
473 value = half_shuffle32(value) << 1;
474 *data = value;
475 return MEMTX_OK;
476 }
477 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff:
478 {
479 int irq;
480
481 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
482
483
484
485 *data = 0;
486 return MEMTX_OK;
487 }
488
489 irq = (offset - GICD_IGRPMODR) * 8;
490 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
491 *data = 0;
492 return MEMTX_OK;
493 }
494 *data = *gic_bmp_ptr32(s->grpmod, irq);
495 return MEMTX_OK;
496 }
497 case GICD_NSACR ... GICD_NSACR + 0xff:
498 {
499
500 int irq = (offset - GICD_NSACR) * 4;
501
502 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
503 *data = 0;
504 return MEMTX_OK;
505 }
506
507 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
508
509
510
511 *data = 0;
512 return MEMTX_OK;
513 }
514
515 *data = s->gicd_nsacr[irq / 16];
516 return MEMTX_OK;
517 }
518 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
519 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
520
521 *data = 0;
522 return MEMTX_OK;
523 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
524 {
525 uint64_t r;
526 int irq = (offset - GICD_IROUTER) / 8;
527
528 r = gicd_read_irouter(s, attrs, irq);
529 if (offset & 7) {
530 *data = r >> 32;
531 } else {
532 *data = (uint32_t)r;
533 }
534 return MEMTX_OK;
535 }
536 case GICD_IDREGS ... GICD_IDREGS + 0x1f:
537
538 *data = gicv3_idreg(offset - GICD_IDREGS);
539 return MEMTX_OK;
540 case GICD_SGIR:
541
542 qemu_log_mask(LOG_GUEST_ERROR,
543 "%s: invalid guest read from WO register at offset "
544 TARGET_FMT_plx "\n", __func__, offset);
545 *data = 0;
546 return MEMTX_OK;
547 default:
548 return MEMTX_ERROR;
549 }
550}
551
552static MemTxResult gicd_writel(GICv3State *s, hwaddr offset,
553 uint64_t value, MemTxAttrs attrs)
554{
555
556
557
558
559 switch (offset) {
560 case GICD_CTLR:
561 {
562 uint32_t mask;
563
564 if (s->gicd_ctlr & GICD_CTLR_DS) {
565
566
567
568
569 mask = GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1NS;
570 } else {
571 if (attrs.secure) {
572
573
574
575
576
577
578 mask = GICD_CTLR_DS | GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1_ALL;
579 } else {
580
581
582
583
584 mask = GICD_CTLR_EN_GRP1NS;
585 }
586 }
587 s->gicd_ctlr = (s->gicd_ctlr & ~mask) | (value & mask);
588 if (value & mask & GICD_CTLR_DS) {
589
590
591
592
593
594 s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS);
595 }
596 gicv3_full_update(s);
597 return MEMTX_OK;
598 }
599 case GICD_STATUSR:
600
601 return MEMTX_OK;
602 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f:
603 {
604 int irq;
605
606 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
607 return MEMTX_OK;
608 }
609
610 irq = (offset - GICD_IGROUPR) * 8;
611 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
612 return MEMTX_OK;
613 }
614 *gic_bmp_ptr32(s->group, irq) = value;
615 gicv3_update(s, irq, 32);
616 return MEMTX_OK;
617 }
618 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f:
619 gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL,
620 offset - GICD_ISENABLER, value);
621 return MEMTX_OK;
622 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f:
623 gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL,
624 offset - GICD_ICENABLER, value);
625 return MEMTX_OK;
626 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f:
627 gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1,
628 offset - GICD_ISPENDR, value);
629 return MEMTX_OK;
630 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f:
631 gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2,
632 offset - GICD_ICPENDR, value);
633 return MEMTX_OK;
634 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f:
635 gicd_write_set_bitmap_reg(s, attrs, s->active, NULL,
636 offset - GICD_ISACTIVER, value);
637 return MEMTX_OK;
638 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f:
639 gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL,
640 offset - GICD_ICACTIVER, value);
641 return MEMTX_OK;
642 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
643 {
644 int i, irq = offset - GICD_IPRIORITYR;
645
646 if (irq < GIC_INTERNAL || irq + 3 >= s->num_irq) {
647 return MEMTX_OK;
648 }
649
650 for (i = irq; i < irq + 4; i++, value >>= 8) {
651 gicd_write_ipriorityr(s, attrs, i, value);
652 }
653 gicv3_update(s, irq, 4);
654 return MEMTX_OK;
655 }
656 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
657
658 return MEMTX_OK;
659 case GICD_ICFGR ... GICD_ICFGR + 0xff:
660 {
661
662 int irq = (offset - GICD_ICFGR) * 4;
663 uint32_t mask, oldval;
664
665 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
666 return MEMTX_OK;
667 }
668
669
670
671
672
673 value = half_unshuffle32(value >> 1);
674 mask = mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f);
675 if (irq & 0x1f) {
676 value <<= 16;
677 mask &= 0xffff0000U;
678 } else {
679 mask &= 0xffff;
680 }
681 oldval = *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f));
682 value = (oldval & ~mask) | (value & mask);
683 *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) = value;
684 return MEMTX_OK;
685 }
686 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff:
687 {
688 int irq;
689
690 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
691
692
693
694 return MEMTX_OK;
695 }
696
697 irq = (offset - GICD_IGRPMODR) * 8;
698 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
699 return MEMTX_OK;
700 }
701 *gic_bmp_ptr32(s->grpmod, irq) = value;
702 gicv3_update(s, irq, 32);
703 return MEMTX_OK;
704 }
705 case GICD_NSACR ... GICD_NSACR + 0xff:
706 {
707
708 int irq = (offset - GICD_NSACR) * 4;
709
710 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
711 return MEMTX_OK;
712 }
713
714 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
715
716
717
718 return MEMTX_OK;
719 }
720
721 s->gicd_nsacr[irq / 16] = value;
722
723 return MEMTX_OK;
724 }
725 case GICD_SGIR:
726
727 return MEMTX_OK;
728 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
729 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
730
731 return MEMTX_OK;
732 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
733 {
734 uint64_t r;
735 int irq = (offset - GICD_IROUTER) / 8;
736
737 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
738 return MEMTX_OK;
739 }
740
741
742 r = gicd_read_irouter(s, attrs, irq);
743 r = deposit64(r, (offset & 7) ? 32 : 0, 32, value);
744 gicd_write_irouter(s, attrs, irq, r);
745 return MEMTX_OK;
746 }
747 case GICD_IDREGS ... GICD_IDREGS + 0x1f:
748 case GICD_TYPER:
749 case GICD_IIDR:
750
751 qemu_log_mask(LOG_GUEST_ERROR,
752 "%s: invalid guest write to RO register at offset "
753 TARGET_FMT_plx "\n", __func__, offset);
754 return MEMTX_OK;
755 default:
756 return MEMTX_ERROR;
757 }
758}
759
760static MemTxResult gicd_writell(GICv3State *s, hwaddr offset,
761 uint64_t value, MemTxAttrs attrs)
762{
763
764 int irq;
765
766 switch (offset) {
767 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
768 irq = (offset - GICD_IROUTER) / 8;
769 gicd_write_irouter(s, attrs, irq, value);
770 return MEMTX_OK;
771 default:
772 return MEMTX_ERROR;
773 }
774}
775
776static MemTxResult gicd_readll(GICv3State *s, hwaddr offset,
777 uint64_t *data, MemTxAttrs attrs)
778{
779
780 int irq;
781
782 switch (offset) {
783 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
784 irq = (offset - GICD_IROUTER) / 8;
785 *data = gicd_read_irouter(s, attrs, irq);
786 return MEMTX_OK;
787 default:
788 return MEMTX_ERROR;
789 }
790}
791
792MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data,
793 unsigned size, MemTxAttrs attrs)
794{
795 GICv3State *s = (GICv3State *)opaque;
796 MemTxResult r;
797
798 switch (size) {
799 case 1:
800 r = gicd_readb(s, offset, data, attrs);
801 break;
802 case 2:
803 r = gicd_readw(s, offset, data, attrs);
804 break;
805 case 4:
806 r = gicd_readl(s, offset, data, attrs);
807 break;
808 case 8:
809 r = gicd_readll(s, offset, data, attrs);
810 break;
811 default:
812 r = MEMTX_ERROR;
813 break;
814 }
815
816 if (r == MEMTX_ERROR) {
817 qemu_log_mask(LOG_GUEST_ERROR,
818 "%s: invalid guest read at offset " TARGET_FMT_plx
819 "size %u\n", __func__, offset, size);
820 trace_gicv3_dist_badread(offset, size, attrs.secure);
821
822
823
824
825
826 r = MEMTX_OK;
827 *data = 0;
828 } else {
829 trace_gicv3_dist_read(offset, *data, size, attrs.secure);
830 }
831 return r;
832}
833
834MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data,
835 unsigned size, MemTxAttrs attrs)
836{
837 GICv3State *s = (GICv3State *)opaque;
838 MemTxResult r;
839
840 switch (size) {
841 case 1:
842 r = gicd_writeb(s, offset, data, attrs);
843 break;
844 case 2:
845 r = gicd_writew(s, offset, data, attrs);
846 break;
847 case 4:
848 r = gicd_writel(s, offset, data, attrs);
849 break;
850 case 8:
851 r = gicd_writell(s, offset, data, attrs);
852 break;
853 default:
854 r = MEMTX_ERROR;
855 break;
856 }
857
858 if (r == MEMTX_ERROR) {
859 qemu_log_mask(LOG_GUEST_ERROR,
860 "%s: invalid guest write at offset " TARGET_FMT_plx
861 "size %u\n", __func__, offset, size);
862 trace_gicv3_dist_badwrite(offset, data, size, attrs.secure);
863
864
865
866
867
868 r = MEMTX_OK;
869 } else {
870 trace_gicv3_dist_write(offset, data, size, attrs.secure);
871 }
872 return r;
873}
874
875void gicv3_dist_set_irq(GICv3State *s, int irq, int level)
876{
877
878 if (level == gicv3_gicd_level_test(s, irq)) {
879 return;
880 }
881
882 trace_gicv3_dist_set_irq(irq, level);
883
884 gicv3_gicd_level_replace(s, irq, level);
885
886 if (level) {
887
888 if (gicv3_gicd_edge_trigger_test(s, irq)) {
889 gicv3_gicd_pending_set(s, irq);
890 }
891 }
892
893 gicv3_update(s, irq, 1);
894}
895