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23#include "qemu/osdep.h"
24#include "qapi/error.h"
25#include "monitor/monitor.h"
26#include "hw/hw.h"
27#include "hw/i386/pc.h"
28#include "hw/i386/apic.h"
29#include "hw/i386/ioapic.h"
30#include "hw/i386/ioapic_internal.h"
31#include "hw/pci/msi.h"
32#include "sysemu/kvm.h"
33#include "hw/i386/apic-msidef.h"
34#include "hw/i386/x86-iommu.h"
35#include "trace.h"
36
37#define APIC_DELIVERY_MODE_SHIFT 8
38#define APIC_POLARITY_SHIFT 14
39#define APIC_TRIG_MODE_SHIFT 15
40
41static IOAPICCommonState *ioapics[MAX_IOAPICS];
42
43
44extern int ioapic_no;
45
46struct ioapic_entry_info {
47
48 uint8_t masked;
49 uint8_t trig_mode;
50 uint16_t dest_idx;
51 uint8_t dest_mode;
52 uint8_t delivery_mode;
53 uint8_t vector;
54
55
56 uint32_t addr;
57 uint32_t data;
58};
59
60static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info)
61{
62 memset(info, 0, sizeof(*info));
63 info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1;
64 info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1;
65
66
67
68
69
70
71 info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff;
72 info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
73 info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \
74 & IOAPIC_DM_MASK;
75 if (info->delivery_mode == IOAPIC_DM_EXTINT) {
76 info->vector = pic_read_irq(isa_pic);
77 } else {
78 info->vector = entry & IOAPIC_VECTOR_MASK;
79 }
80
81 info->addr = APIC_DEFAULT_ADDRESS | \
82 (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \
83 (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT);
84 info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \
85 (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \
86 (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT);
87}
88
89static void ioapic_service(IOAPICCommonState *s)
90{
91 AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as;
92 struct ioapic_entry_info info;
93 uint8_t i;
94 uint32_t mask;
95 uint64_t entry;
96
97 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
98 mask = 1 << i;
99 if (s->irr & mask) {
100 int coalesce = 0;
101
102 entry = s->ioredtbl[i];
103 ioapic_entry_parse(entry, &info);
104 if (!info.masked) {
105 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
106 s->irr &= ~mask;
107 } else {
108 coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR;
109 trace_ioapic_set_remote_irr(i);
110 s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
111 }
112
113 if (coalesce) {
114
115
116
117 continue;
118 }
119
120#ifdef CONFIG_KVM
121 if (kvm_irqchip_is_split()) {
122 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
123 kvm_set_irq(kvm_state, i, 1);
124 kvm_set_irq(kvm_state, i, 0);
125 } else {
126 kvm_set_irq(kvm_state, i, 1);
127 }
128 continue;
129 }
130#endif
131
132
133
134
135
136 stl_le_phys(ioapic_as, info.addr, info.data);
137 }
138 }
139 }
140}
141
142static void ioapic_set_irq(void *opaque, int vector, int level)
143{
144 IOAPICCommonState *s = opaque;
145
146
147
148
149
150 trace_ioapic_set_irq(vector, level);
151 ioapic_stat_update_irq(s, vector, level);
152 if (vector == 0) {
153 vector = 2;
154 }
155 if (vector < IOAPIC_NUM_PINS) {
156 uint32_t mask = 1 << vector;
157 uint64_t entry = s->ioredtbl[vector];
158
159 if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
160 IOAPIC_TRIGGER_LEVEL) {
161
162 if (level) {
163 s->irr |= mask;
164 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) {
165 ioapic_service(s);
166 }
167 } else {
168 s->irr &= ~mask;
169 }
170 } else {
171
172
173 if (level && !(entry & IOAPIC_LVT_MASKED)) {
174 s->irr |= mask;
175 ioapic_service(s);
176 }
177 }
178 }
179}
180
181static void ioapic_update_kvm_routes(IOAPICCommonState *s)
182{
183#ifdef CONFIG_KVM
184 int i;
185
186 if (kvm_irqchip_is_split()) {
187 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
188 MSIMessage msg;
189 struct ioapic_entry_info info;
190 ioapic_entry_parse(s->ioredtbl[i], &info);
191 if (!info.masked) {
192 msg.address = info.addr;
193 msg.data = info.data;
194 kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL);
195 }
196 }
197 kvm_irqchip_commit_routes(kvm_state);
198 }
199#endif
200}
201
202#ifdef CONFIG_KVM
203static void ioapic_iec_notifier(void *private, bool global,
204 uint32_t index, uint32_t mask)
205{
206 IOAPICCommonState *s = (IOAPICCommonState *)private;
207
208 ioapic_update_kvm_routes(s);
209}
210#endif
211
212void ioapic_eoi_broadcast(int vector)
213{
214 IOAPICCommonState *s;
215 uint64_t entry;
216 int i, n;
217
218 trace_ioapic_eoi_broadcast(vector);
219
220 for (i = 0; i < MAX_IOAPICS; i++) {
221 s = ioapics[i];
222 if (!s) {
223 continue;
224 }
225 for (n = 0; n < IOAPIC_NUM_PINS; n++) {
226 entry = s->ioredtbl[n];
227 if ((entry & IOAPIC_LVT_REMOTE_IRR)
228 && (entry & IOAPIC_VECTOR_MASK) == vector) {
229 trace_ioapic_clear_remote_irr(n, vector);
230 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
231 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
232 ioapic_service(s);
233 }
234 }
235 }
236 }
237}
238
239static uint64_t
240ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
241{
242 IOAPICCommonState *s = opaque;
243 int index;
244 uint32_t val = 0;
245
246 addr &= 0xff;
247
248 switch (addr) {
249 case IOAPIC_IOREGSEL:
250 val = s->ioregsel;
251 break;
252 case IOAPIC_IOWIN:
253 if (size != 4) {
254 break;
255 }
256 switch (s->ioregsel) {
257 case IOAPIC_REG_ID:
258 case IOAPIC_REG_ARB:
259 val = s->id << IOAPIC_ID_SHIFT;
260 break;
261 case IOAPIC_REG_VER:
262 val = s->version |
263 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
264 break;
265 default:
266 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
267 if (index >= 0 && index < IOAPIC_NUM_PINS) {
268 if (s->ioregsel & 1) {
269 val = s->ioredtbl[index] >> 32;
270 } else {
271 val = s->ioredtbl[index] & 0xffffffff;
272 }
273 }
274 }
275 break;
276 }
277
278 trace_ioapic_mem_read(addr, s->ioregsel, size, val);
279
280 return val;
281}
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301
302static inline void
303ioapic_fix_edge_remote_irr(uint64_t *entry)
304{
305 if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) {
306
307 *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR);
308 }
309}
310
311static void
312ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
313 unsigned int size)
314{
315 IOAPICCommonState *s = opaque;
316 int index;
317
318 addr &= 0xff;
319 trace_ioapic_mem_write(addr, s->ioregsel, size, val);
320
321 switch (addr) {
322 case IOAPIC_IOREGSEL:
323 s->ioregsel = val;
324 break;
325 case IOAPIC_IOWIN:
326 if (size != 4) {
327 break;
328 }
329 switch (s->ioregsel) {
330 case IOAPIC_REG_ID:
331 s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
332 break;
333 case IOAPIC_REG_VER:
334 case IOAPIC_REG_ARB:
335 break;
336 default:
337 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
338 if (index >= 0 && index < IOAPIC_NUM_PINS) {
339 uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS;
340 if (s->ioregsel & 1) {
341 s->ioredtbl[index] &= 0xffffffff;
342 s->ioredtbl[index] |= (uint64_t)val << 32;
343 } else {
344 s->ioredtbl[index] &= ~0xffffffffULL;
345 s->ioredtbl[index] |= val;
346 }
347
348 s->ioredtbl[index] &= IOAPIC_RW_BITS;
349 s->ioredtbl[index] |= ro_bits;
350 ioapic_fix_edge_remote_irr(&s->ioredtbl[index]);
351 ioapic_service(s);
352 }
353 }
354 break;
355 case IOAPIC_EOI:
356
357 if (size != 4 || s->version != 0x20) {
358 break;
359 }
360 ioapic_eoi_broadcast(val);
361 break;
362 }
363
364 ioapic_update_kvm_routes(s);
365}
366
367static const MemoryRegionOps ioapic_io_ops = {
368 .read = ioapic_mem_read,
369 .write = ioapic_mem_write,
370 .endianness = DEVICE_NATIVE_ENDIAN,
371};
372
373static void ioapic_machine_done_notify(Notifier *notifier, void *data)
374{
375#ifdef CONFIG_KVM
376 IOAPICCommonState *s = container_of(notifier, IOAPICCommonState,
377 machine_done);
378
379 if (kvm_irqchip_is_split()) {
380 X86IOMMUState *iommu = x86_iommu_get_default();
381 if (iommu) {
382
383
384
385 x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s);
386 }
387 }
388#endif
389}
390
391#define IOAPIC_VER_DEF 0x20
392
393static void ioapic_realize(DeviceState *dev, Error **errp)
394{
395 IOAPICCommonState *s = IOAPIC_COMMON(dev);
396
397 if (s->version != 0x11 && s->version != 0x20) {
398 error_setg(errp, "IOAPIC only supports version 0x11 or 0x20 "
399 "(default: 0x%x).", IOAPIC_VER_DEF);
400 return;
401 }
402
403 memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
404 "ioapic", 0x1000);
405
406 qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
407
408 ioapics[ioapic_no] = s;
409 s->machine_done.notify = ioapic_machine_done_notify;
410 qemu_add_machine_init_done_notifier(&s->machine_done);
411}
412
413static Property ioapic_properties[] = {
414 DEFINE_PROP_UINT8("version", IOAPICCommonState, version, IOAPIC_VER_DEF),
415 DEFINE_PROP_END_OF_LIST(),
416};
417
418static void ioapic_class_init(ObjectClass *klass, void *data)
419{
420 IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
421 DeviceClass *dc = DEVICE_CLASS(klass);
422
423 k->realize = ioapic_realize;
424
425
426
427
428 k->post_load = ioapic_update_kvm_routes;
429 dc->reset = ioapic_reset_common;
430 dc->props = ioapic_properties;
431}
432
433static const TypeInfo ioapic_info = {
434 .name = TYPE_IOAPIC,
435 .parent = TYPE_IOAPIC_COMMON,
436 .instance_size = sizeof(IOAPICCommonState),
437 .class_init = ioapic_class_init,
438};
439
440static void ioapic_register_types(void)
441{
442 type_register_static(&ioapic_info);
443}
444
445type_init(ioapic_register_types)
446