LXR qemu/hw/misc/armsse-mhu.c

   1/*
   2 * ARM SSE-200 Message Handling Unit (MHU)
   3 *
   4 * Copyright (c) 2019 Linaro Limited
   5 * Written by Peter Maydell
   6 *
   7 *  This program is free software; you can redistribute it and/or modify
   8 *  it under the terms of the GNU General Public License version 2 or
   9 *  (at your option) any later version.
  10 */
  11
  12/*
  13 * This is a model of the Message Handling Unit (MHU) which is part of the
  14 * Arm SSE-200 and documented in
  15 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
  16 */
  17
  18#include "qemu/osdep.h"
  19#include "qemu/log.h"
  20#include "trace.h"
  21#include "qapi/error.h"
  22#include "sysemu/sysemu.h"
  23#include "hw/sysbus.h"
  24#include "hw/registerfields.h"
  25#include "hw/misc/armsse-mhu.h"
  26
  27REG32(CPU0INTR_STAT, 0x0)
  28REG32(CPU0INTR_SET, 0x4)
  29REG32(CPU0INTR_CLR, 0x8)
  30REG32(CPU1INTR_STAT, 0x10)
  31REG32(CPU1INTR_SET, 0x14)
  32REG32(CPU1INTR_CLR, 0x18)
  33REG32(PID4, 0xfd0)
  34REG32(PID5, 0xfd4)
  35REG32(PID6, 0xfd8)
  36REG32(PID7, 0xfdc)
  37REG32(PID0, 0xfe0)
  38REG32(PID1, 0xfe4)
  39REG32(PID2, 0xfe8)
  40REG32(PID3, 0xfec)
  41REG32(CID0, 0xff0)
  42REG32(CID1, 0xff4)
  43REG32(CID2, 0xff8)
  44REG32(CID3, 0xffc)
  45
  46/* Valid bits in the interrupt registers. If any are set the IRQ is raised */
  47#define INTR_MASK 0xf
  48
  49/* PID/CID values */
  50static const int armsse_mhu_id[] = {
  51    0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
  52    0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
  53    0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
  54};
  55
  56static void armsse_mhu_update(ARMSSEMHU *s)
  57{
  58    qemu_set_irq(s->cpu0irq, s->cpu0intr != 0);
  59    qemu_set_irq(s->cpu1irq, s->cpu1intr != 0);
  60}
  61
  62static uint64_t armsse_mhu_read(void *opaque, hwaddr offset, unsigned size)
  63{
  64    ARMSSEMHU *s = ARMSSE_MHU(opaque);
  65    uint64_t r;
  66
  67    switch (offset) {
  68    case A_CPU0INTR_STAT:
  69        r = s->cpu0intr;
  70        break;
  71
  72    case A_CPU1INTR_STAT:
  73        r = s->cpu1intr;
  74        break;
  75
  76    case A_PID4 ... A_CID3:
  77        r = armsse_mhu_id[(offset - A_PID4) / 4];
  78        break;
  79
  80    case A_CPU0INTR_SET:
  81    case A_CPU0INTR_CLR:
  82    case A_CPU1INTR_SET:
  83    case A_CPU1INTR_CLR:
  84        qemu_log_mask(LOG_GUEST_ERROR,
  85                      "SSE MHU: read of write-only register at offset 0x%x\n",
  86                      (int)offset);
  87        r = 0;
  88        break;
  89
  90    default:
  91        qemu_log_mask(LOG_GUEST_ERROR,
  92                      "SSE MHU read: bad offset 0x%x\n", (int)offset);
  93        r = 0;
  94        break;
  95    }
  96    trace_armsse_mhu_read(offset, r, size);
  97    return r;
  98}
  99
 100static void armsse_mhu_write(void *opaque, hwaddr offset,
 101                             uint64_t value, unsigned size)
 102{
 103    ARMSSEMHU *s = ARMSSE_MHU(opaque);
 104
 105    trace_armsse_mhu_write(offset, value, size);
 106
 107    switch (offset) {
 108    case A_CPU0INTR_SET:
 109        s->cpu0intr |= (value & INTR_MASK);
 110        break;
 111    case A_CPU0INTR_CLR:
 112        s->cpu0intr &= ~(value & INTR_MASK);
 113        break;
 114    case A_CPU1INTR_SET:
 115        s->cpu1intr |= (value & INTR_MASK);
 116        break;
 117    case A_CPU1INTR_CLR:
 118        s->cpu1intr &= ~(value & INTR_MASK);
 119        break;
 120
 121    case A_CPU0INTR_STAT:
 122    case A_CPU1INTR_STAT:
 123    case A_PID4 ... A_CID3:
 124        qemu_log_mask(LOG_GUEST_ERROR,
 125                      "SSE MHU: write to read-only register at offset 0x%x\n",
 126                      (int)offset);
 127        break;
 128
 129    default:
 130        qemu_log_mask(LOG_GUEST_ERROR,
 131                      "SSE MHU write: bad offset 0x%x\n", (int)offset);
 132        break;
 133    }
 134
 135    armsse_mhu_update(s);
 136}
 137
 138static const MemoryRegionOps armsse_mhu_ops = {
 139    .read = armsse_mhu_read,
 140    .write = armsse_mhu_write,
 141    .endianness = DEVICE_LITTLE_ENDIAN,
 142    .valid.min_access_size = 4,
 143    .valid.max_access_size = 4,
 144};
 145
 146static void armsse_mhu_reset(DeviceState *dev)
 147{
 148    ARMSSEMHU *s = ARMSSE_MHU(dev);
 149
 150    s->cpu0intr = 0;
 151    s->cpu1intr = 0;
 152}
 153
 154static const VMStateDescription armsse_mhu_vmstate = {
 155    .name = "armsse-mhu",
 156    .version_id = 1,
 157    .minimum_version_id = 1,
 158    .fields = (VMStateField[]) {
 159        VMSTATE_UINT32(cpu0intr, ARMSSEMHU),
 160        VMSTATE_UINT32(cpu1intr, ARMSSEMHU),
 161        VMSTATE_END_OF_LIST()
 162    },
 163};
 164
 165static void armsse_mhu_init(Object *obj)
 166{
 167    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 168    ARMSSEMHU *s = ARMSSE_MHU(obj);
 169
 170    memory_region_init_io(&s->iomem, obj, &armsse_mhu_ops,
 171                          s, "armsse-mhu", 0x1000);
 172    sysbus_init_mmio(sbd, &s->iomem);
 173    sysbus_init_irq(sbd, &s->cpu0irq);
 174    sysbus_init_irq(sbd, &s->cpu1irq);
 175}
 176
 177static void armsse_mhu_class_init(ObjectClass *klass, void *data)
 178{
 179    DeviceClass *dc = DEVICE_CLASS(klass);
 180
 181    dc->reset = armsse_mhu_reset;
 182    dc->vmsd = &armsse_mhu_vmstate;
 183}
 184
 185static const TypeInfo armsse_mhu_info = {
 186    .name = TYPE_ARMSSE_MHU,
 187    .parent = TYPE_SYS_BUS_DEVICE,
 188    .instance_size = sizeof(ARMSSEMHU),
 189    .instance_init = armsse_mhu_init,
 190    .class_init = armsse_mhu_class_init,
 191};
 192
 193static void armsse_mhu_register_types(void)
 194{
 195    type_register_static(&armsse_mhu_info);
 196}
 197
 198type_init(armsse_mhu_register_types);
 199