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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/i386/pc.h"
28#include "hw/pci/pci.h"
29#include "hw/pci/pci_host.h"
30#include "hw/isa/isa.h"
31#include "hw/sysbus.h"
32#include "qapi/error.h"
33#include "qemu/range.h"
34#include "hw/xen/xen.h"
35#include "hw/pci-host/pam.h"
36#include "sysemu/sysemu.h"
37#include "hw/i386/ioapic.h"
38#include "qapi/visitor.h"
39#include "qemu/error-report.h"
40
41
42
43
44
45
46#define I440FX_PCI_HOST_BRIDGE(obj) \
47 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
48
49typedef struct I440FXState {
50 PCIHostState parent_obj;
51 Range pci_hole;
52 uint64_t pci_hole64_size;
53 bool pci_hole64_fix;
54 uint32_t short_root_bus;
55} I440FXState;
56
57#define PIIX_NUM_PIC_IRQS 16
58#define PIIX_NUM_PIRQS 4ULL
59#define XEN_PIIX_NUM_PIRQS 128ULL
60#define PIIX_PIRQC 0x60
61
62typedef struct PIIX3State {
63 PCIDevice dev;
64
65
66
67
68
69
70
71
72
73
74#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
75#error "unable to encode pic state in 64bit in pic_levels."
76#endif
77 uint64_t pic_levels;
78
79 qemu_irq *pic;
80
81
82 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
83
84
85 uint8_t rcr;
86
87
88 MemoryRegion rcr_mem;
89} PIIX3State;
90
91#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
92#define PIIX3_PCI_DEVICE(obj) \
93 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
94
95#define I440FX_PCI_DEVICE(obj) \
96 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
97
98#define TYPE_PIIX3_DEVICE "PIIX3"
99#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
100
101struct PCII440FXState {
102
103 PCIDevice parent_obj;
104
105
106 MemoryRegion *system_memory;
107 MemoryRegion *pci_address_space;
108 MemoryRegion *ram_memory;
109 PAMMemoryRegion pam_regions[13];
110 MemoryRegion smram_region;
111 MemoryRegion smram, low_smram;
112};
113
114
115#define I440FX_PAM 0x59
116#define I440FX_PAM_SIZE 7
117#define I440FX_SMRAM 0x72
118
119
120#define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
121
122
123
124
125#define I440FX_COREBOOT_RAM_SIZE 0x57
126
127static void piix3_set_irq(void *opaque, int pirq, int level);
128static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
129static void piix3_write_config_xen(PCIDevice *dev,
130 uint32_t address, uint32_t val, int len);
131
132
133
134
135static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
136{
137 int slot_addend;
138 slot_addend = (pci_dev->devfn >> 3) - 1;
139 return (pci_intx + slot_addend) & 3;
140}
141
142static void i440fx_update_memory_mappings(PCII440FXState *d)
143{
144 int i;
145 PCIDevice *pd = PCI_DEVICE(d);
146
147 memory_region_transaction_begin();
148 for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
149 pam_update(&d->pam_regions[i], i,
150 pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
151 }
152 memory_region_set_enabled(&d->smram_region,
153 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
154 memory_region_set_enabled(&d->smram,
155 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
156 memory_region_transaction_commit();
157}
158
159
160static void i440fx_write_config(PCIDevice *dev,
161 uint32_t address, uint32_t val, int len)
162{
163 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
164
165
166 pci_default_write_config(dev, address, val, len);
167 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
168 range_covers_byte(address, len, I440FX_SMRAM)) {
169 i440fx_update_memory_mappings(d);
170 }
171}
172
173static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
174{
175 PCII440FXState *d = opaque;
176 PCIDevice *pd = PCI_DEVICE(d);
177 int ret, i;
178 uint8_t smm_enabled;
179
180 ret = pci_device_load(pd, f);
181 if (ret < 0)
182 return ret;
183 i440fx_update_memory_mappings(d);
184 qemu_get_8s(f, &smm_enabled);
185
186 if (version_id == 2) {
187 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
188 qemu_get_be32(f);
189 }
190 }
191
192 return 0;
193}
194
195static int i440fx_post_load(void *opaque, int version_id)
196{
197 PCII440FXState *d = opaque;
198
199 i440fx_update_memory_mappings(d);
200 return 0;
201}
202
203static const VMStateDescription vmstate_i440fx = {
204 .name = "I440FX",
205 .version_id = 3,
206 .minimum_version_id = 3,
207 .minimum_version_id_old = 1,
208 .load_state_old = i440fx_load_old,
209 .post_load = i440fx_post_load,
210 .fields = (VMStateField[]) {
211 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
212
213
214
215 VMSTATE_UNUSED(1),
216 VMSTATE_END_OF_LIST()
217 }
218};
219
220static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
221 const char *name, void *opaque,
222 Error **errp)
223{
224 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
225 uint64_t val64;
226 uint32_t value;
227
228 val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
229 value = val64;
230 assert(value == val64);
231 visit_type_uint32(v, name, &value, errp);
232}
233
234static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
235 const char *name, void *opaque,
236 Error **errp)
237{
238 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
239 uint64_t val64;
240 uint32_t value;
241
242 val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
243 value = val64;
244 assert(value == val64);
245 visit_type_uint32(v, name, &value, errp);
246}
247
248
249
250
251
252
253
254
255static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
256{
257 PCIHostState *h = PCI_HOST_BRIDGE(obj);
258 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
259 Range w64;
260 uint64_t value;
261
262 pci_bus_get_w64_range(h->bus, &w64);
263 value = range_is_empty(&w64) ? 0 : range_lob(&w64);
264 if (!value && s->pci_hole64_fix) {
265 value = pc_pci_hole64_start();
266 }
267 return value;
268}
269
270static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
271 const char *name,
272 void *opaque, Error **errp)
273{
274 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
275
276 visit_type_uint64(v, name, &hole64_start, errp);
277}
278
279
280
281
282
283
284
285static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
286 const char *name, void *opaque,
287 Error **errp)
288{
289 PCIHostState *h = PCI_HOST_BRIDGE(obj);
290 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
291 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
292 Range w64;
293 uint64_t value, hole64_end;
294
295 pci_bus_get_w64_range(h->bus, &w64);
296 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
297 hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
298 if (s->pci_hole64_fix && value < hole64_end) {
299 value = hole64_end;
300 }
301 visit_type_uint64(v, name, &value, errp);
302}
303
304static void i440fx_pcihost_initfn(Object *obj)
305{
306 PCIHostState *s = PCI_HOST_BRIDGE(obj);
307
308 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
309 "pci-conf-idx", 4);
310 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
311 "pci-conf-data", 4);
312
313 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
314 i440fx_pcihost_get_pci_hole_start,
315 NULL, NULL, NULL, NULL);
316
317 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
318 i440fx_pcihost_get_pci_hole_end,
319 NULL, NULL, NULL, NULL);
320
321 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
322 i440fx_pcihost_get_pci_hole64_start,
323 NULL, NULL, NULL, NULL);
324
325 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
326 i440fx_pcihost_get_pci_hole64_end,
327 NULL, NULL, NULL, NULL);
328}
329
330static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
331{
332 PCIHostState *s = PCI_HOST_BRIDGE(dev);
333 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
334
335 sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
336 sysbus_init_ioports(sbd, 0xcf8, 4);
337
338 sysbus_add_io(sbd, 0xcfc, &s->data_mem);
339 sysbus_init_ioports(sbd, 0xcfc, 4);
340
341
342 memory_region_set_flush_coalesced(&s->data_mem);
343 memory_region_add_coalescing(&s->conf_mem, 0, 4);
344}
345
346static void i440fx_realize(PCIDevice *dev, Error **errp)
347{
348 dev->config[I440FX_SMRAM] = 0x02;
349
350 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
351 warn_report("i440fx doesn't support emulated iommu");
352 }
353}
354
355PCIBus *i440fx_init(const char *host_type, const char *pci_type,
356 PCII440FXState **pi440fx_state,
357 int *piix3_devfn,
358 ISABus **isa_bus, qemu_irq *pic,
359 MemoryRegion *address_space_mem,
360 MemoryRegion *address_space_io,
361 ram_addr_t ram_size,
362 ram_addr_t below_4g_mem_size,
363 ram_addr_t above_4g_mem_size,
364 MemoryRegion *pci_address_space,
365 MemoryRegion *ram_memory)
366{
367 DeviceState *dev;
368 PCIBus *b;
369 PCIDevice *d;
370 PCIHostState *s;
371 PIIX3State *piix3;
372 PCII440FXState *f;
373 unsigned i;
374 I440FXState *i440fx;
375
376 dev = qdev_create(NULL, host_type);
377 s = PCI_HOST_BRIDGE(dev);
378 b = pci_root_bus_new(dev, NULL, pci_address_space,
379 address_space_io, 0, TYPE_PCI_BUS);
380 s->bus = b;
381 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
382 qdev_init_nofail(dev);
383
384 d = pci_create_simple(b, 0, pci_type);
385 *pi440fx_state = I440FX_PCI_DEVICE(d);
386 f = *pi440fx_state;
387 f->system_memory = address_space_mem;
388 f->pci_address_space = pci_address_space;
389 f->ram_memory = ram_memory;
390
391 i440fx = I440FX_PCI_HOST_BRIDGE(dev);
392 range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
393 IO_APIC_DEFAULT_ADDRESS - 1);
394
395
396 pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
397 f->pci_address_space);
398
399
400 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
401 f->pci_address_space, 0xa0000, 0x20000);
402 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
403 &f->smram_region, 1);
404 memory_region_set_enabled(&f->smram_region, true);
405
406
407 memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
408 memory_region_set_enabled(&f->smram, true);
409 memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
410 f->ram_memory, 0xa0000, 0x20000);
411 memory_region_set_enabled(&f->low_smram, true);
412 memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
413 object_property_add_const_link(qdev_get_machine(), "smram",
414 OBJECT(&f->smram), &error_abort);
415
416 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
417 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
418 for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
419 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
420 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
421 PAM_EXPAN_SIZE);
422 }
423
424
425
426
427
428 if (xen_enabled()) {
429 PCIDevice *pci_dev = pci_create_simple_multifunction(b,
430 -1, true, TYPE_PIIX3_XEN_DEVICE);
431 piix3 = PIIX3_PCI_DEVICE(pci_dev);
432 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
433 piix3, XEN_PIIX_NUM_PIRQS);
434 } else {
435 PCIDevice *pci_dev = pci_create_simple_multifunction(b,
436 -1, true, TYPE_PIIX3_DEVICE);
437 piix3 = PIIX3_PCI_DEVICE(pci_dev);
438 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
439 PIIX_NUM_PIRQS);
440 pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
441 }
442 piix3->pic = pic;
443 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
444
445 *piix3_devfn = piix3->dev.devfn;
446
447 ram_size = ram_size / 8 / 1024 / 1024;
448 if (ram_size > 255) {
449 ram_size = 255;
450 }
451 d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
452
453 i440fx_update_memory_mappings(f);
454
455 return b;
456}
457
458PCIBus *find_i440fx(void)
459{
460 PCIHostState *s = OBJECT_CHECK(PCIHostState,
461 object_resolve_path("/machine/i440fx", NULL),
462 TYPE_PCI_HOST_BRIDGE);
463 return s ? s->bus : NULL;
464}
465
466
467static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
468{
469 qemu_set_irq(piix3->pic[pic_irq],
470 !!(piix3->pic_levels &
471 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
472 (pic_irq * PIIX_NUM_PIRQS))));
473}
474
475static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
476{
477 int pic_irq;
478 uint64_t mask;
479
480 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
481 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
482 return;
483 }
484
485 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
486 piix3->pic_levels &= ~mask;
487 piix3->pic_levels |= mask * !!level;
488}
489
490static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
491{
492 int pic_irq;
493
494 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
495 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
496 return;
497 }
498
499 piix3_set_irq_level_internal(piix3, pirq, level);
500
501 piix3_set_irq_pic(piix3, pic_irq);
502}
503
504static void piix3_set_irq(void *opaque, int pirq, int level)
505{
506 PIIX3State *piix3 = opaque;
507 piix3_set_irq_level(piix3, pirq, level);
508}
509
510static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
511{
512 PIIX3State *piix3 = opaque;
513 int irq = piix3->dev.config[PIIX_PIRQC + pin];
514 PCIINTxRoute route;
515
516 if (irq < PIIX_NUM_PIC_IRQS) {
517 route.mode = PCI_INTX_ENABLED;
518 route.irq = irq;
519 } else {
520 route.mode = PCI_INTX_DISABLED;
521 route.irq = -1;
522 }
523 return route;
524}
525
526
527static void piix3_update_irq_levels(PIIX3State *piix3)
528{
529 PCIBus *bus = pci_get_bus(&piix3->dev);
530 int pirq;
531
532 piix3->pic_levels = 0;
533 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
534 piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
535 }
536}
537
538static void piix3_write_config(PCIDevice *dev,
539 uint32_t address, uint32_t val, int len)
540{
541 pci_default_write_config(dev, address, val, len);
542 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
543 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
544 int pic_irq;
545
546 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
547 piix3_update_irq_levels(piix3);
548 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
549 piix3_set_irq_pic(piix3, pic_irq);
550 }
551 }
552}
553
554static void piix3_write_config_xen(PCIDevice *dev,
555 uint32_t address, uint32_t val, int len)
556{
557 xen_piix_pci_write_config_client(address, val, len);
558 piix3_write_config(dev, address, val, len);
559}
560
561static void piix3_reset(void *opaque)
562{
563 PIIX3State *d = opaque;
564 uint8_t *pci_conf = d->dev.config;
565
566 pci_conf[0x04] = 0x07;
567 pci_conf[0x05] = 0x00;
568 pci_conf[0x06] = 0x00;
569 pci_conf[0x07] = 0x02;
570 pci_conf[0x4c] = 0x4d;
571 pci_conf[0x4e] = 0x03;
572 pci_conf[0x4f] = 0x00;
573 pci_conf[0x60] = 0x80;
574 pci_conf[0x61] = 0x80;
575 pci_conf[0x62] = 0x80;
576 pci_conf[0x63] = 0x80;
577 pci_conf[0x69] = 0x02;
578 pci_conf[0x70] = 0x80;
579 pci_conf[0x76] = 0x0c;
580 pci_conf[0x77] = 0x0c;
581 pci_conf[0x78] = 0x02;
582 pci_conf[0x79] = 0x00;
583 pci_conf[0x80] = 0x00;
584 pci_conf[0x82] = 0x00;
585 pci_conf[0xa0] = 0x08;
586 pci_conf[0xa2] = 0x00;
587 pci_conf[0xa3] = 0x00;
588 pci_conf[0xa4] = 0x00;
589 pci_conf[0xa5] = 0x00;
590 pci_conf[0xa6] = 0x00;
591 pci_conf[0xa7] = 0x00;
592 pci_conf[0xa8] = 0x0f;
593 pci_conf[0xaa] = 0x00;
594 pci_conf[0xab] = 0x00;
595 pci_conf[0xac] = 0x00;
596 pci_conf[0xae] = 0x00;
597
598 d->pic_levels = 0;
599 d->rcr = 0;
600}
601
602static int piix3_post_load(void *opaque, int version_id)
603{
604 PIIX3State *piix3 = opaque;
605 int pirq;
606
607
608
609
610
611
612
613
614
615 piix3->pic_levels = 0;
616 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
617 piix3_set_irq_level_internal(piix3, pirq,
618 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
619 }
620 return 0;
621}
622
623static int piix3_pre_save(void *opaque)
624{
625 int i;
626 PIIX3State *piix3 = opaque;
627
628 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
629 piix3->pci_irq_levels_vmstate[i] =
630 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
631 }
632
633 return 0;
634}
635
636static bool piix3_rcr_needed(void *opaque)
637{
638 PIIX3State *piix3 = opaque;
639
640 return (piix3->rcr != 0);
641}
642
643static const VMStateDescription vmstate_piix3_rcr = {
644 .name = "PIIX3/rcr",
645 .version_id = 1,
646 .minimum_version_id = 1,
647 .needed = piix3_rcr_needed,
648 .fields = (VMStateField[]) {
649 VMSTATE_UINT8(rcr, PIIX3State),
650 VMSTATE_END_OF_LIST()
651 }
652};
653
654static const VMStateDescription vmstate_piix3 = {
655 .name = "PIIX3",
656 .version_id = 3,
657 .minimum_version_id = 2,
658 .post_load = piix3_post_load,
659 .pre_save = piix3_pre_save,
660 .fields = (VMStateField[]) {
661 VMSTATE_PCI_DEVICE(dev, PIIX3State),
662 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
663 PIIX_NUM_PIRQS, 3),
664 VMSTATE_END_OF_LIST()
665 },
666 .subsections = (const VMStateDescription*[]) {
667 &vmstate_piix3_rcr,
668 NULL
669 }
670};
671
672
673static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
674{
675 PIIX3State *d = opaque;
676
677 if (val & 4) {
678 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
679 return;
680 }
681 d->rcr = val & 2;
682}
683
684static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
685{
686 PIIX3State *d = opaque;
687
688 return d->rcr;
689}
690
691static const MemoryRegionOps rcr_ops = {
692 .read = rcr_read,
693 .write = rcr_write,
694 .endianness = DEVICE_LITTLE_ENDIAN
695};
696
697static void piix3_realize(PCIDevice *dev, Error **errp)
698{
699 PIIX3State *d = PIIX3_PCI_DEVICE(dev);
700
701 if (!isa_bus_new(DEVICE(d), get_system_memory(),
702 pci_address_space_io(dev), errp)) {
703 return;
704 }
705
706 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
707 "piix3-reset-control", 1);
708 memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
709 &d->rcr_mem, 1);
710
711 qemu_register_reset(piix3_reset, d);
712}
713
714static void pci_piix3_class_init(ObjectClass *klass, void *data)
715{
716 DeviceClass *dc = DEVICE_CLASS(klass);
717 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
718
719 dc->desc = "ISA bridge";
720 dc->vmsd = &vmstate_piix3;
721 dc->hotpluggable = false;
722 k->realize = piix3_realize;
723 k->vendor_id = PCI_VENDOR_ID_INTEL;
724
725 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
726 k->class_id = PCI_CLASS_BRIDGE_ISA;
727
728
729
730
731 dc->user_creatable = false;
732}
733
734static const TypeInfo piix3_pci_type_info = {
735 .name = TYPE_PIIX3_PCI_DEVICE,
736 .parent = TYPE_PCI_DEVICE,
737 .instance_size = sizeof(PIIX3State),
738 .abstract = true,
739 .class_init = pci_piix3_class_init,
740 .interfaces = (InterfaceInfo[]) {
741 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
742 { },
743 },
744};
745
746static void piix3_class_init(ObjectClass *klass, void *data)
747{
748 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
749
750 k->config_write = piix3_write_config;
751}
752
753static const TypeInfo piix3_info = {
754 .name = TYPE_PIIX3_DEVICE,
755 .parent = TYPE_PIIX3_PCI_DEVICE,
756 .class_init = piix3_class_init,
757};
758
759static void piix3_xen_class_init(ObjectClass *klass, void *data)
760{
761 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
762
763 k->config_write = piix3_write_config_xen;
764};
765
766static const TypeInfo piix3_xen_info = {
767 .name = TYPE_PIIX3_XEN_DEVICE,
768 .parent = TYPE_PIIX3_PCI_DEVICE,
769 .class_init = piix3_xen_class_init,
770};
771
772static void i440fx_class_init(ObjectClass *klass, void *data)
773{
774 DeviceClass *dc = DEVICE_CLASS(klass);
775 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
776
777 k->realize = i440fx_realize;
778 k->config_write = i440fx_write_config;
779 k->vendor_id = PCI_VENDOR_ID_INTEL;
780 k->device_id = PCI_DEVICE_ID_INTEL_82441;
781 k->revision = 0x02;
782 k->class_id = PCI_CLASS_BRIDGE_HOST;
783 dc->desc = "Host bridge";
784 dc->vmsd = &vmstate_i440fx;
785
786
787
788
789 dc->user_creatable = false;
790 dc->hotpluggable = false;
791}
792
793static const TypeInfo i440fx_info = {
794 .name = TYPE_I440FX_PCI_DEVICE,
795 .parent = TYPE_PCI_DEVICE,
796 .instance_size = sizeof(PCII440FXState),
797 .class_init = i440fx_class_init,
798 .interfaces = (InterfaceInfo[]) {
799 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
800 { },
801 },
802};
803
804
805typedef struct {
806 uint8_t offset;
807 uint8_t len;
808} IGDHostInfo;
809
810
811static const IGDHostInfo igd_host_bridge_infos[] = {
812 {0x08, 2},
813 {0x2c, 2},
814 {0x2e, 2},
815 {0x50, 2},
816 {0x52, 2},
817 {0xa4, 4},
818 {0xa8, 4},
819};
820
821static void host_pci_config_read(int pos, int len, uint32_t *val, Error **errp)
822{
823 int rc, config_fd;
824
825 char *path = g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
826 0, 0, 0, 0, "config");
827
828 config_fd = open(path, O_RDWR);
829 if (config_fd < 0) {
830 error_setg_errno(errp, errno, "Failed to open: %s", path);
831 goto out;
832 }
833
834 if (lseek(config_fd, pos, SEEK_SET) != pos) {
835 error_setg_errno(errp, errno, "Failed to seek: %s", path);
836 goto out_close_fd;
837 }
838
839 do {
840 rc = read(config_fd, (uint8_t *)val, len);
841 } while (rc < 0 && (errno == EINTR || errno == EAGAIN));
842 if (rc != len) {
843 error_setg_errno(errp, errno, "Failed to read: %s", path);
844 }
845
846out_close_fd:
847 close(config_fd);
848out:
849 g_free(path);
850}
851
852static void igd_pt_i440fx_realize(PCIDevice *pci_dev, Error **errp)
853{
854 uint32_t val = 0;
855 int i, num;
856 int pos, len;
857 Error *local_err = NULL;
858
859 num = ARRAY_SIZE(igd_host_bridge_infos);
860 for (i = 0; i < num; i++) {
861 pos = igd_host_bridge_infos[i].offset;
862 len = igd_host_bridge_infos[i].len;
863 host_pci_config_read(pos, len, &val, &local_err);
864 if (local_err) {
865 error_propagate(errp, local_err);
866 return;
867 }
868 pci_default_write_config(pci_dev, pos, val, len);
869 }
870}
871
872static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)
873{
874 DeviceClass *dc = DEVICE_CLASS(klass);
875 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
876
877 k->realize = igd_pt_i440fx_realize;
878 dc->desc = "IGD Passthrough Host bridge";
879}
880
881static const TypeInfo igd_passthrough_i440fx_info = {
882 .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE,
883 .parent = TYPE_I440FX_PCI_DEVICE,
884 .instance_size = sizeof(PCII440FXState),
885 .class_init = igd_passthrough_i440fx_class_init,
886};
887
888static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
889 PCIBus *rootbus)
890{
891 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
892
893
894 if (s->short_root_bus) {
895 return "0000";
896 }
897 return "0000:00";
898}
899
900static Property i440fx_props[] = {
901 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
902 pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
903 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
904 DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
905 DEFINE_PROP_END_OF_LIST(),
906};
907
908static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
909{
910 DeviceClass *dc = DEVICE_CLASS(klass);
911 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
912
913 hc->root_bus_path = i440fx_pcihost_root_bus_path;
914 dc->realize = i440fx_pcihost_realize;
915 dc->fw_name = "pci";
916 dc->props = i440fx_props;
917
918 dc->user_creatable = false;
919}
920
921static const TypeInfo i440fx_pcihost_info = {
922 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
923 .parent = TYPE_PCI_HOST_BRIDGE,
924 .instance_size = sizeof(I440FXState),
925 .instance_init = i440fx_pcihost_initfn,
926 .class_init = i440fx_pcihost_class_init,
927};
928
929static void i440fx_register_types(void)
930{
931 type_register_static(&i440fx_info);
932 type_register_static(&igd_passthrough_i440fx_info);
933 type_register_static(&piix3_pci_type_info);
934 type_register_static(&piix3_info);
935 type_register_static(&piix3_xen_info);
936 type_register_static(&i440fx_pcihost_info);
937}
938
939type_init(i440fx_register_types)
940