LXR qemu/hw/ppc/pnv

   1/*
   2 * QEMU PowerPC PowerNV XSCOM bus
   3 *
   4 * Copyright (c) 2016, IBM Corporation.
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19#include "qemu/osdep.h"
  20#include "hw/hw.h"
  21#include "qemu/log.h"
  22#include "sysemu/hw_accel.h"
  23#include "target/ppc/cpu.h"
  24#include "hw/sysbus.h"
  25
  26#include "hw/ppc/fdt.h"
  27#include "hw/ppc/pnv.h"
  28#include "hw/ppc/pnv_xscom.h"
  29
  30#include <libfdt.h>
  31
  32static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
  33{
  34    /*
  35     * TODO: When the read/write comes from the monitor, NULL is
  36     * passed for the cpu, and no CPU completion is generated.
  37     */
  38    if (cs) {
  39        PowerPCCPU *cpu = POWERPC_CPU(cs);
  40        CPUPPCState *env = &cpu->env;
  41
  42        /*
  43         * TODO: Need a CPU helper to set HMER, also handle generation
  44         * of HMIs
  45         */
  46        cpu_synchronize_state(cs);
  47        env->spr[SPR_HMER] |= hmer_bits;
  48    }
  49}
  50
  51static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
  52{
  53    addr &= (PNV_XSCOM_SIZE - 1);
  54
  55    if (pnv_chip_is_power9(chip)) {
  56        return addr >> 3;
  57    } else {
  58        return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
  59    }
  60}
  61
  62static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
  63{
  64    switch (pcba) {
  65    case 0xf000f:
  66        return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
  67    case 0x18002:       /* ECID2 */
  68        return 0;
  69
  70    case 0x1010c00:     /* PIBAM FIR */
  71    case 0x1010c03:     /* PIBAM FIR MASK */
  72
  73        /* P9 xscom reset */
  74    case 0x0090018:     /* Receive status reg */
  75    case 0x0090012:     /* log register */
  76    case 0x0090013:     /* error register */
  77
  78        /* P8 xscom reset */
  79    case 0x2020007:     /* ADU stuff, log register */
  80    case 0x2020009:     /* ADU stuff, error register */
  81    case 0x202000f:     /* ADU stuff, receive status register*/
  82        return 0;
  83    case 0x2013f00:     /* PBA stuff */
  84    case 0x2013f01:     /* PBA stuff */
  85    case 0x2013f02:     /* PBA stuff */
  86    case 0x2013f03:     /* PBA stuff */
  87    case 0x2013f04:     /* PBA stuff */
  88    case 0x2013f05:     /* PBA stuff */
  89    case 0x2013f06:     /* PBA stuff */
  90    case 0x2013f07:     /* PBA stuff */
  91        return 0;
  92    case 0x2013028:     /* CAPP stuff */
  93    case 0x201302a:     /* CAPP stuff */
  94    case 0x2013801:     /* CAPP stuff */
  95    case 0x2013802:     /* CAPP stuff */
  96        return 0;
  97    default:
  98        return -1;
  99    }
 100}
 101
 102static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
 103{
 104    /* We ignore writes to these */
 105    switch (pcba) {
 106    case 0xf000f:       /* chip id is RO */
 107    case 0x1010c00:     /* PIBAM FIR */
 108    case 0x1010c01:     /* PIBAM FIR */
 109    case 0x1010c02:     /* PIBAM FIR */
 110    case 0x1010c03:     /* PIBAM FIR MASK */
 111    case 0x1010c04:     /* PIBAM FIR MASK */
 112    case 0x1010c05:     /* PIBAM FIR MASK */
 113        /* P9 xscom reset */
 114    case 0x0090018:     /* Receive status reg */
 115    case 0x0090012:     /* log register */
 116    case 0x0090013:     /* error register */
 117
 118        /* P8 xscom reset */
 119    case 0x2020007:     /* ADU stuff, log register */
 120    case 0x2020009:     /* ADU stuff, error register */
 121    case 0x202000f:     /* ADU stuff, receive status register*/
 122
 123    case 0x2013028:     /* CAPP stuff */
 124    case 0x201302a:     /* CAPP stuff */
 125    case 0x2013801:     /* CAPP stuff */
 126    case 0x2013802:     /* CAPP stuff */
 127        return true;
 128    default:
 129        return false;
 130    }
 131}
 132
 133static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
 134{
 135    PnvChip *chip = opaque;
 136    uint32_t pcba = pnv_xscom_pcba(chip, addr);
 137    uint64_t val = 0;
 138    MemTxResult result;
 139
 140    /* Handle some SCOMs here before dispatch */
 141    val = xscom_read_default(chip, pcba);
 142    if (val != -1) {
 143        goto complete;
 144    }
 145
 146    val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
 147                            MEMTXATTRS_UNSPECIFIED, &result);
 148    if (result != MEMTX_OK) {
 149        qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
 150                      HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
 151        xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
 152        return 0;
 153    }
 154
 155complete:
 156    xscom_complete(current_cpu, HMER_XSCOM_DONE);
 157    return val;
 158}
 159
 160static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
 161                        unsigned width)
 162{
 163    PnvChip *chip = opaque;
 164    uint32_t pcba = pnv_xscom_pcba(chip, addr);
 165    MemTxResult result;
 166
 167    /* Handle some SCOMs here before dispatch */
 168    if (xscom_write_default(chip, pcba, val)) {
 169        goto complete;
 170    }
 171
 172    address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
 173                      MEMTXATTRS_UNSPECIFIED, &result);
 174    if (result != MEMTX_OK) {
 175        qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
 176                      HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
 177                      addr, pcba, val);
 178        xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
 179        return;
 180    }
 181
 182complete:
 183    xscom_complete(current_cpu, HMER_XSCOM_DONE);
 184}
 185
 186const MemoryRegionOps pnv_xscom_ops = {
 187    .read = xscom_read,
 188    .write = xscom_write,
 189    .valid.min_access_size = 8,
 190    .valid.max_access_size = 8,
 191    .impl.min_access_size = 8,
 192    .impl.max_access_size = 8,
 193    .endianness = DEVICE_BIG_ENDIAN,
 194};
 195
 196void pnv_xscom_realize(PnvChip *chip, Error **errp)
 197{
 198    SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
 199    char *name;
 200
 201    name = g_strdup_printf("xscom-%x", chip->chip_id);
 202    memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
 203                          chip, name, PNV_XSCOM_SIZE);
 204    sysbus_init_mmio(sbd, &chip->xscom_mmio);
 205
 206    memory_region_init(&chip->xscom, OBJECT(chip), name, PNV_XSCOM_SIZE);
 207    address_space_init(&chip->xscom_as, &chip->xscom, name);
 208    g_free(name);
 209}
 210
 211static const TypeInfo pnv_xscom_interface_info = {
 212    .name = TYPE_PNV_XSCOM_INTERFACE,
 213    .parent = TYPE_INTERFACE,
 214    .class_size = sizeof(PnvXScomInterfaceClass),
 215};
 216
 217static void pnv_xscom_register_types(void)
 218{
 219    type_register_static(&pnv_xscom_interface_info);
 220}
 221
 222type_init(pnv_xscom_register_types)
 223
 224typedef struct ForeachPopulateArgs {
 225    void *fdt;
 226    int xscom_offset;
 227} ForeachPopulateArgs;
 228
 229static int xscom_dt_child(Object *child, void *opaque)
 230{
 231    if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
 232        ForeachPopulateArgs *args = opaque;
 233        PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
 234        PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
 235
 236        if (xc->dt_xscom) {
 237            _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
 238        }
 239    }
 240    return 0;
 241}
 242
 243static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
 244static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
 245
 246int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
 247{
 248    uint64_t reg[] = { cpu_to_be64(PNV_XSCOM_BASE(chip)),
 249                       cpu_to_be64(PNV_XSCOM_SIZE) };
 250    int xscom_offset;
 251    ForeachPopulateArgs args;
 252    char *name;
 253
 254    name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
 255    xscom_offset = fdt_add_subnode(fdt, root_offset, name);
 256    _FDT(xscom_offset);
 257    g_free(name);
 258    _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
 259    _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
 260    _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
 261    _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
 262
 263    if (pnv_chip_is_power9(chip)) {
 264        _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9,
 265                          sizeof(compat_p9))));
 266    } else {
 267        _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8,
 268                          sizeof(compat_p8))));
 269    }
 270
 271    _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
 272
 273    args.fdt = fdt;
 274    args.xscom_offset = xscom_offset;
 275
 276    object_child_foreach(OBJECT(chip), xscom_dt_child, &args);
 277    return 0;
 278}
 279
 280void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr)
 281{
 282    memory_region_add_subregion(&chip->xscom, offset << 3, mr);
 283}
 284
 285void pnv_xscom_region_init(MemoryRegion *mr,
 286                           struct Object *owner,
 287                           const MemoryRegionOps *ops,
 288                           void *opaque,
 289                           const char *name,
 290                           uint64_t size)
 291{
 292    memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
 293}
 294