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26
27#include "qemu/osdep.h"
28#include "qapi/error.h"
29#include "qapi/visitor.h"
30#include "sysemu/sysemu.h"
31#include "sysemu/numa.h"
32#include "sysemu/qtest.h"
33#include "hw/hw.h"
34#include "qemu/log.h"
35#include "hw/fw-path-provider.h"
36#include "elf.h"
37#include "net/net.h"
38#include "sysemu/device_tree.h"
39#include "sysemu/cpus.h"
40#include "sysemu/hw_accel.h"
41#include "kvm_ppc.h"
42#include "migration/misc.h"
43#include "migration/global_state.h"
44#include "migration/register.h"
45#include "mmu-hash64.h"
46#include "mmu-book3s-v3.h"
47#include "cpu-models.h"
48#include "qom/cpu.h"
49
50#include "hw/boards.h"
51#include "hw/ppc/ppc.h"
52#include "hw/loader.h"
53
54#include "hw/ppc/fdt.h"
55#include "hw/ppc/spapr.h"
56#include "hw/ppc/spapr_vio.h"
57#include "hw/pci-host/spapr.h"
58#include "hw/pci/msi.h"
59
60#include "hw/pci/pci.h"
61#include "hw/scsi/scsi.h"
62#include "hw/virtio/virtio-scsi.h"
63#include "hw/virtio/vhost-scsi-common.h"
64
65#include "exec/address-spaces.h"
66#include "exec/ram_addr.h"
67#include "hw/usb.h"
68#include "qemu/config-file.h"
69#include "qemu/error-report.h"
70#include "trace.h"
71#include "hw/nmi.h"
72#include "hw/intc/intc.h"
73
74#include "qemu/cutils.h"
75#include "hw/ppc/spapr_cpu_core.h"
76#include "hw/mem/memory-device.h"
77
78#include <libfdt.h>
79
80
81
82
83
84
85
86
87
88
89
90#define FDT_MAX_SIZE 0x100000
91#define RTAS_MAX_SIZE 0x10000
92#define RTAS_MAX_ADDR 0x80000000
93#define FW_MAX_SIZE 0x400000
94#define FW_FILE_NAME "slof.bin"
95#define FW_OVERHEAD 0x2800000
96#define KERNEL_LOAD_ADDR FW_MAX_SIZE
97
98#define MIN_RMA_SLOF 128UL
99
100#define PHANDLE_INTC 0x00001111
101
102
103
104
105
106static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
107{
108 assert(spapr->vsmt);
109 return
110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
111}
112static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
113 PowerPCCPU *cpu)
114{
115 assert(spapr->vsmt);
116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
117}
118
119static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
120{
121
122
123
124
125 return false;
126}
127
128static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
129 .name = "icp/server",
130 .version_id = 1,
131 .minimum_version_id = 1,
132 .needed = pre_2_10_vmstate_dummy_icp_needed,
133 .fields = (VMStateField[]) {
134 VMSTATE_UNUSED(4),
135 VMSTATE_UNUSED(1),
136 VMSTATE_UNUSED(1),
137 VMSTATE_END_OF_LIST()
138 },
139};
140
141static void pre_2_10_vmstate_register_dummy_icp(int i)
142{
143 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
144 (void *)(uintptr_t) i);
145}
146
147static void pre_2_10_vmstate_unregister_dummy_icp(int i)
148{
149 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
150 (void *)(uintptr_t) i);
151}
152
153int spapr_max_server_number(SpaprMachineState *spapr)
154{
155 assert(spapr->vsmt);
156 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads);
157}
158
159static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
160 int smt_threads)
161{
162 int i, ret = 0;
163 uint32_t servers_prop[smt_threads];
164 uint32_t gservers_prop[smt_threads * 2];
165 int index = spapr_get_vcpu_id(cpu);
166
167 if (cpu->compat_pvr) {
168 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
169 if (ret < 0) {
170 return ret;
171 }
172 }
173
174
175 for (i = 0; i < smt_threads; i++) {
176 servers_prop[i] = cpu_to_be32(index + i);
177
178 gservers_prop[i*2] = cpu_to_be32(index + i);
179 gservers_prop[i*2 + 1] = 0;
180 }
181 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
182 servers_prop, sizeof(servers_prop));
183 if (ret < 0) {
184 return ret;
185 }
186 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
187 gservers_prop, sizeof(gservers_prop));
188
189 return ret;
190}
191
192static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
193{
194 int index = spapr_get_vcpu_id(cpu);
195 uint32_t associativity[] = {cpu_to_be32(0x5),
196 cpu_to_be32(0x0),
197 cpu_to_be32(0x0),
198 cpu_to_be32(0x0),
199 cpu_to_be32(cpu->node_id),
200 cpu_to_be32(index)};
201
202
203 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
204 sizeof(associativity));
205}
206
207
208static void spapr_populate_pa_features(SpaprMachineState *spapr,
209 PowerPCCPU *cpu,
210 void *fdt, int offset,
211 bool legacy_guest)
212{
213 uint8_t pa_features_206[] = { 6, 0,
214 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
215 uint8_t pa_features_207[] = { 24, 0,
216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
217 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
218 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
219 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
220 uint8_t pa_features_300[] = { 66, 0,
221
222
223 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
224
225 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
226
227 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
228
229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
230
231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
232
233 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00,
234
235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
236
237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
238
239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
240
241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
242
243 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
244 };
245 uint8_t *pa_features = NULL;
246 size_t pa_size;
247
248 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
249 pa_features = pa_features_206;
250 pa_size = sizeof(pa_features_206);
251 }
252 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
253 pa_features = pa_features_207;
254 pa_size = sizeof(pa_features_207);
255 }
256 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
257 pa_features = pa_features_300;
258 pa_size = sizeof(pa_features_300);
259 }
260 if (!pa_features) {
261 return;
262 }
263
264 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
265
266
267
268
269
270
271
272 pa_features[3] |= 0x20;
273 }
274 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
275 pa_features[24] |= 0x80;
276 }
277 if (legacy_guest && pa_size > 40) {
278
279
280
281 pa_features[40 + 2] &= ~0x80;
282 }
283
284 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
285}
286
287static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineState *spapr)
288{
289 int ret = 0, offset, cpus_offset;
290 CPUState *cs;
291 char cpu_model[32];
292 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
293
294 CPU_FOREACH(cs) {
295 PowerPCCPU *cpu = POWERPC_CPU(cs);
296 DeviceClass *dc = DEVICE_GET_CLASS(cs);
297 int index = spapr_get_vcpu_id(cpu);
298 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
299
300 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
301 continue;
302 }
303
304 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
305
306 cpus_offset = fdt_path_offset(fdt, "/cpus");
307 if (cpus_offset < 0) {
308 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
309 if (cpus_offset < 0) {
310 return cpus_offset;
311 }
312 }
313 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
314 if (offset < 0) {
315 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
316 if (offset < 0) {
317 return offset;
318 }
319 }
320
321 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
322 pft_size_prop, sizeof(pft_size_prop));
323 if (ret < 0) {
324 return ret;
325 }
326
327 if (nb_numa_nodes > 1) {
328 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
329 if (ret < 0) {
330 return ret;
331 }
332 }
333
334 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
335 if (ret < 0) {
336 return ret;
337 }
338
339 spapr_populate_pa_features(spapr, cpu, fdt, offset,
340 spapr->cas_legacy_guest_workaround);
341 }
342 return ret;
343}
344
345static hwaddr spapr_node0_size(MachineState *machine)
346{
347 if (nb_numa_nodes) {
348 int i;
349 for (i = 0; i < nb_numa_nodes; ++i) {
350 if (numa_info[i].node_mem) {
351 return MIN(pow2floor(numa_info[i].node_mem),
352 machine->ram_size);
353 }
354 }
355 }
356 return machine->ram_size;
357}
358
359static void add_str(GString *s, const gchar *s1)
360{
361 g_string_append_len(s, s1, strlen(s1) + 1);
362}
363
364static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
365 hwaddr size)
366{
367 uint32_t associativity[] = {
368 cpu_to_be32(0x4),
369 cpu_to_be32(0x0), cpu_to_be32(0x0),
370 cpu_to_be32(0x0), cpu_to_be32(nodeid)
371 };
372 char mem_name[32];
373 uint64_t mem_reg_property[2];
374 int off;
375
376 mem_reg_property[0] = cpu_to_be64(start);
377 mem_reg_property[1] = cpu_to_be64(size);
378
379 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
380 off = fdt_add_subnode(fdt, 0, mem_name);
381 _FDT(off);
382 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
383 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
384 sizeof(mem_reg_property))));
385 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
386 sizeof(associativity))));
387 return off;
388}
389
390static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt)
391{
392 MachineState *machine = MACHINE(spapr);
393 hwaddr mem_start, node_size;
394 int i, nb_nodes = nb_numa_nodes;
395 NodeInfo *nodes = numa_info;
396 NodeInfo ramnode;
397
398
399 if (!nb_numa_nodes) {
400 nb_nodes = 1;
401 ramnode.node_mem = machine->ram_size;
402 nodes = &ramnode;
403 }
404
405 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
406 if (!nodes[i].node_mem) {
407 continue;
408 }
409 if (mem_start >= machine->ram_size) {
410 node_size = 0;
411 } else {
412 node_size = nodes[i].node_mem;
413 if (node_size > machine->ram_size - mem_start) {
414 node_size = machine->ram_size - mem_start;
415 }
416 }
417 if (!mem_start) {
418
419
420 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
421 mem_start += spapr->rma_size;
422 node_size -= spapr->rma_size;
423 }
424 for ( ; node_size; ) {
425 hwaddr sizetmp = pow2floor(node_size);
426
427
428 if (ctzl(mem_start) < ctzl(sizetmp)) {
429 sizetmp = 1ULL << ctzl(mem_start);
430 }
431
432 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
433 node_size -= sizetmp;
434 mem_start += sizetmp;
435 }
436 }
437
438 return 0;
439}
440
441static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
442 SpaprMachineState *spapr)
443{
444 PowerPCCPU *cpu = POWERPC_CPU(cs);
445 CPUPPCState *env = &cpu->env;
446 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
447 int index = spapr_get_vcpu_id(cpu);
448 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
449 0xffffffff, 0xffffffff};
450 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
451 : SPAPR_TIMEBASE_FREQ;
452 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
453 uint32_t page_sizes_prop[64];
454 size_t page_sizes_prop_size;
455 uint32_t vcpus_per_socket = smp_threads * smp_cores;
456 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
457 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
458 SpaprDrc *drc;
459 int drc_index;
460 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
461 int i;
462
463 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
464 if (drc) {
465 drc_index = spapr_drc_index(drc);
466 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
467 }
468
469 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
470 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
471
472 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
473 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
474 env->dcache_line_size)));
475 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
476 env->dcache_line_size)));
477 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
478 env->icache_line_size)));
479 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
480 env->icache_line_size)));
481
482 if (pcc->l1_dcache_size) {
483 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
484 pcc->l1_dcache_size)));
485 } else {
486 warn_report("Unknown L1 dcache size for cpu");
487 }
488 if (pcc->l1_icache_size) {
489 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
490 pcc->l1_icache_size)));
491 } else {
492 warn_report("Unknown L1 icache size for cpu");
493 }
494
495 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
496 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
497 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
498 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
499 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
500 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
501
502 if (env->spr_cb[SPR_PURR].oea_read) {
503 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
504 }
505
506 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
507 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
508 segs, sizeof(segs))));
509 }
510
511
512
513
514
515
516
517 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
518 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
519 } else {
520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
521 }
522
523
524
525
526 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
527 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
528 }
529
530 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
531 sizeof(page_sizes_prop));
532 if (page_sizes_prop_size) {
533 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
534 page_sizes_prop, page_sizes_prop_size)));
535 }
536
537 spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
538
539 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
540 cs->cpu_index / vcpus_per_socket)));
541
542 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
543 pft_size_prop, sizeof(pft_size_prop))));
544
545 if (nb_numa_nodes > 1) {
546 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
547 }
548
549 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
550
551 if (pcc->radix_page_info) {
552 for (i = 0; i < pcc->radix_page_info->count; i++) {
553 radix_AP_encodings[i] =
554 cpu_to_be32(pcc->radix_page_info->entries[i]);
555 }
556 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
557 radix_AP_encodings,
558 pcc->radix_page_info->count *
559 sizeof(radix_AP_encodings[0]))));
560 }
561
562
563
564
565
566 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
567 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
568 pcc->lrg_decr_bits)));
569}
570
571static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr)
572{
573 CPUState **rev;
574 CPUState *cs;
575 int n_cpus;
576 int cpus_offset;
577 char *nodename;
578 int i;
579
580 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
581 _FDT(cpus_offset);
582 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
583 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
584
585
586
587
588
589
590
591
592
593 n_cpus = 0;
594 rev = NULL;
595 CPU_FOREACH(cs) {
596 rev = g_renew(CPUState *, rev, n_cpus + 1);
597 rev[n_cpus++] = cs;
598 }
599
600 for (i = n_cpus - 1; i >= 0; i--) {
601 CPUState *cs = rev[i];
602 PowerPCCPU *cpu = POWERPC_CPU(cs);
603 int index = spapr_get_vcpu_id(cpu);
604 DeviceClass *dc = DEVICE_GET_CLASS(cs);
605 int offset;
606
607 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
608 continue;
609 }
610
611 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
612 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
613 g_free(nodename);
614 _FDT(offset);
615 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
616 }
617
618 g_free(rev);
619}
620
621static int spapr_rng_populate_dt(void *fdt)
622{
623 int node;
624 int ret;
625
626 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
627 if (node <= 0) {
628 return -1;
629 }
630 ret = fdt_setprop_string(fdt, node, "device_type",
631 "ibm,platform-facilities");
632 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
633 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
634
635 node = fdt_add_subnode(fdt, node, "ibm,random-v1");
636 if (node <= 0) {
637 return -1;
638 }
639 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
640
641 return ret ? -1 : 0;
642}
643
644static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
645{
646 MemoryDeviceInfoList *info;
647
648 for (info = list; info; info = info->next) {
649 MemoryDeviceInfo *value = info->value;
650
651 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
652 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
653
654 if (addr >= pcdimm_info->addr &&
655 addr < (pcdimm_info->addr + pcdimm_info->size)) {
656 return pcdimm_info->node;
657 }
658 }
659 }
660
661 return -1;
662}
663
664struct sPAPRDrconfCellV2 {
665 uint32_t seq_lmbs;
666 uint64_t base_addr;
667 uint32_t drc_index;
668 uint32_t aa_index;
669 uint32_t flags;
670} QEMU_PACKED;
671
672typedef struct DrconfCellQueue {
673 struct sPAPRDrconfCellV2 cell;
674 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
675} DrconfCellQueue;
676
677static DrconfCellQueue *
678spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
679 uint32_t drc_index, uint32_t aa_index,
680 uint32_t flags)
681{
682 DrconfCellQueue *elem;
683
684 elem = g_malloc0(sizeof(*elem));
685 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
686 elem->cell.base_addr = cpu_to_be64(base_addr);
687 elem->cell.drc_index = cpu_to_be32(drc_index);
688 elem->cell.aa_index = cpu_to_be32(aa_index);
689 elem->cell.flags = cpu_to_be32(flags);
690
691 return elem;
692}
693
694
695static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt,
696 int offset, MemoryDeviceInfoList *dimms)
697{
698 MachineState *machine = MACHINE(spapr);
699 uint8_t *int_buf, *cur_index;
700 int ret;
701 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
702 uint64_t addr, cur_addr, size;
703 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
704 uint64_t mem_end = machine->device_memory->base +
705 memory_region_size(&machine->device_memory->mr);
706 uint32_t node, buf_len, nr_entries = 0;
707 SpaprDrc *drc;
708 DrconfCellQueue *elem, *next;
709 MemoryDeviceInfoList *info;
710 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
711 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
712
713
714 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
715 SPAPR_LMB_FLAGS_RESERVED |
716 SPAPR_LMB_FLAGS_DRC_INVALID);
717 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
718 nr_entries++;
719
720 cur_addr = machine->device_memory->base;
721 for (info = dimms; info; info = info->next) {
722 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
723
724 addr = di->addr;
725 size = di->size;
726 node = di->node;
727
728
729 if (cur_addr < addr) {
730 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
731 g_assert(drc);
732 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
733 cur_addr, spapr_drc_index(drc), -1, 0);
734 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
735 nr_entries++;
736 }
737
738
739 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
740 g_assert(drc);
741 elem = spapr_get_drconf_cell(size / lmb_size, addr,
742 spapr_drc_index(drc), node,
743 SPAPR_LMB_FLAGS_ASSIGNED);
744 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
745 nr_entries++;
746 cur_addr = addr + size;
747 }
748
749
750 if (cur_addr < mem_end) {
751 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
752 g_assert(drc);
753 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
754 cur_addr, spapr_drc_index(drc), -1, 0);
755 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
756 nr_entries++;
757 }
758
759 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
760 int_buf = cur_index = g_malloc0(buf_len);
761 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
762 cur_index += sizeof(nr_entries);
763
764 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
765 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
766 cur_index += sizeof(elem->cell);
767 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
768 g_free(elem);
769 }
770
771 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
772 g_free(int_buf);
773 if (ret < 0) {
774 return -1;
775 }
776 return 0;
777}
778
779
780static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt,
781 int offset, MemoryDeviceInfoList *dimms)
782{
783 MachineState *machine = MACHINE(spapr);
784 int i, ret;
785 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
786 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
787 uint32_t nr_lmbs = (machine->device_memory->base +
788 memory_region_size(&machine->device_memory->mr)) /
789 lmb_size;
790 uint32_t *int_buf, *cur_index, buf_len;
791
792
793
794
795 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
796 cur_index = int_buf = g_malloc0(buf_len);
797 int_buf[0] = cpu_to_be32(nr_lmbs);
798 cur_index++;
799 for (i = 0; i < nr_lmbs; i++) {
800 uint64_t addr = i * lmb_size;
801 uint32_t *dynamic_memory = cur_index;
802
803 if (i >= device_lmb_start) {
804 SpaprDrc *drc;
805
806 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
807 g_assert(drc);
808
809 dynamic_memory[0] = cpu_to_be32(addr >> 32);
810 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
811 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
812 dynamic_memory[3] = cpu_to_be32(0);
813 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
814 if (memory_region_present(get_system_memory(), addr)) {
815 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
816 } else {
817 dynamic_memory[5] = cpu_to_be32(0);
818 }
819 } else {
820
821
822
823
824
825 dynamic_memory[0] = cpu_to_be32(addr >> 32);
826 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
827 dynamic_memory[2] = cpu_to_be32(0);
828 dynamic_memory[3] = cpu_to_be32(0);
829 dynamic_memory[4] = cpu_to_be32(-1);
830 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
831 SPAPR_LMB_FLAGS_DRC_INVALID);
832 }
833
834 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
835 }
836 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
837 g_free(int_buf);
838 if (ret < 0) {
839 return -1;
840 }
841 return 0;
842}
843
844
845
846
847
848
849static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt)
850{
851 MachineState *machine = MACHINE(spapr);
852 int ret, i, offset;
853 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
854 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
855 uint32_t *int_buf, *cur_index, buf_len;
856 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
857 MemoryDeviceInfoList *dimms = NULL;
858
859
860
861
862 if (machine->ram_size == machine->maxram_size) {
863 return 0;
864 }
865
866 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
867
868 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
869 sizeof(prop_lmb_size));
870 if (ret < 0) {
871 return ret;
872 }
873
874 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
875 if (ret < 0) {
876 return ret;
877 }
878
879 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
880 if (ret < 0) {
881 return ret;
882 }
883
884
885 dimms = qmp_memory_device_list();
886 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
887 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
888 } else {
889 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
890 }
891 qapi_free_MemoryDeviceInfoList(dimms);
892
893 if (ret < 0) {
894 return ret;
895 }
896
897
898 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
899 cur_index = int_buf = g_malloc0(buf_len);
900 int_buf[0] = cpu_to_be32(nr_nodes);
901 int_buf[1] = cpu_to_be32(4);
902 cur_index += 2;
903 for (i = 0; i < nr_nodes; i++) {
904 uint32_t associativity[] = {
905 cpu_to_be32(0x0),
906 cpu_to_be32(0x0),
907 cpu_to_be32(0x0),
908 cpu_to_be32(i)
909 };
910 memcpy(cur_index, associativity, sizeof(associativity));
911 cur_index += 4;
912 }
913 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
914 (cur_index - int_buf) * sizeof(uint32_t));
915 g_free(int_buf);
916
917 return ret;
918}
919
920static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt,
921 SpaprOptionVector *ov5_updates)
922{
923 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
924 int ret = 0, offset;
925
926
927 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
928 g_assert(smc->dr_lmb_enabled);
929 ret = spapr_populate_drconf_memory(spapr, fdt);
930 if (ret) {
931 goto out;
932 }
933 }
934
935 offset = fdt_path_offset(fdt, "/chosen");
936 if (offset < 0) {
937 offset = fdt_add_subnode(fdt, 0, "chosen");
938 if (offset < 0) {
939 return offset;
940 }
941 }
942 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
943 "ibm,architecture-vec-5");
944
945out:
946 return ret;
947}
948
949static bool spapr_hotplugged_dev_before_cas(void)
950{
951 Object *drc_container, *obj;
952 ObjectProperty *prop;
953 ObjectPropertyIterator iter;
954
955 drc_container = container_get(object_get_root(), "/dr-connector");
956 object_property_iter_init(&iter, drc_container);
957 while ((prop = object_property_iter_next(&iter))) {
958 if (!strstart(prop->type, "link<", NULL)) {
959 continue;
960 }
961 obj = object_property_get_link(drc_container, prop->name, NULL);
962 if (spapr_drc_needed(obj)) {
963 return true;
964 }
965 }
966 return false;
967}
968
969int spapr_h_cas_compose_response(SpaprMachineState *spapr,
970 target_ulong addr, target_ulong size,
971 SpaprOptionVector *ov5_updates)
972{
973 void *fdt, *fdt_skel;
974 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };
975
976 if (spapr_hotplugged_dev_before_cas()) {
977 return 1;
978 }
979
980 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
981 error_report("SLOF provided an unexpected CAS buffer size "
982 TARGET_FMT_lu " (min: %zu, max: %u)",
983 size, sizeof(hdr), FW_MAX_SIZE);
984 exit(EXIT_FAILURE);
985 }
986
987 size -= sizeof(hdr);
988
989
990 fdt_skel = g_malloc0(size);
991 _FDT((fdt_create(fdt_skel, size)));
992 _FDT((fdt_finish_reservemap(fdt_skel)));
993 _FDT((fdt_begin_node(fdt_skel, "")));
994 _FDT((fdt_end_node(fdt_skel)));
995 _FDT((fdt_finish(fdt_skel)));
996 fdt = g_malloc0(size);
997 _FDT((fdt_open_into(fdt_skel, fdt, size)));
998 g_free(fdt_skel);
999
1000
1001 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
1002
1003 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
1004 return -1;
1005 }
1006
1007
1008 _FDT((fdt_pack(fdt)));
1009
1010 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
1011 trace_spapr_cas_failed(size);
1012 return -1;
1013 }
1014
1015 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
1016 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
1017 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
1018 g_free(fdt);
1019
1020 return 0;
1021}
1022
1023static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
1024{
1025 int rtas;
1026 GString *hypertas = g_string_sized_new(256);
1027 GString *qemu_hypertas = g_string_sized_new(256);
1028 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1029 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
1030 memory_region_size(&MACHINE(spapr)->device_memory->mr);
1031 uint32_t lrdr_capacity[] = {
1032 cpu_to_be32(max_device_addr >> 32),
1033 cpu_to_be32(max_device_addr & 0xffffffff),
1034 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
1035 cpu_to_be32(max_cpus / smp_threads),
1036 };
1037 uint32_t maxdomains[] = {
1038 cpu_to_be32(4),
1039 cpu_to_be32(0),
1040 cpu_to_be32(0),
1041 cpu_to_be32(0),
1042 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes : 1),
1043 };
1044
1045 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
1046
1047
1048 add_str(hypertas, "hcall-pft");
1049 add_str(hypertas, "hcall-term");
1050 add_str(hypertas, "hcall-dabr");
1051 add_str(hypertas, "hcall-interrupt");
1052 add_str(hypertas, "hcall-tce");
1053 add_str(hypertas, "hcall-vio");
1054 add_str(hypertas, "hcall-splpar");
1055 add_str(hypertas, "hcall-bulk");
1056 add_str(hypertas, "hcall-set-mode");
1057 add_str(hypertas, "hcall-sprg0");
1058 add_str(hypertas, "hcall-copy");
1059 add_str(hypertas, "hcall-debug");
1060 add_str(hypertas, "hcall-vphn");
1061 add_str(qemu_hypertas, "hcall-memop1");
1062
1063 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1064 add_str(hypertas, "hcall-multi-tce");
1065 }
1066
1067 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
1068 add_str(hypertas, "hcall-hpt-resize");
1069 }
1070
1071 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
1072 hypertas->str, hypertas->len));
1073 g_string_free(hypertas, TRUE);
1074 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
1075 qemu_hypertas->str, qemu_hypertas->len));
1076 g_string_free(qemu_hypertas, TRUE);
1077
1078 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
1079 refpoints, sizeof(refpoints)));
1080
1081 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
1082 maxdomains, sizeof(maxdomains)));
1083
1084 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
1085 RTAS_ERROR_LOG_MAX));
1086 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
1087 RTAS_EVENT_SCAN_RATE));
1088
1089 g_assert(msi_nonbroken);
1090 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
1091
1092
1093
1094
1095
1096
1097
1098
1099 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
1100
1101 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
1102 lrdr_capacity, sizeof(lrdr_capacity)));
1103
1104 spapr_dt_rtas_tokens(fdt, rtas);
1105}
1106
1107
1108
1109
1110
1111
1112static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
1113 int chosen)
1114{
1115 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1116
1117 char val[2 * 4] = {
1118 23, spapr->irq->ov5,
1119 24, 0x00,
1120 25, 0x00,
1121 26, 0x40,
1122 };
1123
1124 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1125 first_ppc_cpu->compat_pvr)) {
1126
1127
1128
1129
1130 val[1] = 0x00;
1131 val[3] = 0x00;
1132 } else if (kvm_enabled()) {
1133 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1134 val[3] = 0x80;
1135 } else if (kvmppc_has_cap_mmu_radix()) {
1136 val[3] = 0x40;
1137 } else {
1138 val[3] = 0x00;
1139 }
1140 } else {
1141
1142 val[3] = 0xC0;
1143 }
1144 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1145 val, sizeof(val)));
1146}
1147
1148static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt)
1149{
1150 MachineState *machine = MACHINE(spapr);
1151 int chosen;
1152 const char *boot_device = machine->boot_order;
1153 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1154 size_t cb = 0;
1155 char *bootlist = get_boot_devices_list(&cb);
1156
1157 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1158
1159 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1160 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1161 spapr->initrd_base));
1162 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1163 spapr->initrd_base + spapr->initrd_size));
1164
1165 if (spapr->kernel_size) {
1166 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1167 cpu_to_be64(spapr->kernel_size) };
1168
1169 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1170 &kprop, sizeof(kprop)));
1171 if (spapr->kernel_le) {
1172 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1173 }
1174 }
1175 if (boot_menu) {
1176 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1177 }
1178 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1179 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1180 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1181
1182 if (cb && bootlist) {
1183 int i;
1184
1185 for (i = 0; i < cb; i++) {
1186 if (bootlist[i] == '\n') {
1187 bootlist[i] = ' ';
1188 }
1189 }
1190 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1191 }
1192
1193 if (boot_device && strlen(boot_device)) {
1194 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1195 }
1196
1197 if (!spapr->has_graphics && stdout_path) {
1198
1199
1200
1201
1202
1203
1204 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1205 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1206 }
1207
1208 spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1209
1210 g_free(stdout_path);
1211 g_free(bootlist);
1212}
1213
1214static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
1215{
1216
1217
1218 int hypervisor;
1219 uint8_t hypercall[16];
1220
1221 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1222
1223 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1224 if (kvmppc_has_cap_fixup_hcalls()) {
1225
1226
1227
1228
1229 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1230 sizeof(hypercall))) {
1231 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1232 hypercall, sizeof(hypercall)));
1233 }
1234 }
1235}
1236
1237static void *spapr_build_fdt(SpaprMachineState *spapr)
1238{
1239 MachineState *machine = MACHINE(spapr);
1240 MachineClass *mc = MACHINE_GET_CLASS(machine);
1241 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1242 int ret;
1243 void *fdt;
1244 SpaprPhbState *phb;
1245 char *buf;
1246
1247 fdt = g_malloc0(FDT_MAX_SIZE);
1248 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1249
1250
1251 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1252 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1253 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1254
1255
1256 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1257 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1258 if (qemu_uuid_set) {
1259 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1260 }
1261 g_free(buf);
1262
1263 if (qemu_get_vm_name()) {
1264 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1265 qemu_get_vm_name()));
1266 }
1267
1268
1269 if (spapr->host_model) {
1270 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1271 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) {
1272 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1273 g_free(buf);
1274 }
1275
1276 if (spapr->host_serial) {
1277 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1278 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) {
1279 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1280 g_free(buf);
1281 }
1282
1283 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1284 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1285
1286
1287 spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt,
1288 PHANDLE_INTC);
1289
1290 ret = spapr_populate_memory(spapr, fdt);
1291 if (ret < 0) {
1292 error_report("couldn't setup memory nodes in fdt");
1293 exit(1);
1294 }
1295
1296
1297 spapr_dt_vdevice(spapr->vio_bus, fdt);
1298
1299 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1300 ret = spapr_rng_populate_dt(fdt);
1301 if (ret < 0) {
1302 error_report("could not set up rng device in the fdt");
1303 exit(1);
1304 }
1305 }
1306
1307 QLIST_FOREACH(phb, &spapr->phbs, list) {
1308 ret = spapr_populate_pci_dt(phb, PHANDLE_INTC, fdt,
1309 spapr->irq->nr_msis, NULL);
1310 if (ret < 0) {
1311 error_report("couldn't setup PCI devices in fdt");
1312 exit(1);
1313 }
1314 }
1315
1316
1317 spapr_populate_cpus_dt_node(fdt, spapr);
1318
1319 if (smc->dr_lmb_enabled) {
1320 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1321 }
1322
1323 if (mc->has_hotpluggable_cpus) {
1324 int offset = fdt_path_offset(fdt, "/cpus");
1325 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1326 SPAPR_DR_CONNECTOR_TYPE_CPU);
1327 if (ret < 0) {
1328 error_report("Couldn't set up CPU DR device tree properties");
1329 exit(1);
1330 }
1331 }
1332
1333
1334 spapr_dt_events(spapr, fdt);
1335
1336
1337 spapr_dt_rtas(spapr, fdt);
1338
1339
1340 spapr_dt_chosen(spapr, fdt);
1341
1342
1343 if (kvm_enabled()) {
1344 spapr_dt_hypervisor(spapr, fdt);
1345 }
1346
1347
1348 if (spapr->kernel_size) {
1349 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1350 }
1351 if (spapr->initrd_size) {
1352 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1353 }
1354
1355
1356 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1357 if (ret < 0) {
1358 error_report("couldn't setup CAS properties fdt");
1359 exit(1);
1360 }
1361
1362 if (smc->dr_phb_enabled) {
1363 ret = spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
1364 if (ret < 0) {
1365 error_report("Couldn't set up PHB DR device tree properties");
1366 exit(1);
1367 }
1368 }
1369
1370 return fdt;
1371}
1372
1373static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1374{
1375 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1376}
1377
1378static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1379 PowerPCCPU *cpu)
1380{
1381 CPUPPCState *env = &cpu->env;
1382
1383
1384 g_assert(qemu_mutex_iothread_locked());
1385
1386 if (msr_pr) {
1387 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1388 env->gpr[3] = H_PRIVILEGE;
1389 } else {
1390 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1391 }
1392}
1393
1394struct LPCRSyncState {
1395 target_ulong value;
1396 target_ulong mask;
1397};
1398
1399static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
1400{
1401 struct LPCRSyncState *s = arg.host_ptr;
1402 PowerPCCPU *cpu = POWERPC_CPU(cs);
1403 CPUPPCState *env = &cpu->env;
1404 target_ulong lpcr;
1405
1406 cpu_synchronize_state(cs);
1407 lpcr = env->spr[SPR_LPCR];
1408 lpcr &= ~s->mask;
1409 lpcr |= s->value;
1410 ppc_store_lpcr(cpu, lpcr);
1411}
1412
1413void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
1414{
1415 CPUState *cs;
1416 struct LPCRSyncState s = {
1417 .value = value,
1418 .mask = mask
1419 };
1420 CPU_FOREACH(cs) {
1421 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
1422 }
1423}
1424
1425static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
1426{
1427 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1428
1429
1430 entry->dw0 = spapr->patb_entry & PATE0_HR;
1431 entry->dw1 = spapr->patb_entry;
1432}
1433
1434#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1435#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1436#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1437#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1438#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1439
1440
1441
1442
1443static int get_htab_fd(SpaprMachineState *spapr)
1444{
1445 Error *local_err = NULL;
1446
1447 if (spapr->htab_fd >= 0) {
1448 return spapr->htab_fd;
1449 }
1450
1451 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1452 if (spapr->htab_fd < 0) {
1453 error_report_err(local_err);
1454 }
1455
1456 return spapr->htab_fd;
1457}
1458
1459void close_htab_fd(SpaprMachineState *spapr)
1460{
1461 if (spapr->htab_fd >= 0) {
1462 close(spapr->htab_fd);
1463 }
1464 spapr->htab_fd = -1;
1465}
1466
1467static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1468{
1469 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1470
1471 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1472}
1473
1474static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1475{
1476 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1477
1478 assert(kvm_enabled());
1479
1480 if (!spapr->htab) {
1481 return 0;
1482 }
1483
1484 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1485}
1486
1487static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1488 hwaddr ptex, int n)
1489{
1490 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1491 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1492
1493 if (!spapr->htab) {
1494
1495
1496
1497 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1498 kvmppc_read_hptes(hptes, ptex, n);
1499 return hptes;
1500 }
1501
1502
1503
1504
1505
1506 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1507}
1508
1509static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1510 const ppc_hash_pte64_t *hptes,
1511 hwaddr ptex, int n)
1512{
1513 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1514
1515 if (!spapr->htab) {
1516 g_free((void *)hptes);
1517 }
1518
1519
1520}
1521
1522static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1523 uint64_t pte0, uint64_t pte1)
1524{
1525 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1526 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1527
1528 if (!spapr->htab) {
1529 kvmppc_write_hpte(ptex, pte0, pte1);
1530 } else {
1531 if (pte0 & HPTE64_V_VALID) {
1532 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1533
1534
1535
1536
1537
1538 smp_wmb();
1539 stq_p(spapr->htab + offset, pte0);
1540 } else {
1541 stq_p(spapr->htab + offset, pte0);
1542
1543
1544
1545
1546
1547 smp_wmb();
1548 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1549 }
1550 }
1551}
1552
1553int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1554{
1555 int shift;
1556
1557
1558
1559
1560 shift = ctz64(pow2ceil(ramsize)) - 7;
1561 shift = MAX(shift, 18);
1562 shift = MIN(shift, 46);
1563 return shift;
1564}
1565
1566void spapr_free_hpt(SpaprMachineState *spapr)
1567{
1568 g_free(spapr->htab);
1569 spapr->htab = NULL;
1570 spapr->htab_shift = 0;
1571 close_htab_fd(spapr);
1572}
1573
1574void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
1575 Error **errp)
1576{
1577 long rc;
1578
1579
1580 spapr_free_hpt(spapr);
1581
1582 rc = kvmppc_reset_htab(shift);
1583 if (rc < 0) {
1584
1585 error_setg_errno(errp, errno,
1586 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1587 shift);
1588
1589
1590 } else if (rc > 0) {
1591
1592 if (rc != shift) {
1593 error_setg(errp,
1594 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1595 shift, rc);
1596 }
1597
1598 spapr->htab_shift = shift;
1599 spapr->htab = NULL;
1600 } else {
1601
1602 size_t size = 1ULL << shift;
1603 int i;
1604
1605 spapr->htab = qemu_memalign(size, size);
1606 if (!spapr->htab) {
1607 error_setg_errno(errp, errno,
1608 "Could not allocate HPT of order %d", shift);
1609 return;
1610 }
1611
1612 memset(spapr->htab, 0, size);
1613 spapr->htab_shift = shift;
1614
1615 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1616 DIRTY_HPTE(HPTE(spapr->htab, i));
1617 }
1618 }
1619
1620 spapr->patb_entry = 0;
1621 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
1622}
1623
1624void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr)
1625{
1626 int hpt_shift;
1627
1628 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1629 || (spapr->cas_reboot
1630 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1631 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1632 } else {
1633 uint64_t current_ram_size;
1634
1635 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1636 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1637 }
1638 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1639
1640 if (spapr->vrma_adjust) {
1641 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1642 spapr->htab_shift);
1643 }
1644}
1645
1646static int spapr_reset_drcs(Object *child, void *opaque)
1647{
1648 SpaprDrc *drc =
1649 (SpaprDrc *) object_dynamic_cast(child,
1650 TYPE_SPAPR_DR_CONNECTOR);
1651
1652 if (drc) {
1653 spapr_drc_reset(drc);
1654 }
1655
1656 return 0;
1657}
1658
1659static void spapr_machine_reset(void)
1660{
1661 MachineState *machine = MACHINE(qdev_get_machine());
1662 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
1663 PowerPCCPU *first_ppc_cpu;
1664 uint32_t rtas_limit;
1665 hwaddr rtas_addr, fdt_addr;
1666 void *fdt;
1667 int rc;
1668
1669 spapr_caps_apply(spapr);
1670
1671 first_ppc_cpu = POWERPC_CPU(first_cpu);
1672 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1673 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1674 spapr->max_compat_pvr)) {
1675
1676
1677
1678
1679
1680 spapr->patb_entry = PATE1_GR;
1681 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
1682 } else {
1683 spapr_setup_hpt_and_vrma(spapr);
1684 }
1685
1686
1687
1688
1689
1690 if (!spapr->cas_reboot) {
1691 spapr_ovec_cleanup(spapr->ov5_cas);
1692 spapr->ov5_cas = spapr_ovec_new();
1693
1694 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1695 }
1696
1697 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
1698 spapr_irq_msi_reset(spapr);
1699 }
1700
1701 qemu_devices_reset();
1702
1703
1704
1705
1706
1707 spapr_irq_reset(spapr, &error_fatal);
1708
1709
1710
1711
1712
1713
1714 if (qtest_enabled()) {
1715 spapr_ovec_cleanup(spapr->ov5_cas);
1716 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
1717 }
1718
1719
1720
1721
1722
1723
1724 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1725
1726 spapr_clear_pending_events(spapr);
1727
1728
1729
1730
1731
1732
1733 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1734 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1735 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1736
1737 fdt = spapr_build_fdt(spapr);
1738
1739 spapr_load_rtas(spapr, fdt, rtas_addr);
1740
1741 rc = fdt_pack(fdt);
1742
1743
1744 assert(rc == 0);
1745
1746 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1747 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1748 fdt_totalsize(fdt), FDT_MAX_SIZE);
1749 exit(1);
1750 }
1751
1752
1753 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1754 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1755 g_free(spapr->fdt_blob);
1756 spapr->fdt_size = fdt_totalsize(fdt);
1757 spapr->fdt_initial_size = spapr->fdt_size;
1758 spapr->fdt_blob = fdt;
1759
1760
1761 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
1762 first_ppc_cpu->env.gpr[5] = 0;
1763
1764 spapr->cas_reboot = false;
1765}
1766
1767static void spapr_create_nvram(SpaprMachineState *spapr)
1768{
1769 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1770 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1771
1772 if (dinfo) {
1773 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1774 &error_fatal);
1775 }
1776
1777 qdev_init_nofail(dev);
1778
1779 spapr->nvram = (struct SpaprNvram *)dev;
1780}
1781
1782static void spapr_rtc_create(SpaprMachineState *spapr)
1783{
1784 object_initialize_child(OBJECT(spapr), "rtc",
1785 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC,
1786 &error_fatal, NULL);
1787 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1788 &error_fatal);
1789 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1790 "date", &error_fatal);
1791}
1792
1793
1794static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1795{
1796 switch (vga_interface_type) {
1797 case VGA_NONE:
1798 return false;
1799 case VGA_DEVICE:
1800 return true;
1801 case VGA_STD:
1802 case VGA_VIRTIO:
1803 case VGA_CIRRUS:
1804 return pci_vga_init(pci_bus) != NULL;
1805 default:
1806 error_setg(errp,
1807 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1808 return false;
1809 }
1810}
1811
1812static int spapr_pre_load(void *opaque)
1813{
1814 int rc;
1815
1816 rc = spapr_caps_pre_load(opaque);
1817 if (rc) {
1818 return rc;
1819 }
1820
1821 return 0;
1822}
1823
1824static int spapr_post_load(void *opaque, int version_id)
1825{
1826 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1827 int err = 0;
1828
1829 err = spapr_caps_post_migration(spapr);
1830 if (err) {
1831 return err;
1832 }
1833
1834
1835
1836
1837
1838
1839
1840 if (version_id < 3) {
1841 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1842 if (err) {
1843 return err;
1844 }
1845 }
1846
1847 if (kvm_enabled() && spapr->patb_entry) {
1848 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1849 bool radix = !!(spapr->patb_entry & PATE1_GR);
1850 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1851
1852
1853
1854
1855
1856 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0,
1857 LPCR_HR | LPCR_UPRT);
1858
1859 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1860 if (err) {
1861 error_report("Process table config unsupported by the host");
1862 return -EINVAL;
1863 }
1864 }
1865
1866 err = spapr_irq_post_load(spapr, version_id);
1867 if (err) {
1868 return err;
1869 }
1870
1871 return err;
1872}
1873
1874static int spapr_pre_save(void *opaque)
1875{
1876 int rc;
1877
1878 rc = spapr_caps_pre_save(opaque);
1879 if (rc) {
1880 return rc;
1881 }
1882
1883 return 0;
1884}
1885
1886static bool version_before_3(void *opaque, int version_id)
1887{
1888 return version_id < 3;
1889}
1890
1891static bool spapr_pending_events_needed(void *opaque)
1892{
1893 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1894 return !QTAILQ_EMPTY(&spapr->pending_events);
1895}
1896
1897static const VMStateDescription vmstate_spapr_event_entry = {
1898 .name = "spapr_event_log_entry",
1899 .version_id = 1,
1900 .minimum_version_id = 1,
1901 .fields = (VMStateField[]) {
1902 VMSTATE_UINT32(summary, SpaprEventLogEntry),
1903 VMSTATE_UINT32(extended_length, SpaprEventLogEntry),
1904 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0,
1905 NULL, extended_length),
1906 VMSTATE_END_OF_LIST()
1907 },
1908};
1909
1910static const VMStateDescription vmstate_spapr_pending_events = {
1911 .name = "spapr_pending_events",
1912 .version_id = 1,
1913 .minimum_version_id = 1,
1914 .needed = spapr_pending_events_needed,
1915 .fields = (VMStateField[]) {
1916 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1,
1917 vmstate_spapr_event_entry, SpaprEventLogEntry, next),
1918 VMSTATE_END_OF_LIST()
1919 },
1920};
1921
1922static bool spapr_ov5_cas_needed(void *opaque)
1923{
1924 SpaprMachineState *spapr = opaque;
1925 SpaprOptionVector *ov5_mask = spapr_ovec_new();
1926 SpaprOptionVector *ov5_legacy = spapr_ovec_new();
1927 SpaprOptionVector *ov5_removed = spapr_ovec_new();
1928 bool cas_needed;
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1956 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1957 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
1958
1959
1960
1961
1962
1963
1964 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1965 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1966
1967 spapr_ovec_cleanup(ov5_mask);
1968 spapr_ovec_cleanup(ov5_legacy);
1969 spapr_ovec_cleanup(ov5_removed);
1970
1971 return cas_needed;
1972}
1973
1974static const VMStateDescription vmstate_spapr_ov5_cas = {
1975 .name = "spapr_option_vector_ov5_cas",
1976 .version_id = 1,
1977 .minimum_version_id = 1,
1978 .needed = spapr_ov5_cas_needed,
1979 .fields = (VMStateField[]) {
1980 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1,
1981 vmstate_spapr_ovec, SpaprOptionVector),
1982 VMSTATE_END_OF_LIST()
1983 },
1984};
1985
1986static bool spapr_patb_entry_needed(void *opaque)
1987{
1988 SpaprMachineState *spapr = opaque;
1989
1990 return !!spapr->patb_entry;
1991}
1992
1993static const VMStateDescription vmstate_spapr_patb_entry = {
1994 .name = "spapr_patb_entry",
1995 .version_id = 1,
1996 .minimum_version_id = 1,
1997 .needed = spapr_patb_entry_needed,
1998 .fields = (VMStateField[]) {
1999 VMSTATE_UINT64(patb_entry, SpaprMachineState),
2000 VMSTATE_END_OF_LIST()
2001 },
2002};
2003
2004static bool spapr_irq_map_needed(void *opaque)
2005{
2006 SpaprMachineState *spapr = opaque;
2007
2008 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
2009}
2010
2011static const VMStateDescription vmstate_spapr_irq_map = {
2012 .name = "spapr_irq_map",
2013 .version_id = 1,
2014 .minimum_version_id = 1,
2015 .needed = spapr_irq_map_needed,
2016 .fields = (VMStateField[]) {
2017 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr),
2018 VMSTATE_END_OF_LIST()
2019 },
2020};
2021
2022static bool spapr_dtb_needed(void *opaque)
2023{
2024 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
2025
2026 return smc->update_dt_enabled;
2027}
2028
2029static int spapr_dtb_pre_load(void *opaque)
2030{
2031 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
2032
2033 g_free(spapr->fdt_blob);
2034 spapr->fdt_blob = NULL;
2035 spapr->fdt_size = 0;
2036
2037 return 0;
2038}
2039
2040static const VMStateDescription vmstate_spapr_dtb = {
2041 .name = "spapr_dtb",
2042 .version_id = 1,
2043 .minimum_version_id = 1,
2044 .needed = spapr_dtb_needed,
2045 .pre_load = spapr_dtb_pre_load,
2046 .fields = (VMStateField[]) {
2047 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState),
2048 VMSTATE_UINT32(fdt_size, SpaprMachineState),
2049 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL,
2050 fdt_size),
2051 VMSTATE_END_OF_LIST()
2052 },
2053};
2054
2055static const VMStateDescription vmstate_spapr = {
2056 .name = "spapr",
2057 .version_id = 3,
2058 .minimum_version_id = 1,
2059 .pre_load = spapr_pre_load,
2060 .post_load = spapr_post_load,
2061 .pre_save = spapr_pre_save,
2062 .fields = (VMStateField[]) {
2063
2064 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
2065
2066
2067 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3),
2068
2069 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2),
2070 VMSTATE_END_OF_LIST()
2071 },
2072 .subsections = (const VMStateDescription*[]) {
2073 &vmstate_spapr_ov5_cas,
2074 &vmstate_spapr_patb_entry,
2075 &vmstate_spapr_pending_events,
2076 &vmstate_spapr_cap_htm,
2077 &vmstate_spapr_cap_vsx,
2078 &vmstate_spapr_cap_dfp,
2079 &vmstate_spapr_cap_cfpc,
2080 &vmstate_spapr_cap_sbbc,
2081 &vmstate_spapr_cap_ibs,
2082 &vmstate_spapr_irq_map,
2083 &vmstate_spapr_cap_nested_kvm_hv,
2084 &vmstate_spapr_dtb,
2085 &vmstate_spapr_cap_large_decr,
2086 &vmstate_spapr_cap_ccf_assist,
2087 NULL
2088 }
2089};
2090
2091static int htab_save_setup(QEMUFile *f, void *opaque)
2092{
2093 SpaprMachineState *spapr = opaque;
2094
2095
2096 if (!spapr->htab_shift) {
2097 qemu_put_be32(f, -1);
2098 } else {
2099 qemu_put_be32(f, spapr->htab_shift);
2100 }
2101
2102 if (spapr->htab) {
2103 spapr->htab_save_index = 0;
2104 spapr->htab_first_pass = true;
2105 } else {
2106 if (spapr->htab_shift) {
2107 assert(kvm_enabled());
2108 }
2109 }
2110
2111
2112 return 0;
2113}
2114
2115static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr,
2116 int chunkstart, int n_valid, int n_invalid)
2117{
2118 qemu_put_be32(f, chunkstart);
2119 qemu_put_be16(f, n_valid);
2120 qemu_put_be16(f, n_invalid);
2121 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2122 HASH_PTE_SIZE_64 * n_valid);
2123}
2124
2125static void htab_save_end_marker(QEMUFile *f)
2126{
2127 qemu_put_be32(f, 0);
2128 qemu_put_be16(f, 0);
2129 qemu_put_be16(f, 0);
2130}
2131
2132static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr,
2133 int64_t max_ns)
2134{
2135 bool has_timeout = max_ns != -1;
2136 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2137 int index = spapr->htab_save_index;
2138 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2139
2140 assert(spapr->htab_first_pass);
2141
2142 do {
2143 int chunkstart;
2144
2145
2146 while ((index < htabslots)
2147 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2148 CLEAN_HPTE(HPTE(spapr->htab, index));
2149 index++;
2150 }
2151
2152
2153 chunkstart = index;
2154 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2155 && HPTE_VALID(HPTE(spapr->htab, index))) {
2156 CLEAN_HPTE(HPTE(spapr->htab, index));
2157 index++;
2158 }
2159
2160 if (index > chunkstart) {
2161 int n_valid = index - chunkstart;
2162
2163 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2164
2165 if (has_timeout &&
2166 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2167 break;
2168 }
2169 }
2170 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2171
2172 if (index >= htabslots) {
2173 assert(index == htabslots);
2174 index = 0;
2175 spapr->htab_first_pass = false;
2176 }
2177 spapr->htab_save_index = index;
2178}
2179
2180static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr,
2181 int64_t max_ns)
2182{
2183 bool final = max_ns < 0;
2184 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2185 int examined = 0, sent = 0;
2186 int index = spapr->htab_save_index;
2187 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2188
2189 assert(!spapr->htab_first_pass);
2190
2191 do {
2192 int chunkstart, invalidstart;
2193
2194
2195 while ((index < htabslots)
2196 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2197 index++;
2198 examined++;
2199 }
2200
2201 chunkstart = index;
2202
2203 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2204 && HPTE_DIRTY(HPTE(spapr->htab, index))
2205 && HPTE_VALID(HPTE(spapr->htab, index))) {
2206 CLEAN_HPTE(HPTE(spapr->htab, index));
2207 index++;
2208 examined++;
2209 }
2210
2211 invalidstart = index;
2212
2213 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2214 && HPTE_DIRTY(HPTE(spapr->htab, index))
2215 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2216 CLEAN_HPTE(HPTE(spapr->htab, index));
2217 index++;
2218 examined++;
2219 }
2220
2221 if (index > chunkstart) {
2222 int n_valid = invalidstart - chunkstart;
2223 int n_invalid = index - invalidstart;
2224
2225 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2226 sent += index - chunkstart;
2227
2228 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2229 break;
2230 }
2231 }
2232
2233 if (examined >= htabslots) {
2234 break;
2235 }
2236
2237 if (index >= htabslots) {
2238 assert(index == htabslots);
2239 index = 0;
2240 }
2241 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2242
2243 if (index >= htabslots) {
2244 assert(index == htabslots);
2245 index = 0;
2246 }
2247
2248 spapr->htab_save_index = index;
2249
2250 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2251}
2252
2253#define MAX_ITERATION_NS 5000000
2254#define MAX_KVM_BUF_SIZE 2048
2255
2256static int htab_save_iterate(QEMUFile *f, void *opaque)
2257{
2258 SpaprMachineState *spapr = opaque;
2259 int fd;
2260 int rc = 0;
2261
2262
2263 if (!spapr->htab_shift) {
2264 qemu_put_be32(f, -1);
2265 return 1;
2266 } else {
2267 qemu_put_be32(f, 0);
2268 }
2269
2270 if (!spapr->htab) {
2271 assert(kvm_enabled());
2272
2273 fd = get_htab_fd(spapr);
2274 if (fd < 0) {
2275 return fd;
2276 }
2277
2278 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2279 if (rc < 0) {
2280 return rc;
2281 }
2282 } else if (spapr->htab_first_pass) {
2283 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2284 } else {
2285 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2286 }
2287
2288 htab_save_end_marker(f);
2289
2290 return rc;
2291}
2292
2293static int htab_save_complete(QEMUFile *f, void *opaque)
2294{
2295 SpaprMachineState *spapr = opaque;
2296 int fd;
2297
2298
2299 if (!spapr->htab_shift) {
2300 qemu_put_be32(f, -1);
2301 return 0;
2302 } else {
2303 qemu_put_be32(f, 0);
2304 }
2305
2306 if (!spapr->htab) {
2307 int rc;
2308
2309 assert(kvm_enabled());
2310
2311 fd = get_htab_fd(spapr);
2312 if (fd < 0) {
2313 return fd;
2314 }
2315
2316 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2317 if (rc < 0) {
2318 return rc;
2319 }
2320 } else {
2321 if (spapr->htab_first_pass) {
2322 htab_save_first_pass(f, spapr, -1);
2323 }
2324 htab_save_later_pass(f, spapr, -1);
2325 }
2326
2327
2328 htab_save_end_marker(f);
2329
2330 return 0;
2331}
2332
2333static int htab_load(QEMUFile *f, void *opaque, int version_id)
2334{
2335 SpaprMachineState *spapr = opaque;
2336 uint32_t section_hdr;
2337 int fd = -1;
2338 Error *local_err = NULL;
2339
2340 if (version_id < 1 || version_id > 1) {
2341 error_report("htab_load() bad version");
2342 return -EINVAL;
2343 }
2344
2345 section_hdr = qemu_get_be32(f);
2346
2347 if (section_hdr == -1) {
2348 spapr_free_hpt(spapr);
2349 return 0;
2350 }
2351
2352 if (section_hdr) {
2353
2354 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2355 if (local_err) {
2356 error_report_err(local_err);
2357 return -EINVAL;
2358 }
2359 return 0;
2360 }
2361
2362 if (!spapr->htab) {
2363 assert(kvm_enabled());
2364
2365 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2366 if (fd < 0) {
2367 error_report_err(local_err);
2368 return fd;
2369 }
2370 }
2371
2372 while (true) {
2373 uint32_t index;
2374 uint16_t n_valid, n_invalid;
2375
2376 index = qemu_get_be32(f);
2377 n_valid = qemu_get_be16(f);
2378 n_invalid = qemu_get_be16(f);
2379
2380 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2381
2382 break;
2383 }
2384
2385 if ((index + n_valid + n_invalid) >
2386 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2387
2388 error_report(
2389 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2390 index, n_valid, n_invalid, spapr->htab_shift);
2391 return -EINVAL;
2392 }
2393
2394 if (spapr->htab) {
2395 if (n_valid) {
2396 qemu_get_buffer(f, HPTE(spapr->htab, index),
2397 HASH_PTE_SIZE_64 * n_valid);
2398 }
2399 if (n_invalid) {
2400 memset(HPTE(spapr->htab, index + n_valid), 0,
2401 HASH_PTE_SIZE_64 * n_invalid);
2402 }
2403 } else {
2404 int rc;
2405
2406 assert(fd >= 0);
2407
2408 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2409 if (rc < 0) {
2410 return rc;
2411 }
2412 }
2413 }
2414
2415 if (!spapr->htab) {
2416 assert(fd >= 0);
2417 close(fd);
2418 }
2419
2420 return 0;
2421}
2422
2423static void htab_save_cleanup(void *opaque)
2424{
2425 SpaprMachineState *spapr = opaque;
2426
2427 close_htab_fd(spapr);
2428}
2429
2430static SaveVMHandlers savevm_htab_handlers = {
2431 .save_setup = htab_save_setup,
2432 .save_live_iterate = htab_save_iterate,
2433 .save_live_complete_precopy = htab_save_complete,
2434 .save_cleanup = htab_save_cleanup,
2435 .load_state = htab_load,
2436};
2437
2438static void spapr_boot_set(void *opaque, const char *boot_device,
2439 Error **errp)
2440{
2441 MachineState *machine = MACHINE(opaque);
2442 machine->boot_order = g_strdup(boot_device);
2443}
2444
2445static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr)
2446{
2447 MachineState *machine = MACHINE(spapr);
2448 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2449 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2450 int i;
2451
2452 for (i = 0; i < nr_lmbs; i++) {
2453 uint64_t addr;
2454
2455 addr = i * lmb_size + machine->device_memory->base;
2456 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2457 addr / lmb_size);
2458 }
2459}
2460
2461
2462
2463
2464
2465
2466static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2467{
2468 int i;
2469
2470 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2471 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2472 " is not aligned to %" PRIu64 " MiB",
2473 machine->ram_size,
2474 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2475 return;
2476 }
2477
2478 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2479 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2480 " is not aligned to %" PRIu64 " MiB",
2481 machine->ram_size,
2482 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2483 return;
2484 }
2485
2486 for (i = 0; i < nb_numa_nodes; i++) {
2487 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2488 error_setg(errp,
2489 "Node %d memory size 0x%" PRIx64
2490 " is not aligned to %" PRIu64 " MiB",
2491 i, numa_info[i].node_mem,
2492 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2493 return;
2494 }
2495 }
2496}
2497
2498
2499static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2500{
2501 int index = id / smp_threads;
2502
2503 if (index >= ms->possible_cpus->len) {
2504 return NULL;
2505 }
2506 if (idx) {
2507 *idx = index;
2508 }
2509 return &ms->possible_cpus->cpus[index];
2510}
2511
2512static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
2513{
2514 Error *local_err = NULL;
2515 bool vsmt_user = !!spapr->vsmt;
2516 int kvm_smt = kvmppc_smt_threads();
2517 int ret;
2518
2519 if (!kvm_enabled() && (smp_threads > 1)) {
2520 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2521 "on a pseries machine");
2522 goto out;
2523 }
2524 if (!is_power_of_2(smp_threads)) {
2525 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2526 "machine because it must be a power of 2", smp_threads);
2527 goto out;
2528 }
2529
2530
2531 if (vsmt_user) {
2532 if (spapr->vsmt < smp_threads) {
2533 error_setg(&local_err, "Cannot support VSMT mode %d"
2534 " because it must be >= threads/core (%d)",
2535 spapr->vsmt, smp_threads);
2536 goto out;
2537 }
2538
2539 } else {
2540
2541
2542
2543
2544
2545
2546
2547 spapr->vsmt = MAX(8, smp_threads);
2548 }
2549
2550
2551 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2552 ret = kvmppc_set_smt_threads(spapr->vsmt);
2553 if (ret) {
2554
2555 error_setg(&local_err,
2556 "Failed to set KVM's VSMT mode to %d (errno %d)",
2557 spapr->vsmt, ret);
2558
2559
2560
2561
2562 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2563 warn_report_err(local_err);
2564 local_err = NULL;
2565 goto out;
2566 } else {
2567 if (!vsmt_user) {
2568 error_append_hint(&local_err,
2569 "On PPC, a VM with %d threads/core"
2570 " on a host with %d threads/core"
2571 " requires the use of VSMT mode %d.\n",
2572 smp_threads, kvm_smt, spapr->vsmt);
2573 }
2574 kvmppc_hint_smt_possible(&local_err);
2575 goto out;
2576 }
2577 }
2578 }
2579
2580out:
2581 error_propagate(errp, local_err);
2582}
2583
2584static void spapr_init_cpus(SpaprMachineState *spapr)
2585{
2586 MachineState *machine = MACHINE(spapr);
2587 MachineClass *mc = MACHINE_GET_CLASS(machine);
2588 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2589 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2590 const CPUArchIdList *possible_cpus;
2591 int boot_cores_nr = smp_cpus / smp_threads;
2592 int i;
2593
2594 possible_cpus = mc->possible_cpu_arch_ids(machine);
2595 if (mc->has_hotpluggable_cpus) {
2596 if (smp_cpus % smp_threads) {
2597 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2598 smp_cpus, smp_threads);
2599 exit(1);
2600 }
2601 if (max_cpus % smp_threads) {
2602 error_report("max_cpus (%u) must be multiple of threads (%u)",
2603 max_cpus, smp_threads);
2604 exit(1);
2605 }
2606 } else {
2607 if (max_cpus != smp_cpus) {
2608 error_report("This machine version does not support CPU hotplug");
2609 exit(1);
2610 }
2611 boot_cores_nr = possible_cpus->len;
2612 }
2613
2614 if (smc->pre_2_10_has_unused_icps) {
2615 int i;
2616
2617 for (i = 0; i < spapr_max_server_number(spapr); i++) {
2618
2619
2620
2621 pre_2_10_vmstate_register_dummy_icp(i);
2622 }
2623 }
2624
2625 for (i = 0; i < possible_cpus->len; i++) {
2626 int core_id = i * smp_threads;
2627
2628 if (mc->has_hotpluggable_cpus) {
2629 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2630 spapr_vcpu_id(spapr, core_id));
2631 }
2632
2633 if (i < boot_cores_nr) {
2634 Object *core = object_new(type);
2635 int nr_threads = smp_threads;
2636
2637
2638 if ((i + 1) * smp_threads >= smp_cpus) {
2639 nr_threads = smp_cpus - i * smp_threads;
2640 }
2641
2642 object_property_set_int(core, nr_threads, "nr-threads",
2643 &error_fatal);
2644 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2645 &error_fatal);
2646 object_property_set_bool(core, true, "realized", &error_fatal);
2647
2648 object_unref(core);
2649 }
2650 }
2651}
2652
2653static PCIHostState *spapr_create_default_phb(void)
2654{
2655 DeviceState *dev;
2656
2657 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
2658 qdev_prop_set_uint32(dev, "index", 0);
2659 qdev_init_nofail(dev);
2660
2661 return PCI_HOST_BRIDGE(dev);
2662}
2663
2664
2665static void spapr_machine_init(MachineState *machine)
2666{
2667 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
2668 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2669 const char *kernel_filename = machine->kernel_filename;
2670 const char *initrd_filename = machine->initrd_filename;
2671 PCIHostState *phb;
2672 int i;
2673 MemoryRegion *sysmem = get_system_memory();
2674 MemoryRegion *ram = g_new(MemoryRegion, 1);
2675 hwaddr node0_size = spapr_node0_size(machine);
2676 long load_limit, fw_size;
2677 char *filename;
2678 Error *resize_hpt_err = NULL;
2679
2680 msi_nonbroken = true;
2681
2682 QLIST_INIT(&spapr->phbs);
2683 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2684
2685
2686 spapr_caps_init(spapr);
2687
2688 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2689 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2690
2691
2692
2693
2694
2695
2696 if (resize_hpt_err) {
2697 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2698 error_free(resize_hpt_err);
2699 resize_hpt_err = NULL;
2700 } else {
2701 spapr->resize_hpt = smc->resize_hpt_default;
2702 }
2703 }
2704
2705 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2706
2707 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2708
2709
2710
2711 error_report_err(resize_hpt_err);
2712 exit(1);
2713 }
2714
2715 spapr->rma_size = node0_size;
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726 if (kvm_enabled()) {
2727 spapr->vrma_adjust = 1;
2728 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2729 }
2730
2731
2732
2733
2734
2735
2736 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2737
2738 if (spapr->rma_size > node0_size) {
2739 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2740 spapr->rma_size);
2741 exit(1);
2742 }
2743
2744
2745 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2746
2747
2748
2749
2750
2751 spapr_set_vsmt_mode(spapr, &error_fatal);
2752
2753
2754 spapr_irq_init(spapr, &error_fatal);
2755
2756
2757
2758 spapr->ov5 = spapr_ovec_new();
2759 spapr->ov5_cas = spapr_ovec_new();
2760
2761 if (smc->dr_lmb_enabled) {
2762 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2763 spapr_validate_node_memory(machine, &error_fatal);
2764 }
2765
2766 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2767
2768
2769 if (spapr->use_hotplug_event_source) {
2770 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2771 }
2772
2773
2774 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2775 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2776 }
2777
2778
2779 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2780
2781
2782 if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) {
2783 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2784 }
2785
2786
2787 spapr_init_cpus(spapr);
2788
2789 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2790 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2791 spapr->max_compat_pvr)) {
2792
2793 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2794 }
2795
2796
2797 if (kvm_enabled()) {
2798
2799 kvmppc_enable_logical_ci_hcalls();
2800 kvmppc_enable_set_mode_hcall();
2801
2802
2803 kvmppc_enable_clear_ref_mod_hcalls();
2804
2805
2806 kvmppc_enable_h_page_init();
2807 }
2808
2809
2810 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2811 machine->ram_size);
2812 memory_region_add_subregion(sysmem, 0, ram);
2813
2814
2815 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2816
2817
2818 if (machine->ram_size < machine->maxram_size) {
2819 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2820
2821
2822
2823
2824
2825 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2826 SPAPR_MAX_RAM_SLOTS;
2827
2828 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2829 max_memslots = SPAPR_MAX_RAM_SLOTS;
2830 }
2831 if (machine->ram_slots > max_memslots) {
2832 error_report("Specified number of memory slots %"
2833 PRIu64" exceeds max supported %d",
2834 machine->ram_slots, max_memslots);
2835 exit(1);
2836 }
2837
2838 machine->device_memory->base = ROUND_UP(machine->ram_size,
2839 SPAPR_DEVICE_MEM_ALIGN);
2840 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2841 "device-memory", device_mem_size);
2842 memory_region_add_subregion(sysmem, machine->device_memory->base,
2843 &machine->device_memory->mr);
2844 }
2845
2846 if (smc->dr_lmb_enabled) {
2847 spapr_create_lmb_dr_connectors(spapr);
2848 }
2849
2850 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2851 if (!filename) {
2852 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2853 exit(1);
2854 }
2855 spapr->rtas_size = get_image_size(filename);
2856 if (spapr->rtas_size < 0) {
2857 error_report("Could not get size of LPAR rtas '%s'", filename);
2858 exit(1);
2859 }
2860 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2861 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2862 error_report("Could not load LPAR rtas '%s'", filename);
2863 exit(1);
2864 }
2865 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2866 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2867 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2868 exit(1);
2869 }
2870 g_free(filename);
2871
2872
2873 spapr_events_init(spapr);
2874
2875
2876 spapr_rtc_create(spapr);
2877
2878
2879 spapr->vio_bus = spapr_vio_bus_init();
2880
2881 for (i = 0; i < serial_max_hds(); i++) {
2882 if (serial_hd(i)) {
2883 spapr_vty_create(spapr->vio_bus, serial_hd(i));
2884 }
2885 }
2886
2887
2888 spapr_create_nvram(spapr);
2889
2890
2891
2892
2893
2894
2895
2896
2897 if (smc->dr_phb_enabled) {
2898 for (i = 0; i < SPAPR_MAX_PHBS; i++) {
2899 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i);
2900 }
2901 }
2902
2903
2904 spapr_pci_rtas_init();
2905
2906 phb = spapr_create_default_phb();
2907
2908 for (i = 0; i < nb_nics; i++) {
2909 NICInfo *nd = &nd_table[i];
2910
2911 if (!nd->model) {
2912 nd->model = g_strdup("spapr-vlan");
2913 }
2914
2915 if (g_str_equal(nd->model, "spapr-vlan") ||
2916 g_str_equal(nd->model, "ibmveth")) {
2917 spapr_vlan_create(spapr->vio_bus, nd);
2918 } else {
2919 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2920 }
2921 }
2922
2923 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2924 spapr_vscsi_create(spapr->vio_bus);
2925 }
2926
2927
2928 if (spapr_vga_init(phb->bus, &error_fatal)) {
2929 spapr->has_graphics = true;
2930 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2931 }
2932
2933 if (machine->usb) {
2934 if (smc->use_ohci_by_default) {
2935 pci_create_simple(phb->bus, -1, "pci-ohci");
2936 } else {
2937 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2938 }
2939
2940 if (spapr->has_graphics) {
2941 USBBus *usb_bus = usb_bus_find(-1);
2942
2943 usb_create_simple(usb_bus, "usb-kbd");
2944 usb_create_simple(usb_bus, "usb-mouse");
2945 }
2946 }
2947
2948 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) {
2949 error_report(
2950 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2951 MIN_RMA_SLOF);
2952 exit(1);
2953 }
2954
2955 if (kernel_filename) {
2956 uint64_t lowaddr = 0;
2957
2958 spapr->kernel_size = load_elf(kernel_filename, NULL,
2959 translate_kernel_address, NULL,
2960 NULL, &lowaddr, NULL, 1,
2961 PPC_ELF_MACHINE, 0, 0);
2962 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2963 spapr->kernel_size = load_elf(kernel_filename, NULL,
2964 translate_kernel_address, NULL, NULL,
2965 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2966 0, 0);
2967 spapr->kernel_le = spapr->kernel_size > 0;
2968 }
2969 if (spapr->kernel_size < 0) {
2970 error_report("error loading %s: %s", kernel_filename,
2971 load_elf_strerror(spapr->kernel_size));
2972 exit(1);
2973 }
2974
2975
2976 if (initrd_filename) {
2977
2978
2979
2980 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2981 + 0x1ffff) & ~0xffff;
2982 spapr->initrd_size = load_image_targphys(initrd_filename,
2983 spapr->initrd_base,
2984 load_limit
2985 - spapr->initrd_base);
2986 if (spapr->initrd_size < 0) {
2987 error_report("could not load initial ram disk '%s'",
2988 initrd_filename);
2989 exit(1);
2990 }
2991 }
2992 }
2993
2994 if (bios_name == NULL) {
2995 bios_name = FW_FILE_NAME;
2996 }
2997 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2998 if (!filename) {
2999 error_report("Could not find LPAR firmware '%s'", bios_name);
3000 exit(1);
3001 }
3002 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
3003 if (fw_size <= 0) {
3004 error_report("Could not load LPAR firmware '%s'", filename);
3005 exit(1);
3006 }
3007 g_free(filename);
3008
3009
3010
3011
3012 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
3013 register_savevm_live(NULL, "spapr/htab", -1, 1,
3014 &savevm_htab_handlers, spapr);
3015
3016 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine),
3017 &error_fatal);
3018
3019 qemu_register_boot_set(spapr_boot_set, spapr);
3020
3021 if (kvm_enabled()) {
3022
3023 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
3024 &spapr->tb);
3025
3026 kvmppc_spapr_enable_inkernel_multitce();
3027 }
3028}
3029
3030static int spapr_kvm_type(MachineState *machine, const char *vm_type)
3031{
3032 if (!vm_type) {
3033 return 0;
3034 }
3035
3036 if (!strcmp(vm_type, "HV")) {
3037 return 1;
3038 }
3039
3040 if (!strcmp(vm_type, "PR")) {
3041 return 2;
3042 }
3043
3044 error_report("Unknown kvm-type specified '%s'", vm_type);
3045 exit(1);
3046}
3047
3048
3049
3050
3051
3052static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
3053 DeviceState *dev)
3054{
3055#define CAST(type, obj, name) \
3056 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3057 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
3058 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
3059 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
3060
3061 if (d) {
3062 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
3063 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
3064 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
3065
3066 if (spapr) {
3067
3068
3069
3070
3071
3072
3073 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
3074 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3075 (uint64_t)id << 48);
3076 } else if (virtio) {
3077
3078
3079
3080
3081
3082
3083
3084 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
3085 if (d->lun >= 256) {
3086
3087 id |= 0x4000;
3088 }
3089 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3090 (uint64_t)id << 32);
3091 } else if (usb) {
3092
3093
3094
3095
3096 unsigned usb_port = atoi(usb->port->path);
3097 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3098 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3099 (uint64_t)id << 32);
3100 }
3101 }
3102
3103
3104
3105
3106
3107
3108
3109 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3110 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3111 if (usb_host_dev_is_scsi_storage(usbdev)) {
3112 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3113 }
3114 }
3115
3116 if (phb) {
3117
3118 return g_strdup_printf("pci@%"PRIX64, phb->buid);
3119 }
3120
3121 if (vsc) {
3122
3123 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3124 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3125 }
3126
3127 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3128
3129 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3130 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3131 }
3132
3133 return NULL;
3134}
3135
3136static char *spapr_get_kvm_type(Object *obj, Error **errp)
3137{
3138 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3139
3140 return g_strdup(spapr->kvm_type);
3141}
3142
3143static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3144{
3145 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3146
3147 g_free(spapr->kvm_type);
3148 spapr->kvm_type = g_strdup(value);
3149}
3150
3151static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3152{
3153 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3154
3155 return spapr->use_hotplug_event_source;
3156}
3157
3158static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3159 Error **errp)
3160{
3161 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3162
3163 spapr->use_hotplug_event_source = value;
3164}
3165
3166static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3167{
3168 return true;
3169}
3170
3171static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3172{
3173 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3174
3175 switch (spapr->resize_hpt) {
3176 case SPAPR_RESIZE_HPT_DEFAULT:
3177 return g_strdup("default");
3178 case SPAPR_RESIZE_HPT_DISABLED:
3179 return g_strdup("disabled");
3180 case SPAPR_RESIZE_HPT_ENABLED:
3181 return g_strdup("enabled");
3182 case SPAPR_RESIZE_HPT_REQUIRED:
3183 return g_strdup("required");
3184 }
3185 g_assert_not_reached();
3186}
3187
3188static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3189{
3190 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3191
3192 if (strcmp(value, "default") == 0) {
3193 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3194 } else if (strcmp(value, "disabled") == 0) {
3195 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3196 } else if (strcmp(value, "enabled") == 0) {
3197 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3198 } else if (strcmp(value, "required") == 0) {
3199 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3200 } else {
3201 error_setg(errp, "Bad value for \"resize-hpt\" property");
3202 }
3203}
3204
3205static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
3206 void *opaque, Error **errp)
3207{
3208 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3209}
3210
3211static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
3212 void *opaque, Error **errp)
3213{
3214 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3215}
3216
3217static char *spapr_get_ic_mode(Object *obj, Error **errp)
3218{
3219 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3220
3221 if (spapr->irq == &spapr_irq_xics_legacy) {
3222 return g_strdup("legacy");
3223 } else if (spapr->irq == &spapr_irq_xics) {
3224 return g_strdup("xics");
3225 } else if (spapr->irq == &spapr_irq_xive) {
3226 return g_strdup("xive");
3227 } else if (spapr->irq == &spapr_irq_dual) {
3228 return g_strdup("dual");
3229 }
3230 g_assert_not_reached();
3231}
3232
3233static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3234{
3235 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3236
3237 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3238 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3239 return;
3240 }
3241
3242
3243 if (strcmp(value, "xics") == 0) {
3244 spapr->irq = &spapr_irq_xics;
3245 } else if (strcmp(value, "xive") == 0) {
3246 spapr->irq = &spapr_irq_xive;
3247 } else if (strcmp(value, "dual") == 0) {
3248 spapr->irq = &spapr_irq_dual;
3249 } else {
3250 error_setg(errp, "Bad value for \"ic-mode\" property");
3251 }
3252}
3253
3254static char *spapr_get_host_model(Object *obj, Error **errp)
3255{
3256 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3257
3258 return g_strdup(spapr->host_model);
3259}
3260
3261static void spapr_set_host_model(Object *obj, const char *value, Error **errp)
3262{
3263 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3264
3265 g_free(spapr->host_model);
3266 spapr->host_model = g_strdup(value);
3267}
3268
3269static char *spapr_get_host_serial(Object *obj, Error **errp)
3270{
3271 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3272
3273 return g_strdup(spapr->host_serial);
3274}
3275
3276static void spapr_set_host_serial(Object *obj, const char *value, Error **errp)
3277{
3278 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3279
3280 g_free(spapr->host_serial);
3281 spapr->host_serial = g_strdup(value);
3282}
3283
3284static void spapr_instance_init(Object *obj)
3285{
3286 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3287 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3288
3289 spapr->htab_fd = -1;
3290 spapr->use_hotplug_event_source = true;
3291 object_property_add_str(obj, "kvm-type",
3292 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
3293 object_property_set_description(obj, "kvm-type",
3294 "Specifies the KVM virtualization mode (HV, PR)",
3295 NULL);
3296 object_property_add_bool(obj, "modern-hotplug-events",
3297 spapr_get_modern_hotplug_events,
3298 spapr_set_modern_hotplug_events,
3299 NULL);
3300 object_property_set_description(obj, "modern-hotplug-events",
3301 "Use dedicated hotplug event mechanism in"
3302 " place of standard EPOW events when possible"
3303 " (required for memory hot-unplug support)",
3304 NULL);
3305 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3306 "Maximum permitted CPU compatibility mode",
3307 &error_fatal);
3308
3309 object_property_add_str(obj, "resize-hpt",
3310 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
3311 object_property_set_description(obj, "resize-hpt",
3312 "Resizing of the Hash Page Table (enabled, disabled, required)",
3313 NULL);
3314 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
3315 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
3316 object_property_set_description(obj, "vsmt",
3317 "Virtual SMT: KVM behaves as if this were"
3318 " the host's SMT mode", &error_abort);
3319 object_property_add_bool(obj, "vfio-no-msix-emulation",
3320 spapr_get_msix_emulation, NULL, NULL);
3321
3322
3323 spapr->irq = smc->irq;
3324 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode,
3325 spapr_set_ic_mode, NULL);
3326 object_property_set_description(obj, "ic-mode",
3327 "Specifies the interrupt controller mode (xics, xive, dual)",
3328 NULL);
3329
3330 object_property_add_str(obj, "host-model",
3331 spapr_get_host_model, spapr_set_host_model,
3332 &error_abort);
3333 object_property_set_description(obj, "host-model",
3334 "Host model to advertise in guest device tree", &error_abort);
3335 object_property_add_str(obj, "host-serial",
3336 spapr_get_host_serial, spapr_set_host_serial,
3337 &error_abort);
3338 object_property_set_description(obj, "host-serial",
3339 "Host serial number to advertise in guest device tree", &error_abort);
3340}
3341
3342static void spapr_machine_finalizefn(Object *obj)
3343{
3344 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3345
3346 g_free(spapr->kvm_type);
3347}
3348
3349void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
3350{
3351 cpu_synchronize_state(cs);
3352 ppc_cpu_do_system_reset(cs);
3353}
3354
3355static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3356{
3357 CPUState *cs;
3358
3359 CPU_FOREACH(cs) {
3360 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
3361 }
3362}
3363
3364int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3365 void *fdt, int *fdt_start_offset, Error **errp)
3366{
3367 uint64_t addr;
3368 uint32_t node;
3369
3370 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE;
3371 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP,
3372 &error_abort);
3373 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr,
3374 SPAPR_MEMORY_BLOCK_SIZE);
3375 return 0;
3376}
3377
3378static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3379 bool dedicated_hp_event_source, Error **errp)
3380{
3381 SpaprDrc *drc;
3382 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3383 int i;
3384 uint64_t addr = addr_start;
3385 bool hotplugged = spapr_drc_hotplugged(dev);
3386 Error *local_err = NULL;
3387
3388 for (i = 0; i < nr_lmbs; i++) {
3389 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3390 addr / SPAPR_MEMORY_BLOCK_SIZE);
3391 g_assert(drc);
3392
3393 spapr_drc_attach(drc, dev, &local_err);
3394 if (local_err) {
3395 while (addr > addr_start) {
3396 addr -= SPAPR_MEMORY_BLOCK_SIZE;
3397 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3398 addr / SPAPR_MEMORY_BLOCK_SIZE);
3399 spapr_drc_detach(drc);
3400 }
3401 error_propagate(errp, local_err);
3402 return;
3403 }
3404 if (!hotplugged) {
3405 spapr_drc_reset(drc);
3406 }
3407 addr += SPAPR_MEMORY_BLOCK_SIZE;
3408 }
3409
3410
3411
3412 if (hotplugged) {
3413 if (dedicated_hp_event_source) {
3414 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3415 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3416 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3417 nr_lmbs,
3418 spapr_drc_index(drc));
3419 } else {
3420 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3421 nr_lmbs);
3422 }
3423 }
3424}
3425
3426static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3427 Error **errp)
3428{
3429 Error *local_err = NULL;
3430 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3431 PCDIMMDevice *dimm = PC_DIMM(dev);
3432 uint64_t size, addr;
3433
3434 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort);
3435
3436 pc_dimm_plug(dimm, MACHINE(ms), &local_err);
3437 if (local_err) {
3438 goto out;
3439 }
3440
3441 addr = object_property_get_uint(OBJECT(dimm),
3442 PC_DIMM_ADDR_PROP, &local_err);
3443 if (local_err) {
3444 goto out_unplug;
3445 }
3446
3447 spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3448 &local_err);
3449 if (local_err) {
3450 goto out_unplug;
3451 }
3452
3453 return;
3454
3455out_unplug:
3456 pc_dimm_unplug(dimm, MACHINE(ms));
3457out:
3458 error_propagate(errp, local_err);
3459}
3460
3461static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3462 Error **errp)
3463{
3464 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
3465 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3466 PCDIMMDevice *dimm = PC_DIMM(dev);
3467 Error *local_err = NULL;
3468 uint64_t size;
3469 Object *memdev;
3470 hwaddr pagesize;
3471
3472 if (!smc->dr_lmb_enabled) {
3473 error_setg(errp, "Memory hotplug not supported for this machine");
3474 return;
3475 }
3476
3477 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err);
3478 if (local_err) {
3479 error_propagate(errp, local_err);
3480 return;
3481 }
3482
3483 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3484 error_setg(errp, "Hotplugged memory size must be a multiple of "
3485 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
3486 return;
3487 }
3488
3489 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP,
3490 &error_abort);
3491 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev));
3492 spapr_check_pagesize(spapr, pagesize, &local_err);
3493 if (local_err) {
3494 error_propagate(errp, local_err);
3495 return;
3496 }
3497
3498 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp);
3499}
3500
3501struct SpaprDimmState {
3502 PCDIMMDevice *dimm;
3503 uint32_t nr_lmbs;
3504 QTAILQ_ENTRY(SpaprDimmState) next;
3505};
3506
3507static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s,
3508 PCDIMMDevice *dimm)
3509{
3510 SpaprDimmState *dimm_state = NULL;
3511
3512 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3513 if (dimm_state->dimm == dimm) {
3514 break;
3515 }
3516 }
3517 return dimm_state;
3518}
3519
3520static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr,
3521 uint32_t nr_lmbs,
3522 PCDIMMDevice *dimm)
3523{
3524 SpaprDimmState *ds = NULL;
3525
3526
3527
3528
3529
3530
3531
3532 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3533 if (!ds) {
3534 ds = g_malloc0(sizeof(SpaprDimmState));
3535 ds->nr_lmbs = nr_lmbs;
3536 ds->dimm = dimm;
3537 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3538 }
3539 return ds;
3540}
3541
3542static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr,
3543 SpaprDimmState *dimm_state)
3544{
3545 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3546 g_free(dimm_state);
3547}
3548
3549static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms,
3550 PCDIMMDevice *dimm)
3551{
3552 SpaprDrc *drc;
3553 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm),
3554 &error_abort);
3555 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3556 uint32_t avail_lmbs = 0;
3557 uint64_t addr_start, addr;
3558 int i;
3559
3560 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3561 &error_abort);
3562
3563 addr = addr_start;
3564 for (i = 0; i < nr_lmbs; i++) {
3565 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3566 addr / SPAPR_MEMORY_BLOCK_SIZE);
3567 g_assert(drc);
3568 if (drc->dev) {
3569 avail_lmbs++;
3570 }
3571 addr += SPAPR_MEMORY_BLOCK_SIZE;
3572 }
3573
3574 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3575}
3576
3577
3578void spapr_lmb_release(DeviceState *dev)
3579{
3580 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3581 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
3582 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3583
3584
3585
3586 if (ds == NULL) {
3587 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3588 g_assert(ds);
3589
3590 g_assert(ds->nr_lmbs);
3591 }
3592
3593 if (--ds->nr_lmbs) {
3594 return;
3595 }
3596
3597
3598
3599
3600
3601 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3602 object_unparent(OBJECT(dev));
3603}
3604
3605static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3606{
3607 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3608 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3609
3610 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev));
3611 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3612 spapr_pending_dimm_unplugs_remove(spapr, ds);
3613}
3614
3615static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3616 DeviceState *dev, Error **errp)
3617{
3618 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3619 Error *local_err = NULL;
3620 PCDIMMDevice *dimm = PC_DIMM(dev);
3621 uint32_t nr_lmbs;
3622 uint64_t size, addr_start, addr;
3623 int i;
3624 SpaprDrc *drc;
3625
3626 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort);
3627 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3628
3629 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3630 &local_err);
3631 if (local_err) {
3632 goto out;
3633 }
3634
3635
3636
3637
3638
3639
3640
3641 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3642 error_setg(&local_err,
3643 "Memory unplug already in progress for device %s",
3644 dev->id);
3645 goto out;
3646 }
3647
3648 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3649
3650 addr = addr_start;
3651 for (i = 0; i < nr_lmbs; i++) {
3652 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3653 addr / SPAPR_MEMORY_BLOCK_SIZE);
3654 g_assert(drc);
3655
3656 spapr_drc_detach(drc);
3657 addr += SPAPR_MEMORY_BLOCK_SIZE;
3658 }
3659
3660 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3661 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3662 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3663 nr_lmbs, spapr_drc_index(drc));
3664out:
3665 error_propagate(errp, local_err);
3666}
3667
3668
3669void spapr_core_release(DeviceState *dev)
3670{
3671 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3672
3673
3674 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3675 object_unparent(OBJECT(dev));
3676}
3677
3678static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3679{
3680 MachineState *ms = MACHINE(hotplug_dev);
3681 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3682 CPUCore *cc = CPU_CORE(dev);
3683 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3684
3685 if (smc->pre_2_10_has_unused_icps) {
3686 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3687 int i;
3688
3689 for (i = 0; i < cc->nr_threads; i++) {
3690 CPUState *cs = CPU(sc->threads[i]);
3691
3692 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3693 }
3694 }
3695
3696 assert(core_slot);
3697 core_slot->cpu = NULL;
3698 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3699}
3700
3701static
3702void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3703 Error **errp)
3704{
3705 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3706 int index;
3707 SpaprDrc *drc;
3708 CPUCore *cc = CPU_CORE(dev);
3709
3710 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3711 error_setg(errp, "Unable to find CPU core with core-id: %d",
3712 cc->core_id);
3713 return;
3714 }
3715 if (index == 0) {
3716 error_setg(errp, "Boot CPU core may not be unplugged");
3717 return;
3718 }
3719
3720 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3721 spapr_vcpu_id(spapr, cc->core_id));
3722 g_assert(drc);
3723
3724 spapr_drc_detach(drc);
3725
3726 spapr_hotplug_req_remove_by_index(drc);
3727}
3728
3729int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3730 void *fdt, int *fdt_start_offset, Error **errp)
3731{
3732 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev);
3733 CPUState *cs = CPU(core->threads[0]);
3734 PowerPCCPU *cpu = POWERPC_CPU(cs);
3735 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3736 int id = spapr_get_vcpu_id(cpu);
3737 char *nodename;
3738 int offset;
3739
3740 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3741 offset = fdt_add_subnode(fdt, 0, nodename);
3742 g_free(nodename);
3743
3744 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3745
3746 *fdt_start_offset = offset;
3747 return 0;
3748}
3749
3750static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3751 Error **errp)
3752{
3753 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3754 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3755 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3756 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3757 CPUCore *cc = CPU_CORE(dev);
3758 CPUState *cs;
3759 SpaprDrc *drc;
3760 Error *local_err = NULL;
3761 CPUArchId *core_slot;
3762 int index;
3763 bool hotplugged = spapr_drc_hotplugged(dev);
3764
3765 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3766 if (!core_slot) {
3767 error_setg(errp, "Unable to find CPU core with core-id: %d",
3768 cc->core_id);
3769 return;
3770 }
3771 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3772 spapr_vcpu_id(spapr, cc->core_id));
3773
3774 g_assert(drc || !mc->has_hotpluggable_cpus);
3775
3776 if (drc) {
3777 spapr_drc_attach(drc, dev, &local_err);
3778 if (local_err) {
3779 error_propagate(errp, local_err);
3780 return;
3781 }
3782
3783 if (hotplugged) {
3784
3785
3786
3787
3788 spapr_hotplug_req_add_by_index(drc);
3789 } else {
3790 spapr_drc_reset(drc);
3791 }
3792 }
3793
3794 core_slot->cpu = OBJECT(dev);
3795
3796 if (smc->pre_2_10_has_unused_icps) {
3797 int i;
3798
3799 for (i = 0; i < cc->nr_threads; i++) {
3800 cs = CPU(core->threads[i]);
3801 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3802 }
3803 }
3804}
3805
3806static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3807 Error **errp)
3808{
3809 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3810 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3811 Error *local_err = NULL;
3812 CPUCore *cc = CPU_CORE(dev);
3813 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3814 const char *type = object_get_typename(OBJECT(dev));
3815 CPUArchId *core_slot;
3816 int index;
3817
3818 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3819 error_setg(&local_err, "CPU hotplug not supported for this machine");
3820 goto out;
3821 }
3822
3823 if (strcmp(base_core_type, type)) {
3824 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3825 goto out;
3826 }
3827
3828 if (cc->core_id % smp_threads) {
3829 error_setg(&local_err, "invalid core id %d", cc->core_id);
3830 goto out;
3831 }
3832
3833
3834
3835
3836
3837
3838
3839 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3840 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3841 cc->nr_threads, smp_threads);
3842 goto out;
3843 }
3844
3845 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3846 if (!core_slot) {
3847 error_setg(&local_err, "core id %d out of range", cc->core_id);
3848 goto out;
3849 }
3850
3851 if (core_slot->cpu) {
3852 error_setg(&local_err, "core %d already populated", cc->core_id);
3853 goto out;
3854 }
3855
3856 numa_cpu_pre_plug(core_slot, dev, &local_err);
3857
3858out:
3859 error_propagate(errp, local_err);
3860}
3861
3862int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3863 void *fdt, int *fdt_start_offset, Error **errp)
3864{
3865 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev);
3866 int intc_phandle;
3867
3868 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp);
3869 if (intc_phandle <= 0) {
3870 return -1;
3871 }
3872
3873 if (spapr_populate_pci_dt(sphb, intc_phandle, fdt, spapr->irq->nr_msis,
3874 fdt_start_offset)) {
3875 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index);
3876 return -1;
3877 }
3878
3879
3880 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci"));
3881
3882 return 0;
3883}
3884
3885static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3886 Error **errp)
3887{
3888 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3889 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3890 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3891 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
3892
3893 if (dev->hotplugged && !smc->dr_phb_enabled) {
3894 error_setg(errp, "PHB hotplug not supported for this machine");
3895 return;
3896 }
3897
3898 if (sphb->index == (uint32_t)-1) {
3899 error_setg(errp, "\"index\" for PAPR PHB is mandatory");
3900 return;
3901 }
3902
3903
3904
3905
3906
3907 smc->phb_placement(spapr, sphb->index,
3908 &sphb->buid, &sphb->io_win_addr,
3909 &sphb->mem_win_addr, &sphb->mem64_win_addr,
3910 windows_supported, sphb->dma_liobn, errp);
3911}
3912
3913static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3914 Error **errp)
3915{
3916 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3917 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3918 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3919 SpaprDrc *drc;
3920 bool hotplugged = spapr_drc_hotplugged(dev);
3921 Error *local_err = NULL;
3922
3923 if (!smc->dr_phb_enabled) {
3924 return;
3925 }
3926
3927 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
3928
3929 assert(drc);
3930
3931 spapr_drc_attach(drc, DEVICE(dev), &local_err);
3932 if (local_err) {
3933 error_propagate(errp, local_err);
3934 return;
3935 }
3936
3937 if (hotplugged) {
3938 spapr_hotplug_req_add_by_index(drc);
3939 } else {
3940 spapr_drc_reset(drc);
3941 }
3942}
3943
3944void spapr_phb_release(DeviceState *dev)
3945{
3946 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3947
3948 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3949 object_unparent(OBJECT(dev));
3950}
3951
3952static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3953{
3954 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3955}
3956
3957static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev,
3958 DeviceState *dev, Error **errp)
3959{
3960 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3961 SpaprDrc *drc;
3962
3963 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
3964 assert(drc);
3965
3966 if (!spapr_drc_unplug_requested(drc)) {
3967 spapr_drc_detach(drc);
3968 spapr_hotplug_req_remove_by_index(drc);
3969 }
3970}
3971
3972static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3973 DeviceState *dev, Error **errp)
3974{
3975 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3976 spapr_memory_plug(hotplug_dev, dev, errp);
3977 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3978 spapr_core_plug(hotplug_dev, dev, errp);
3979 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
3980 spapr_phb_plug(hotplug_dev, dev, errp);
3981 }
3982}
3983
3984static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
3985 DeviceState *dev, Error **errp)
3986{
3987 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3988 spapr_memory_unplug(hotplug_dev, dev);
3989 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3990 spapr_core_unplug(hotplug_dev, dev);
3991 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
3992 spapr_phb_unplug(hotplug_dev, dev);
3993 }
3994}
3995
3996static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3997 DeviceState *dev, Error **errp)
3998{
3999 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
4000 MachineClass *mc = MACHINE_GET_CLASS(sms);
4001 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4002
4003 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4004 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
4005 spapr_memory_unplug_request(hotplug_dev, dev, errp);
4006 } else {
4007
4008
4009
4010
4011
4012
4013 error_setg(errp, "Memory hot unplug not supported for this guest");
4014 }
4015 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4016 if (!mc->has_hotpluggable_cpus) {
4017 error_setg(errp, "CPU hot unplug not supported on this machine");
4018 return;
4019 }
4020 spapr_core_unplug_request(hotplug_dev, dev, errp);
4021 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4022 if (!smc->dr_phb_enabled) {
4023 error_setg(errp, "PHB hot unplug not supported on this machine");
4024 return;
4025 }
4026 spapr_phb_unplug_request(hotplug_dev, dev, errp);
4027 }
4028}
4029
4030static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
4031 DeviceState *dev, Error **errp)
4032{
4033 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4034 spapr_memory_pre_plug(hotplug_dev, dev, errp);
4035 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4036 spapr_core_pre_plug(hotplug_dev, dev, errp);
4037 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4038 spapr_phb_pre_plug(hotplug_dev, dev, errp);
4039 }
4040}
4041
4042static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
4043 DeviceState *dev)
4044{
4045 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
4046 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) ||
4047 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4048 return HOTPLUG_HANDLER(machine);
4049 }
4050 return NULL;
4051}
4052
4053static CpuInstanceProperties
4054spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
4055{
4056 CPUArchId *core_slot;
4057 MachineClass *mc = MACHINE_GET_CLASS(machine);
4058
4059
4060 mc->possible_cpu_arch_ids(machine);
4061
4062 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
4063 assert(core_slot);
4064 return core_slot->props;
4065}
4066
4067static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
4068{
4069 return idx / smp_cores % nb_numa_nodes;
4070}
4071
4072static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
4073{
4074 int i;
4075 const char *core_type;
4076 int spapr_max_cores = max_cpus / smp_threads;
4077 MachineClass *mc = MACHINE_GET_CLASS(machine);
4078
4079 if (!mc->has_hotpluggable_cpus) {
4080 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
4081 }
4082 if (machine->possible_cpus) {
4083 assert(machine->possible_cpus->len == spapr_max_cores);
4084 return machine->possible_cpus;
4085 }
4086
4087 core_type = spapr_get_cpu_core_type(machine->cpu_type);
4088 if (!core_type) {
4089 error_report("Unable to find sPAPR CPU Core definition");
4090 exit(1);
4091 }
4092
4093 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
4094 sizeof(CPUArchId) * spapr_max_cores);
4095 machine->possible_cpus->len = spapr_max_cores;
4096 for (i = 0; i < machine->possible_cpus->len; i++) {
4097 int core_id = i * smp_threads;
4098
4099 machine->possible_cpus->cpus[i].type = core_type;
4100 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
4101 machine->possible_cpus->cpus[i].arch_id = core_id;
4102 machine->possible_cpus->cpus[i].props.has_core_id = true;
4103 machine->possible_cpus->cpus[i].props.core_id = core_id;
4104 }
4105 return machine->possible_cpus;
4106}
4107
4108static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index,
4109 uint64_t *buid, hwaddr *pio,
4110 hwaddr *mmio32, hwaddr *mmio64,
4111 unsigned n_dma, uint32_t *liobns, Error **errp)
4112{
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128 const uint64_t base_buid = 0x800000020000000ULL;
4129 int i;
4130
4131
4132 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4133 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4134 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
4135 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
4136
4137 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
4138 SPAPR_PCI_MEM32_WIN_SIZE);
4139 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
4140 SPAPR_PCI_MEM64_WIN_SIZE);
4141
4142 if (index >= SPAPR_MAX_PHBS) {
4143 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
4144 SPAPR_MAX_PHBS - 1);
4145 return;
4146 }
4147
4148 *buid = base_buid + index;
4149 for (i = 0; i < n_dma; ++i) {
4150 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4151 }
4152
4153 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
4154 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
4155 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
4156}
4157
4158static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
4159{
4160 SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4161
4162 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
4163}
4164
4165static void spapr_ics_resend(XICSFabric *dev)
4166{
4167 SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4168
4169 ics_resend(spapr->ics);
4170}
4171
4172static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
4173{
4174 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
4175
4176 return cpu ? spapr_cpu_state(cpu)->icp : NULL;
4177}
4178
4179static void spapr_pic_print_info(InterruptStatsProvider *obj,
4180 Monitor *mon)
4181{
4182 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
4183
4184 spapr->irq->print_info(spapr, mon);
4185}
4186
4187int spapr_get_vcpu_id(PowerPCCPU *cpu)
4188{
4189 return cpu->vcpu_id;
4190}
4191
4192void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
4193{
4194 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
4195 int vcpu_id;
4196
4197 vcpu_id = spapr_vcpu_id(spapr, cpu_index);
4198
4199 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
4200 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
4201 error_append_hint(errp, "Adjust the number of cpus to %d "
4202 "or try to raise the number of threads per core\n",
4203 vcpu_id * smp_threads / spapr->vsmt);
4204 return;
4205 }
4206
4207 cpu->vcpu_id = vcpu_id;
4208}
4209
4210PowerPCCPU *spapr_find_cpu(int vcpu_id)
4211{
4212 CPUState *cs;
4213
4214 CPU_FOREACH(cs) {
4215 PowerPCCPU *cpu = POWERPC_CPU(cs);
4216
4217 if (spapr_get_vcpu_id(cpu) == vcpu_id) {
4218 return cpu;
4219 }
4220 }
4221
4222 return NULL;
4223}
4224
4225static void spapr_machine_class_init(ObjectClass *oc, void *data)
4226{
4227 MachineClass *mc = MACHINE_CLASS(oc);
4228 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
4229 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
4230 NMIClass *nc = NMI_CLASS(oc);
4231 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
4232 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
4233 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
4234 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
4235
4236 mc->desc = "pSeries Logical Partition (PAPR compliant)";
4237 mc->ignore_boot_device_suffixes = true;
4238
4239
4240
4241
4242
4243
4244 mc->init = spapr_machine_init;
4245 mc->reset = spapr_machine_reset;
4246 mc->block_default_type = IF_SCSI;
4247 mc->max_cpus = 1024;
4248 mc->no_parallel = 1;
4249 mc->default_boot_order = "";
4250 mc->default_ram_size = 512 * MiB;
4251 mc->default_display = "std";
4252 mc->kvm_type = spapr_kvm_type;
4253 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
4254 mc->pci_allow_0_address = true;
4255 assert(!mc->get_hotplug_handler);
4256 mc->get_hotplug_handler = spapr_get_hotplug_handler;
4257 hc->pre_plug = spapr_machine_device_pre_plug;
4258 hc->plug = spapr_machine_device_plug;
4259 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
4260 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
4261 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
4262 hc->unplug_request = spapr_machine_device_unplug_request;
4263 hc->unplug = spapr_machine_device_unplug;
4264
4265 smc->dr_lmb_enabled = true;
4266 smc->update_dt_enabled = true;
4267 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
4268 mc->has_hotpluggable_cpus = true;
4269 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
4270 fwc->get_dev_path = spapr_get_fw_dev_path;
4271 nc->nmi_monitor_handler = spapr_nmi;
4272 smc->phb_placement = spapr_phb_placement;
4273 vhc->hypercall = emulate_spapr_hypercall;
4274 vhc->hpt_mask = spapr_hpt_mask;
4275 vhc->map_hptes = spapr_map_hptes;
4276 vhc->unmap_hptes = spapr_unmap_hptes;
4277 vhc->store_hpte = spapr_store_hpte;
4278 vhc->get_pate = spapr_get_pate;
4279 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
4280 xic->ics_get = spapr_ics_get;
4281 xic->ics_resend = spapr_ics_resend;
4282 xic->icp_get = spapr_icp_get;
4283 ispc->print_info = spapr_pic_print_info;
4284
4285
4286
4287
4288 mc->numa_mem_align_shift = 28;
4289
4290 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
4291 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
4292 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
4293 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4294 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4295 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND;
4296 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16;
4297 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
4298 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
4299 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF;
4300 spapr_caps_add_properties(smc, &error_abort);
4301 smc->irq = &spapr_irq_xics;
4302 smc->dr_phb_enabled = true;
4303}
4304
4305static const TypeInfo spapr_machine_info = {
4306 .name = TYPE_SPAPR_MACHINE,
4307 .parent = TYPE_MACHINE,
4308 .abstract = true,
4309 .instance_size = sizeof(SpaprMachineState),
4310 .instance_init = spapr_instance_init,
4311 .instance_finalize = spapr_machine_finalizefn,
4312 .class_size = sizeof(SpaprMachineClass),
4313 .class_init = spapr_machine_class_init,
4314 .interfaces = (InterfaceInfo[]) {
4315 { TYPE_FW_PATH_PROVIDER },
4316 { TYPE_NMI },
4317 { TYPE_HOTPLUG_HANDLER },
4318 { TYPE_PPC_VIRTUAL_HYPERVISOR },
4319 { TYPE_XICS_FABRIC },
4320 { TYPE_INTERRUPT_STATS_PROVIDER },
4321 { }
4322 },
4323};
4324
4325#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4326 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4327 void *data) \
4328 { \
4329 MachineClass *mc = MACHINE_CLASS(oc); \
4330 spapr_machine_##suffix##_class_options(mc); \
4331 if (latest) { \
4332 mc->alias = "pseries"; \
4333 mc->is_default = 1; \
4334 } \
4335 } \
4336 static const TypeInfo spapr_machine_##suffix##_info = { \
4337 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4338 .parent = TYPE_SPAPR_MACHINE, \
4339 .class_init = spapr_machine_##suffix##_class_init, \
4340 }; \
4341 static void spapr_machine_register_##suffix(void) \
4342 { \
4343 type_register(&spapr_machine_##suffix##_info); \
4344 } \
4345 type_init(spapr_machine_register_##suffix)
4346
4347
4348
4349
4350static void spapr_machine_4_0_class_options(MachineClass *mc)
4351{
4352
4353}
4354
4355DEFINE_SPAPR_MACHINE(4_0, "4.0", true);
4356
4357
4358
4359
4360static void spapr_machine_3_1_class_options(MachineClass *mc)
4361{
4362 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4363
4364 spapr_machine_4_0_class_options(mc);
4365 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
4366
4367 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
4368 smc->update_dt_enabled = false;
4369 smc->dr_phb_enabled = false;
4370 smc->broken_host_serial_model = true;
4371 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
4372 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
4373 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
4374 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;
4375}
4376
4377DEFINE_SPAPR_MACHINE(3_1, "3.1", false);
4378
4379
4380
4381
4382
4383static void spapr_machine_3_0_class_options(MachineClass *mc)
4384{
4385 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4386
4387 spapr_machine_3_1_class_options(mc);
4388 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
4389
4390 smc->legacy_irq_allocation = true;
4391 smc->irq = &spapr_irq_xics_legacy;
4392}
4393
4394DEFINE_SPAPR_MACHINE(3_0, "3.0", false);
4395
4396
4397
4398
4399static void spapr_machine_2_12_class_options(MachineClass *mc)
4400{
4401 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4402 static GlobalProperty compat[] = {
4403 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" },
4404 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" },
4405 };
4406
4407 spapr_machine_3_0_class_options(mc);
4408 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
4409 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4410
4411
4412
4413
4414
4415
4416 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
4417}
4418
4419DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
4420
4421static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc)
4422{
4423 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4424
4425 spapr_machine_2_12_class_options(mc);
4426 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4427 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4428 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
4429}
4430
4431DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false);
4432
4433
4434
4435
4436
4437static void spapr_machine_2_11_class_options(MachineClass *mc)
4438{
4439 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4440
4441 spapr_machine_2_12_class_options(mc);
4442 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
4443 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
4444}
4445
4446DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4447
4448
4449
4450
4451
4452static void spapr_machine_2_10_class_options(MachineClass *mc)
4453{
4454 spapr_machine_2_11_class_options(mc);
4455 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
4456}
4457
4458DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4459
4460
4461
4462
4463
4464static void spapr_machine_2_9_class_options(MachineClass *mc)
4465{
4466 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4467 static GlobalProperty compat[] = {
4468 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" },
4469 };
4470
4471 spapr_machine_2_10_class_options(mc);
4472 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
4473 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4474 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4475 smc->pre_2_10_has_unused_icps = true;
4476 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4477}
4478
4479DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4480
4481
4482
4483
4484
4485static void spapr_machine_2_8_class_options(MachineClass *mc)
4486{
4487 static GlobalProperty compat[] = {
4488 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" },
4489 };
4490
4491 spapr_machine_2_9_class_options(mc);
4492 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
4493 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4494 mc->numa_mem_align_shift = 23;
4495}
4496
4497DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4498
4499
4500
4501
4502
4503static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index,
4504 uint64_t *buid, hwaddr *pio,
4505 hwaddr *mmio32, hwaddr *mmio64,
4506 unsigned n_dma, uint32_t *liobns, Error **errp)
4507{
4508
4509 const uint64_t base_buid = 0x800000020000000ULL;
4510 const hwaddr phb_spacing = 0x1000000000ULL;
4511 const hwaddr mmio_offset = 0xa0000000;
4512 const hwaddr pio_offset = 0x80000000;
4513 const uint32_t max_index = 255;
4514 const hwaddr phb0_alignment = 0x10000000000ULL;
4515
4516 uint64_t ram_top = MACHINE(spapr)->ram_size;
4517 hwaddr phb0_base, phb_base;
4518 int i;
4519
4520
4521 if (MACHINE(spapr)->maxram_size > ram_top) {
4522
4523
4524
4525 ram_top = MACHINE(spapr)->device_memory->base +
4526 memory_region_size(&MACHINE(spapr)->device_memory->mr);
4527 }
4528
4529 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4530
4531 if (index > max_index) {
4532 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4533 max_index);
4534 return;
4535 }
4536
4537 *buid = base_buid + index;
4538 for (i = 0; i < n_dma; ++i) {
4539 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4540 }
4541
4542 phb_base = phb0_base + index * phb_spacing;
4543 *pio = phb_base + pio_offset;
4544 *mmio32 = phb_base + mmio_offset;
4545
4546
4547
4548
4549
4550}
4551
4552static void spapr_machine_2_7_class_options(MachineClass *mc)
4553{
4554 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4555 static GlobalProperty compat[] = {
4556 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", },
4557 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", },
4558 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", },
4559 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", },
4560 };
4561
4562 spapr_machine_2_8_class_options(mc);
4563 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4564 mc->default_machine_opts = "modern-hotplug-events=off";
4565 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
4566 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4567 smc->phb_placement = phb_placement_2_7;
4568}
4569
4570DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4571
4572
4573
4574
4575
4576static void spapr_machine_2_6_class_options(MachineClass *mc)
4577{
4578 static GlobalProperty compat[] = {
4579 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" },
4580 };
4581
4582 spapr_machine_2_7_class_options(mc);
4583 mc->has_hotpluggable_cpus = false;
4584 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
4585 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4586}
4587
4588DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4589
4590
4591
4592
4593
4594static void spapr_machine_2_5_class_options(MachineClass *mc)
4595{
4596 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4597 static GlobalProperty compat[] = {
4598 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4599 };
4600
4601 spapr_machine_2_6_class_options(mc);
4602 smc->use_ohci_by_default = true;
4603 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len);
4604 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4605}
4606
4607DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4608
4609
4610
4611
4612
4613static void spapr_machine_2_4_class_options(MachineClass *mc)
4614{
4615 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4616
4617 spapr_machine_2_5_class_options(mc);
4618 smc->dr_lmb_enabled = false;
4619 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len);
4620}
4621
4622DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4623
4624
4625
4626
4627
4628static void spapr_machine_2_3_class_options(MachineClass *mc)
4629{
4630 static GlobalProperty compat[] = {
4631 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4632 };
4633 spapr_machine_2_4_class_options(mc);
4634 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len);
4635 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4636}
4637DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4638
4639
4640
4641
4642
4643static void spapr_machine_2_2_class_options(MachineClass *mc)
4644{
4645 static GlobalProperty compat[] = {
4646 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" },
4647 };
4648
4649 spapr_machine_2_3_class_options(mc);
4650 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len);
4651 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4652 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on";
4653}
4654DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4655
4656
4657
4658
4659
4660static void spapr_machine_2_1_class_options(MachineClass *mc)
4661{
4662 spapr_machine_2_2_class_options(mc);
4663 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len);
4664}
4665DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4666
4667static void spapr_machine_register_types(void)
4668{
4669 type_register_static(&spapr_machine_info);
4670}
4671
4672type_init(spapr_machine_register_types)
4673