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9#include "qemu/osdep.h"
10#include "hw/cpu/core.h"
11#include "hw/ppc/spapr_cpu_core.h"
12#include "target/ppc/cpu.h"
13#include "hw/ppc/spapr.h"
14#include "hw/boards.h"
15#include "qapi/error.h"
16#include "sysemu/cpus.h"
17#include "sysemu/kvm.h"
18#include "target/ppc/kvm_ppc.h"
19#include "hw/ppc/ppc.h"
20#include "target/ppc/mmu-hash64.h"
21#include "sysemu/numa.h"
22#include "sysemu/hw_accel.h"
23#include "qemu/error-report.h"
24
25static void spapr_cpu_reset(void *opaque)
26{
27 PowerPCCPU *cpu = opaque;
28 CPUState *cs = CPU(cpu);
29 CPUPPCState *env = &cpu->env;
30 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
31 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
32 target_ulong lpcr;
33
34 cpu_reset(cs);
35
36
37
38
39 cs->halted = 1;
40
41
42
43
44 ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
45
46 env->spr[SPR_HIOR] = 0;
47
48 lpcr = env->spr[SPR_LPCR];
49
50
51
52
53
54
55
56
57
58
59
60
61
62 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
63 lpcr |= LPCR_LPES0 | LPCR_LPES1;
64
65
66 lpcr &= ~LPCR_RMLS;
67 lpcr |= 1ull << LPCR_RMLS_SHIFT;
68
69 ppc_store_lpcr(cpu, lpcr);
70
71
72 env->spr[SPR_AMOR] = 0xffffffffffffffffull;
73
74 spapr_cpu->vpa_addr = 0;
75 spapr_cpu->slb_shadow_addr = 0;
76 spapr_cpu->slb_shadow_size = 0;
77 spapr_cpu->dtl_addr = 0;
78 spapr_cpu->dtl_size = 0;
79
80 spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu);
81
82 kvm_check_mmu(cpu, &error_fatal);
83}
84
85void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
86{
87 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
88 CPUPPCState *env = &cpu->env;
89
90 env->nip = nip;
91 env->gpr[3] = r3;
92 kvmppc_set_reg_ppc_online(cpu, 1);
93 CPU(cpu)->halted = 0;
94
95 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
96}
97
98
99
100
101
102const char *spapr_get_cpu_core_type(const char *cpu_type)
103{
104 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
105 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
106 len, cpu_type);
107 ObjectClass *oc = object_class_by_name(core_type);
108
109 g_free(core_type);
110 if (!oc) {
111 return NULL;
112 }
113
114 return object_class_get_name(oc);
115}
116
117static bool slb_shadow_needed(void *opaque)
118{
119 SpaprCpuState *spapr_cpu = opaque;
120
121 return spapr_cpu->slb_shadow_addr != 0;
122}
123
124static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
125 .name = "spapr_cpu/vpa/slb_shadow",
126 .version_id = 1,
127 .minimum_version_id = 1,
128 .needed = slb_shadow_needed,
129 .fields = (VMStateField[]) {
130 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
131 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
132 VMSTATE_END_OF_LIST()
133 }
134};
135
136static bool dtl_needed(void *opaque)
137{
138 SpaprCpuState *spapr_cpu = opaque;
139
140 return spapr_cpu->dtl_addr != 0;
141}
142
143static const VMStateDescription vmstate_spapr_cpu_dtl = {
144 .name = "spapr_cpu/vpa/dtl",
145 .version_id = 1,
146 .minimum_version_id = 1,
147 .needed = dtl_needed,
148 .fields = (VMStateField[]) {
149 VMSTATE_UINT64(dtl_addr, SpaprCpuState),
150 VMSTATE_UINT64(dtl_size, SpaprCpuState),
151 VMSTATE_END_OF_LIST()
152 }
153};
154
155static bool vpa_needed(void *opaque)
156{
157 SpaprCpuState *spapr_cpu = opaque;
158
159 return spapr_cpu->vpa_addr != 0;
160}
161
162static const VMStateDescription vmstate_spapr_cpu_vpa = {
163 .name = "spapr_cpu/vpa",
164 .version_id = 1,
165 .minimum_version_id = 1,
166 .needed = vpa_needed,
167 .fields = (VMStateField[]) {
168 VMSTATE_UINT64(vpa_addr, SpaprCpuState),
169 VMSTATE_END_OF_LIST()
170 },
171 .subsections = (const VMStateDescription * []) {
172 &vmstate_spapr_cpu_slb_shadow,
173 &vmstate_spapr_cpu_dtl,
174 NULL
175 }
176};
177
178static const VMStateDescription vmstate_spapr_cpu_state = {
179 .name = "spapr_cpu",
180 .version_id = 1,
181 .minimum_version_id = 1,
182 .fields = (VMStateField[]) {
183 VMSTATE_END_OF_LIST()
184 },
185 .subsections = (const VMStateDescription * []) {
186 &vmstate_spapr_cpu_vpa,
187 NULL
188 }
189};
190
191static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
192{
193 if (!sc->pre_3_0_migration) {
194 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
195 }
196 qemu_unregister_reset(spapr_cpu_reset, cpu);
197 if (spapr_cpu_state(cpu)->icp) {
198 object_unparent(OBJECT(spapr_cpu_state(cpu)->icp));
199 }
200 if (spapr_cpu_state(cpu)->tctx) {
201 object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx));
202 }
203 cpu_remove_sync(CPU(cpu));
204 object_unparent(OBJECT(cpu));
205}
206
207static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
208{
209 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
210 CPUCore *cc = CPU_CORE(dev);
211 int i;
212
213 for (i = 0; i < cc->nr_threads; i++) {
214 spapr_unrealize_vcpu(sc->threads[i], sc);
215 }
216 g_free(sc->threads);
217}
218
219static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
220 SpaprCpuCore *sc, Error **errp)
221{
222 CPUPPCState *env = &cpu->env;
223 CPUState *cs = CPU(cpu);
224 Error *local_err = NULL;
225
226 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
227 if (local_err) {
228 goto error;
229 }
230
231
232 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
233
234 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
235 kvmppc_set_papr(cpu);
236
237 qemu_register_reset(spapr_cpu_reset, cpu);
238 spapr_cpu_reset(cpu);
239
240 spapr->irq->cpu_intc_create(spapr, cpu, &local_err);
241 if (local_err) {
242 goto error_unregister;
243 }
244
245 if (!sc->pre_3_0_migration) {
246 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
247 cpu->machine_data);
248 }
249
250 return;
251
252error_unregister:
253 qemu_unregister_reset(spapr_cpu_reset, cpu);
254 cpu_remove_sync(CPU(cpu));
255error:
256 error_propagate(errp, local_err);
257}
258
259static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
260{
261 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
262 CPUCore *cc = CPU_CORE(sc);
263 Object *obj;
264 char *id;
265 CPUState *cs;
266 PowerPCCPU *cpu;
267 Error *local_err = NULL;
268
269 obj = object_new(scc->cpu_type);
270
271 cs = CPU(obj);
272 cpu = POWERPC_CPU(obj);
273 cs->cpu_index = cc->core_id + i;
274 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
275 if (local_err) {
276 goto err;
277 }
278
279 cpu->node_id = sc->node_id;
280
281 id = g_strdup_printf("thread[%d]", i);
282 object_property_add_child(OBJECT(sc), id, obj, &local_err);
283 g_free(id);
284 if (local_err) {
285 goto err;
286 }
287
288 cpu->machine_data = g_new0(SpaprCpuState, 1);
289
290 object_unref(obj);
291 return cpu;
292
293err:
294 object_unref(obj);
295 error_propagate(errp, local_err);
296 return NULL;
297}
298
299static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
300{
301 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
302
303 cpu->machine_data = NULL;
304 g_free(spapr_cpu);
305 object_unparent(OBJECT(cpu));
306}
307
308static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
309{
310
311
312
313 SpaprMachineState *spapr =
314 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
315 TYPE_SPAPR_MACHINE);
316 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
317 CPUCore *cc = CPU_CORE(OBJECT(dev));
318 Error *local_err = NULL;
319 int i, j;
320
321 if (!spapr) {
322 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
323 return;
324 }
325
326 sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
327 for (i = 0; i < cc->nr_threads; i++) {
328 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
329 if (local_err) {
330 goto err;
331 }
332 }
333
334 for (j = 0; j < cc->nr_threads; j++) {
335 spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err);
336 if (local_err) {
337 goto err_unrealize;
338 }
339 }
340 return;
341
342err_unrealize:
343 while (--j >= 0) {
344 spapr_unrealize_vcpu(sc->threads[j], sc);
345 }
346err:
347 while (--i >= 0) {
348 spapr_delete_vcpu(sc->threads[i], sc);
349 }
350 g_free(sc->threads);
351 error_propagate(errp, local_err);
352}
353
354static Property spapr_cpu_core_properties[] = {
355 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
356 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
357 false),
358 DEFINE_PROP_END_OF_LIST()
359};
360
361static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
362{
363 DeviceClass *dc = DEVICE_CLASS(oc);
364 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
365
366 dc->realize = spapr_cpu_core_realize;
367 dc->unrealize = spapr_cpu_core_unrealize;
368 dc->props = spapr_cpu_core_properties;
369 scc->cpu_type = data;
370}
371
372#define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
373 { \
374 .parent = TYPE_SPAPR_CPU_CORE, \
375 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
376 .class_init = spapr_cpu_core_class_init, \
377 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
378 }
379
380static const TypeInfo spapr_cpu_core_type_infos[] = {
381 {
382 .name = TYPE_SPAPR_CPU_CORE,
383 .parent = TYPE_CPU_CORE,
384 .abstract = true,
385 .instance_size = sizeof(SpaprCpuCore),
386 .class_size = sizeof(SpaprCpuCoreClass),
387 },
388 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
389 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
390 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
391 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
392 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
393 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
394 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
395 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
396 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
397 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
398 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
399#ifdef CONFIG_KVM
400 DEFINE_SPAPR_CPU_CORE_TYPE("host"),
401#endif
402};
403
404DEFINE_TYPES(spapr_cpu_core_type_infos)
405
