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16#include "qemu/osdep.h"
17#include "qapi/error.h"
18#include "hw/hw.h"
19#include "hw/pci/pci.h"
20#include "hw/pci/pci_ids.h"
21#include "hw/pci/msi.h"
22#include "hw/pci/msix.h"
23#include "hw/qdev-core.h"
24#include "hw/qdev-properties.h"
25#include "cpu.h"
26#include "trace.h"
27#include "sysemu/sysemu.h"
28#include "monitor/monitor.h"
29#include "hw/rdma/rdma.h"
30
31#include "../rdma_rm.h"
32#include "../rdma_backend.h"
33#include "../rdma_utils.h"
34
35#include <infiniband/verbs.h>
36#include "pvrdma.h"
37#include "standard-headers/rdma/vmw_pvrdma-abi.h"
38#include "standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h"
39#include "pvrdma_qp_ops.h"
40
41static Property pvrdma_dev_properties[] = {
42 DEFINE_PROP_STRING("netdev", PVRDMADev, backend_eth_device_name),
43 DEFINE_PROP_STRING("ibdev", PVRDMADev, backend_device_name),
44 DEFINE_PROP_UINT8("ibport", PVRDMADev, backend_port_num, 1),
45 DEFINE_PROP_UINT64("dev-caps-max-mr-size", PVRDMADev, dev_attr.max_mr_size,
46 MAX_MR_SIZE),
47 DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
48 DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
49 DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
50 DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
51 DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
52 MAX_QP_RD_ATOM),
53 DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
54 dev_attr.max_qp_init_rd_atom, MAX_QP_INIT_RD_ATOM),
55 DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
56 DEFINE_PROP_CHR("mad-chardev", PVRDMADev, mad_chr),
57 DEFINE_PROP_END_OF_LIST(),
58};
59
60static void pvrdma_print_statistics(Monitor *mon, RdmaProvider *obj)
61{
62 PVRDMADev *dev = PVRDMA_DEV(obj);
63 PCIDevice *pdev = PCI_DEVICE(dev);
64
65 monitor_printf(mon, "%s, %x.%x\n", pdev->name, PCI_SLOT(pdev->devfn),
66 PCI_FUNC(pdev->devfn));
67 monitor_printf(mon, "\tcommands : %" PRId64 "\n",
68 dev->stats.commands);
69 monitor_printf(mon, "\tregs_reads : %" PRId64 "\n",
70 dev->stats.regs_reads);
71 monitor_printf(mon, "\tregs_writes : %" PRId64 "\n",
72 dev->stats.regs_writes);
73 monitor_printf(mon, "\tuar_writes : %" PRId64 "\n",
74 dev->stats.uar_writes);
75 monitor_printf(mon, "\tinterrupts : %" PRId64 "\n",
76 dev->stats.interrupts);
77 rdma_dump_device_counters(mon, &dev->rdma_dev_res);
78}
79
80static void free_dev_ring(PCIDevice *pci_dev, PvrdmaRing *ring,
81 void *ring_state)
82{
83 pvrdma_ring_free(ring);
84 rdma_pci_dma_unmap(pci_dev, ring_state, TARGET_PAGE_SIZE);
85}
86
87static int init_dev_ring(PvrdmaRing *ring, struct pvrdma_ring **ring_state,
88 const char *name, PCIDevice *pci_dev,
89 dma_addr_t dir_addr, uint32_t num_pages)
90{
91 uint64_t *dir, *tbl;
92 int rc = 0;
93
94 dir = rdma_pci_dma_map(pci_dev, dir_addr, TARGET_PAGE_SIZE);
95 if (!dir) {
96 rdma_error_report("Failed to map to page directory (ring %s)", name);
97 rc = -ENOMEM;
98 goto out;
99 }
100 tbl = rdma_pci_dma_map(pci_dev, dir[0], TARGET_PAGE_SIZE);
101 if (!tbl) {
102 rdma_error_report("Failed to map to page table (ring %s)", name);
103 rc = -ENOMEM;
104 goto out_free_dir;
105 }
106
107 *ring_state = rdma_pci_dma_map(pci_dev, tbl[0], TARGET_PAGE_SIZE);
108 if (!*ring_state) {
109 rdma_error_report("Failed to map to ring state (ring %s)", name);
110 rc = -ENOMEM;
111 goto out_free_tbl;
112 }
113
114 (*ring_state)++;
115 rc = pvrdma_ring_init(ring, name, pci_dev,
116 (struct pvrdma_ring *)*ring_state,
117 (num_pages - 1) * TARGET_PAGE_SIZE /
118 sizeof(struct pvrdma_cqne),
119 sizeof(struct pvrdma_cqne),
120 (dma_addr_t *)&tbl[1], (dma_addr_t)num_pages - 1);
121 if (rc) {
122 rc = -ENOMEM;
123 goto out_free_ring_state;
124 }
125
126 goto out_free_tbl;
127
128out_free_ring_state:
129 rdma_pci_dma_unmap(pci_dev, *ring_state, TARGET_PAGE_SIZE);
130
131out_free_tbl:
132 rdma_pci_dma_unmap(pci_dev, tbl, TARGET_PAGE_SIZE);
133
134out_free_dir:
135 rdma_pci_dma_unmap(pci_dev, dir, TARGET_PAGE_SIZE);
136
137out:
138 return rc;
139}
140
141static void free_dsr(PVRDMADev *dev)
142{
143 PCIDevice *pci_dev = PCI_DEVICE(dev);
144
145 if (!dev->dsr_info.dsr) {
146 return;
147 }
148
149 free_dev_ring(pci_dev, &dev->dsr_info.async,
150 dev->dsr_info.async_ring_state);
151
152 free_dev_ring(pci_dev, &dev->dsr_info.cq, dev->dsr_info.cq_ring_state);
153
154 rdma_pci_dma_unmap(pci_dev, dev->dsr_info.req,
155 sizeof(union pvrdma_cmd_req));
156
157 rdma_pci_dma_unmap(pci_dev, dev->dsr_info.rsp,
158 sizeof(union pvrdma_cmd_resp));
159
160 rdma_pci_dma_unmap(pci_dev, dev->dsr_info.dsr,
161 sizeof(struct pvrdma_device_shared_region));
162
163 dev->dsr_info.dsr = NULL;
164}
165
166static int load_dsr(PVRDMADev *dev)
167{
168 int rc = 0;
169 PCIDevice *pci_dev = PCI_DEVICE(dev);
170 DSRInfo *dsr_info;
171 struct pvrdma_device_shared_region *dsr;
172
173 free_dsr(dev);
174
175
176 dev->dsr_info.dsr = rdma_pci_dma_map(pci_dev, dev->dsr_info.dma,
177 sizeof(struct pvrdma_device_shared_region));
178 if (!dev->dsr_info.dsr) {
179 rdma_error_report("Failed to map to DSR");
180 rc = -ENOMEM;
181 goto out;
182 }
183
184
185 dsr_info = &dev->dsr_info;
186 dsr = dsr_info->dsr;
187
188
189 dsr_info->req = rdma_pci_dma_map(pci_dev, dsr->cmd_slot_dma,
190 sizeof(union pvrdma_cmd_req));
191 if (!dsr_info->req) {
192 rdma_error_report("Failed to map to command slot address");
193 rc = -ENOMEM;
194 goto out_free_dsr;
195 }
196
197
198 dsr_info->rsp = rdma_pci_dma_map(pci_dev, dsr->resp_slot_dma,
199 sizeof(union pvrdma_cmd_resp));
200 if (!dsr_info->rsp) {
201 rdma_error_report("Failed to map to response slot address");
202 rc = -ENOMEM;
203 goto out_free_req;
204 }
205
206
207 rc = init_dev_ring(&dsr_info->cq, &dsr_info->cq_ring_state, "dev_cq",
208 pci_dev, dsr->cq_ring_pages.pdir_dma,
209 dsr->cq_ring_pages.num_pages);
210 if (rc) {
211 rc = -ENOMEM;
212 goto out_free_rsp;
213 }
214
215
216 rc = init_dev_ring(&dsr_info->async, &dsr_info->async_ring_state,
217 "dev_async", pci_dev, dsr->async_ring_pages.pdir_dma,
218 dsr->async_ring_pages.num_pages);
219 if (rc) {
220 rc = -ENOMEM;
221 goto out_free_rsp;
222 }
223
224 goto out;
225
226out_free_rsp:
227 rdma_pci_dma_unmap(pci_dev, dsr_info->rsp, sizeof(union pvrdma_cmd_resp));
228
229out_free_req:
230 rdma_pci_dma_unmap(pci_dev, dsr_info->req, sizeof(union pvrdma_cmd_req));
231
232out_free_dsr:
233 rdma_pci_dma_unmap(pci_dev, dsr_info->dsr,
234 sizeof(struct pvrdma_device_shared_region));
235 dsr_info->dsr = NULL;
236
237out:
238 return rc;
239}
240
241static void init_dsr_dev_caps(PVRDMADev *dev)
242{
243 struct pvrdma_device_shared_region *dsr;
244
245 if (dev->dsr_info.dsr == NULL) {
246 rdma_error_report("Can't initialized DSR");
247 return;
248 }
249
250 dsr = dev->dsr_info.dsr;
251 dsr->caps.fw_ver = PVRDMA_FW_VERSION;
252 dsr->caps.mode = PVRDMA_DEVICE_MODE_ROCE;
253 dsr->caps.gid_types |= PVRDMA_GID_TYPE_FLAG_ROCE_V1;
254 dsr->caps.max_uar = RDMA_BAR2_UAR_SIZE;
255 dsr->caps.max_mr_size = dev->dev_attr.max_mr_size;
256 dsr->caps.max_qp = dev->dev_attr.max_qp;
257 dsr->caps.max_qp_wr = dev->dev_attr.max_qp_wr;
258 dsr->caps.max_sge = dev->dev_attr.max_sge;
259 dsr->caps.max_cq = dev->dev_attr.max_cq;
260 dsr->caps.max_cqe = dev->dev_attr.max_cqe;
261 dsr->caps.max_mr = dev->dev_attr.max_mr;
262 dsr->caps.max_pd = dev->dev_attr.max_pd;
263 dsr->caps.max_ah = dev->dev_attr.max_ah;
264 dsr->caps.gid_tbl_len = MAX_GIDS;
265 dsr->caps.sys_image_guid = 0;
266 dsr->caps.node_guid = dev->node_guid;
267 dsr->caps.phys_port_cnt = MAX_PORTS;
268 dsr->caps.max_pkeys = MAX_PKEYS;
269}
270
271static void uninit_msix(PCIDevice *pdev, int used_vectors)
272{
273 PVRDMADev *dev = PVRDMA_DEV(pdev);
274 int i;
275
276 for (i = 0; i < used_vectors; i++) {
277 msix_vector_unuse(pdev, i);
278 }
279
280 msix_uninit(pdev, &dev->msix, &dev->msix);
281}
282
283static int init_msix(PCIDevice *pdev)
284{
285 PVRDMADev *dev = PVRDMA_DEV(pdev);
286 int i;
287 int rc;
288
289 rc = msix_init(pdev, RDMA_MAX_INTRS, &dev->msix, RDMA_MSIX_BAR_IDX,
290 RDMA_MSIX_TABLE, &dev->msix, RDMA_MSIX_BAR_IDX,
291 RDMA_MSIX_PBA, 0, NULL);
292
293 if (rc < 0) {
294 rdma_error_report("Failed to initialize MSI-X");
295 return rc;
296 }
297
298 for (i = 0; i < RDMA_MAX_INTRS; i++) {
299 rc = msix_vector_use(PCI_DEVICE(dev), i);
300 if (rc < 0) {
301 rdma_error_report("Fail mark MSI-X vector %d", i);
302 uninit_msix(pdev, i);
303 return rc;
304 }
305 }
306
307 return 0;
308}
309
310static void pvrdma_fini(PCIDevice *pdev)
311{
312 PVRDMADev *dev = PVRDMA_DEV(pdev);
313
314 notifier_remove(&dev->shutdown_notifier);
315
316 pvrdma_qp_ops_fini();
317
318 rdma_backend_stop(&dev->backend_dev);
319
320 rdma_rm_fini(&dev->rdma_dev_res, &dev->backend_dev,
321 dev->backend_eth_device_name);
322
323 rdma_backend_fini(&dev->backend_dev);
324
325 free_dsr(dev);
326
327 if (msix_enabled(pdev)) {
328 uninit_msix(pdev, RDMA_MAX_INTRS);
329 }
330
331 rdma_info_report("Device %s %x.%x is down", pdev->name,
332 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
333}
334
335static void pvrdma_stop(PVRDMADev *dev)
336{
337 rdma_backend_stop(&dev->backend_dev);
338}
339
340static void pvrdma_start(PVRDMADev *dev)
341{
342 rdma_backend_start(&dev->backend_dev);
343}
344
345static void activate_device(PVRDMADev *dev)
346{
347 pvrdma_start(dev);
348 set_reg_val(dev, PVRDMA_REG_ERR, 0);
349}
350
351static int unquiesce_device(PVRDMADev *dev)
352{
353 return 0;
354}
355
356static void reset_device(PVRDMADev *dev)
357{
358 pvrdma_stop(dev);
359}
360
361static uint64_t pvrdma_regs_read(void *opaque, hwaddr addr, unsigned size)
362{
363 PVRDMADev *dev = opaque;
364 uint32_t val;
365
366 dev->stats.regs_reads++;
367
368 if (get_reg_val(dev, addr, &val)) {
369 rdma_error_report("Failed to read REG value from address 0x%x",
370 (uint32_t)addr);
371 return -EINVAL;
372 }
373
374 trace_pvrdma_regs_read(addr, val);
375
376 return val;
377}
378
379static void pvrdma_regs_write(void *opaque, hwaddr addr, uint64_t val,
380 unsigned size)
381{
382 PVRDMADev *dev = opaque;
383
384 dev->stats.regs_writes++;
385
386 if (set_reg_val(dev, addr, val)) {
387 rdma_error_report("Failed to set REG value, addr=0x%"PRIx64 ", val=0x%"PRIx64,
388 addr, val);
389 return;
390 }
391
392 switch (addr) {
393 case PVRDMA_REG_DSRLOW:
394 trace_pvrdma_regs_write(addr, val, "DSRLOW", "");
395 dev->dsr_info.dma = val;
396 break;
397 case PVRDMA_REG_DSRHIGH:
398 trace_pvrdma_regs_write(addr, val, "DSRHIGH", "");
399 dev->dsr_info.dma |= val << 32;
400 load_dsr(dev);
401 init_dsr_dev_caps(dev);
402 break;
403 case PVRDMA_REG_CTL:
404 switch (val) {
405 case PVRDMA_DEVICE_CTL_ACTIVATE:
406 trace_pvrdma_regs_write(addr, val, "CTL", "ACTIVATE");
407 activate_device(dev);
408 break;
409 case PVRDMA_DEVICE_CTL_UNQUIESCE:
410 trace_pvrdma_regs_write(addr, val, "CTL", "UNQUIESCE");
411 unquiesce_device(dev);
412 break;
413 case PVRDMA_DEVICE_CTL_RESET:
414 trace_pvrdma_regs_write(addr, val, "CTL", "URESET");
415 reset_device(dev);
416 break;
417 }
418 break;
419 case PVRDMA_REG_IMR:
420 trace_pvrdma_regs_write(addr, val, "INTR_MASK", "");
421 dev->interrupt_mask = val;
422 break;
423 case PVRDMA_REG_REQUEST:
424 if (val == 0) {
425 trace_pvrdma_regs_write(addr, val, "REQUEST", "");
426 pvrdma_exec_cmd(dev);
427 }
428 break;
429 default:
430 break;
431 }
432}
433
434static const MemoryRegionOps regs_ops = {
435 .read = pvrdma_regs_read,
436 .write = pvrdma_regs_write,
437 .endianness = DEVICE_LITTLE_ENDIAN,
438 .impl = {
439 .min_access_size = sizeof(uint32_t),
440 .max_access_size = sizeof(uint32_t),
441 },
442};
443
444static uint64_t pvrdma_uar_read(void *opaque, hwaddr addr, unsigned size)
445{
446 return 0xffffffff;
447}
448
449static void pvrdma_uar_write(void *opaque, hwaddr addr, uint64_t val,
450 unsigned size)
451{
452 PVRDMADev *dev = opaque;
453
454 dev->stats.uar_writes++;
455
456 switch (addr & 0xFFF) {
457 case PVRDMA_UAR_QP_OFFSET:
458 if (val & PVRDMA_UAR_QP_SEND) {
459 trace_pvrdma_uar_write(addr, val, "QP", "SEND",
460 val & PVRDMA_UAR_HANDLE_MASK, 0);
461 pvrdma_qp_send(dev, val & PVRDMA_UAR_HANDLE_MASK);
462 }
463 if (val & PVRDMA_UAR_QP_RECV) {
464 trace_pvrdma_uar_write(addr, val, "QP", "RECV",
465 val & PVRDMA_UAR_HANDLE_MASK, 0);
466 pvrdma_qp_recv(dev, val & PVRDMA_UAR_HANDLE_MASK);
467 }
468 break;
469 case PVRDMA_UAR_CQ_OFFSET:
470 if (val & PVRDMA_UAR_CQ_ARM) {
471 trace_pvrdma_uar_write(addr, val, "CQ", "ARM",
472 val & PVRDMA_UAR_HANDLE_MASK,
473 !!(val & PVRDMA_UAR_CQ_ARM_SOL));
474 rdma_rm_req_notify_cq(&dev->rdma_dev_res,
475 val & PVRDMA_UAR_HANDLE_MASK,
476 !!(val & PVRDMA_UAR_CQ_ARM_SOL));
477 }
478 if (val & PVRDMA_UAR_CQ_ARM_SOL) {
479 trace_pvrdma_uar_write(addr, val, "CQ", "ARMSOL - not supported", 0,
480 0);
481 }
482 if (val & PVRDMA_UAR_CQ_POLL) {
483 trace_pvrdma_uar_write(addr, val, "CQ", "POLL",
484 val & PVRDMA_UAR_HANDLE_MASK, 0);
485 pvrdma_cq_poll(&dev->rdma_dev_res, val & PVRDMA_UAR_HANDLE_MASK);
486 }
487 break;
488 default:
489 rdma_error_report("Unsupported command, addr=0x%"PRIx64", val=0x%"PRIx64,
490 addr, val);
491 break;
492 }
493}
494
495static const MemoryRegionOps uar_ops = {
496 .read = pvrdma_uar_read,
497 .write = pvrdma_uar_write,
498 .endianness = DEVICE_LITTLE_ENDIAN,
499 .impl = {
500 .min_access_size = sizeof(uint32_t),
501 .max_access_size = sizeof(uint32_t),
502 },
503};
504
505static void init_pci_config(PCIDevice *pdev)
506{
507 pdev->config[PCI_INTERRUPT_PIN] = 1;
508}
509
510static void init_bars(PCIDevice *pdev)
511{
512 PVRDMADev *dev = PVRDMA_DEV(pdev);
513
514
515 memory_region_init(&dev->msix, OBJECT(dev), "pvrdma-msix",
516 RDMA_BAR0_MSIX_SIZE);
517 pci_register_bar(pdev, RDMA_MSIX_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
518 &dev->msix);
519
520
521 memset(&dev->regs_data, 0, sizeof(dev->regs_data));
522 memory_region_init_io(&dev->regs, OBJECT(dev), ®s_ops, dev,
523 "pvrdma-regs", sizeof(dev->regs_data));
524 pci_register_bar(pdev, RDMA_REG_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
525 &dev->regs);
526
527
528 memset(&dev->uar_data, 0, sizeof(dev->uar_data));
529 memory_region_init_io(&dev->uar, OBJECT(dev), &uar_ops, dev, "rdma-uar",
530 sizeof(dev->uar_data));
531 pci_register_bar(pdev, RDMA_UAR_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
532 &dev->uar);
533}
534
535static void init_regs(PCIDevice *pdev)
536{
537 PVRDMADev *dev = PVRDMA_DEV(pdev);
538
539 set_reg_val(dev, PVRDMA_REG_VERSION, PVRDMA_HW_VERSION);
540 set_reg_val(dev, PVRDMA_REG_ERR, 0xFFFF);
541}
542
543static void init_dev_caps(PVRDMADev *dev)
544{
545 size_t pg_tbl_bytes = TARGET_PAGE_SIZE *
546 (TARGET_PAGE_SIZE / sizeof(uint64_t));
547 size_t wr_sz = MAX(sizeof(struct pvrdma_sq_wqe_hdr),
548 sizeof(struct pvrdma_rq_wqe_hdr));
549
550 dev->dev_attr.max_qp_wr = pg_tbl_bytes /
551 (wr_sz + sizeof(struct pvrdma_sge) *
552 dev->dev_attr.max_sge) - TARGET_PAGE_SIZE;
553
554
555 dev->dev_attr.max_cqe = pg_tbl_bytes / sizeof(struct pvrdma_cqe) -
556 TARGET_PAGE_SIZE;
557}
558
559static int pvrdma_check_ram_shared(Object *obj, void *opaque)
560{
561 bool *shared = opaque;
562
563 if (object_dynamic_cast(obj, "memory-backend-ram")) {
564 *shared = object_property_get_bool(obj, "share", NULL);
565 }
566
567 return 0;
568}
569
570static void pvrdma_shutdown_notifier(Notifier *n, void *opaque)
571{
572 PVRDMADev *dev = container_of(n, PVRDMADev, shutdown_notifier);
573 PCIDevice *pci_dev = PCI_DEVICE(dev);
574
575 pvrdma_fini(pci_dev);
576}
577
578static void pvrdma_realize(PCIDevice *pdev, Error **errp)
579{
580 int rc = 0;
581 PVRDMADev *dev = PVRDMA_DEV(pdev);
582 Object *memdev_root;
583 bool ram_shared = false;
584 PCIDevice *func0;
585
586 rdma_info_report("Initializing device %s %x.%x", pdev->name,
587 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
588
589 if (TARGET_PAGE_SIZE != getpagesize()) {
590 error_setg(errp, "Target page size must be the same as host page size");
591 return;
592 }
593
594 func0 = pci_get_function_0(pdev);
595
596 if (strcmp(object_get_typename(OBJECT(func0)), TYPE_VMXNET3)) {
597 error_setg(errp, "Device on %x.0 must be %s", PCI_SLOT(pdev->devfn),
598 TYPE_VMXNET3);
599 return;
600 }
601 dev->func0 = VMXNET3(func0);
602
603 addrconf_addr_eui48((unsigned char *)&dev->node_guid,
604 (const char *)&dev->func0->conf.macaddr.a);
605
606 memdev_root = object_resolve_path("/objects", NULL);
607 if (memdev_root) {
608 object_child_foreach(memdev_root, pvrdma_check_ram_shared, &ram_shared);
609 }
610 if (!ram_shared) {
611 error_setg(errp, "Only shared memory backed ram is supported");
612 return;
613 }
614
615 dev->dsr_info.dsr = NULL;
616
617 init_pci_config(pdev);
618
619 init_bars(pdev);
620
621 init_regs(pdev);
622
623 rc = init_msix(pdev);
624 if (rc) {
625 goto out;
626 }
627
628 rc = rdma_backend_init(&dev->backend_dev, pdev, &dev->rdma_dev_res,
629 dev->backend_device_name, dev->backend_port_num,
630 &dev->dev_attr, &dev->mad_chr);
631 if (rc) {
632 goto out;
633 }
634
635 init_dev_caps(dev);
636
637 rc = rdma_rm_init(&dev->rdma_dev_res, &dev->dev_attr);
638 if (rc) {
639 goto out;
640 }
641
642 rc = pvrdma_qp_ops_init();
643 if (rc) {
644 goto out;
645 }
646
647 memset(&dev->stats, 0, sizeof(dev->stats));
648
649 dev->shutdown_notifier.notify = pvrdma_shutdown_notifier;
650 qemu_register_shutdown_notifier(&dev->shutdown_notifier);
651
652out:
653 if (rc) {
654 pvrdma_fini(pdev);
655 error_append_hint(errp, "Device failed to load\n");
656 }
657}
658
659static void pvrdma_class_init(ObjectClass *klass, void *data)
660{
661 DeviceClass *dc = DEVICE_CLASS(klass);
662 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
663 RdmaProviderClass *ir = INTERFACE_RDMA_PROVIDER_CLASS(klass);
664
665 k->realize = pvrdma_realize;
666 k->vendor_id = PCI_VENDOR_ID_VMWARE;
667 k->device_id = PCI_DEVICE_ID_VMWARE_PVRDMA;
668 k->revision = 0x00;
669 k->class_id = PCI_CLASS_NETWORK_OTHER;
670
671 dc->desc = "RDMA Device";
672 dc->props = pvrdma_dev_properties;
673 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
674
675 ir->print_statistics = pvrdma_print_statistics;
676}
677
678static const TypeInfo pvrdma_info = {
679 .name = PVRDMA_HW_NAME,
680 .parent = TYPE_PCI_DEVICE,
681 .instance_size = sizeof(PVRDMADev),
682 .class_init = pvrdma_class_init,
683 .interfaces = (InterfaceInfo[]) {
684 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
685 { INTERFACE_RDMA_PROVIDER },
686 { }
687 }
688};
689
690static void register_types(void)
691{
692 type_register_static(&pvrdma_info);
693}
694
695type_init(register_types)
696
