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21#include "qemu/osdep.h"
22#include "qemu/units.h"
23#include "qemu/log.h"
24#include "qemu/error-report.h"
25#include "qapi/error.h"
26#include "hw/hw.h"
27#include "hw/boards.h"
28#include "hw/loader.h"
29#include "hw/sysbus.h"
30#include "hw/char/serial.h"
31#include "target/riscv/cpu.h"
32#include "hw/riscv/riscv_htif.h"
33#include "hw/riscv/riscv_hart.h"
34#include "hw/riscv/sifive_plic.h"
35#include "hw/riscv/sifive_clint.h"
36#include "hw/riscv/sifive_test.h"
37#include "hw/riscv/virt.h"
38#include "chardev/char.h"
39#include "sysemu/arch_init.h"
40#include "sysemu/device_tree.h"
41#include "exec/address-spaces.h"
42#include "hw/pci/pci.h"
43#include "hw/pci-host/gpex.h"
44#include "elf.h"
45
46#include <libfdt.h>
47
48static const struct MemmapEntry {
49 hwaddr base;
50 hwaddr size;
51} virt_memmap[] = {
52 [VIRT_DEBUG] = { 0x0, 0x100 },
53 [VIRT_MROM] = { 0x1000, 0x11000 },
54 [VIRT_TEST] = { 0x100000, 0x1000 },
55 [VIRT_CLINT] = { 0x2000000, 0x10000 },
56 [VIRT_PLIC] = { 0xc000000, 0x4000000 },
57 [VIRT_UART0] = { 0x10000000, 0x100 },
58 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
59 [VIRT_DRAM] = { 0x80000000, 0x0 },
60 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
61 [VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 },
62 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
63};
64
65static target_ulong load_kernel(const char *kernel_filename)
66{
67 uint64_t kernel_entry, kernel_high;
68
69 if (load_elf(kernel_filename, NULL, NULL, NULL,
70 &kernel_entry, NULL, &kernel_high,
71 0, EM_RISCV, 1, 0) < 0) {
72 error_report("could not load kernel '%s'", kernel_filename);
73 exit(1);
74 }
75 return kernel_entry;
76}
77
78static hwaddr load_initrd(const char *filename, uint64_t mem_size,
79 uint64_t kernel_entry, hwaddr *start)
80{
81 int size;
82
83
84
85
86
87
88
89
90
91
92
93 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
94
95 size = load_ramdisk(filename, *start, mem_size - *start);
96 if (size == -1) {
97 size = load_image_targphys(filename, *start, mem_size - *start);
98 if (size == -1) {
99 error_report("could not load ramdisk '%s'", filename);
100 exit(1);
101 }
102 }
103 return *start + size;
104}
105
106static void create_pcie_irq_map(void *fdt, char *nodename,
107 uint32_t plic_phandle)
108{
109 int pin, dev;
110 uint32_t
111 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
112 uint32_t *irq_map = full_irq_map;
113
114
115
116
117
118
119
120
121
122 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
123 int devfn = dev * 0x8;
124
125 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
126 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
127 int i = 0;
128
129 irq_map[i] = cpu_to_be32(devfn << 8);
130
131 i += FDT_PCI_ADDR_CELLS;
132 irq_map[i] = cpu_to_be32(pin + 1);
133
134 i += FDT_PCI_INT_CELLS;
135 irq_map[i++] = cpu_to_be32(plic_phandle);
136
137 i += FDT_PLIC_ADDR_CELLS;
138 irq_map[i] = cpu_to_be32(irq_nr);
139
140 irq_map += FDT_INT_MAP_WIDTH;
141 }
142 }
143
144 qemu_fdt_setprop(fdt, nodename, "interrupt-map",
145 full_irq_map, sizeof(full_irq_map));
146
147 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
148 0x1800, 0, 0, 0x7);
149}
150
151static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
152 uint64_t mem_size, const char *cmdline)
153{
154 void *fdt;
155 int cpu;
156 uint32_t *cells;
157 char *nodename;
158 uint32_t plic_phandle, phandle = 1;
159 int i;
160
161 fdt = s->fdt = create_device_tree(&s->fdt_size);
162 if (!fdt) {
163 error_report("create_device_tree() failed");
164 exit(1);
165 }
166
167 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
168 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
169 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
170 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
171
172 qemu_fdt_add_subnode(fdt, "/soc");
173 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
174 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
175 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
176 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
177
178 nodename = g_strdup_printf("/memory@%lx",
179 (long)memmap[VIRT_DRAM].base);
180 qemu_fdt_add_subnode(fdt, nodename);
181 qemu_fdt_setprop_cells(fdt, nodename, "reg",
182 memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
183 mem_size >> 32, mem_size);
184 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
185 g_free(nodename);
186
187 qemu_fdt_add_subnode(fdt, "/cpus");
188 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
189 SIFIVE_CLINT_TIMEBASE_FREQ);
190 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
191 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
192
193 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
194 int cpu_phandle = phandle++;
195 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
196 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
197 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
198 qemu_fdt_add_subnode(fdt, nodename);
199 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
200 VIRT_CLOCK_FREQ);
201 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
202 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
203 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
204 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
205 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
206 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
207 qemu_fdt_add_subnode(fdt, intc);
208 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
209 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
210 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
211 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
212 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
213 g_free(isa);
214 g_free(intc);
215 g_free(nodename);
216 }
217
218 cells = g_new0(uint32_t, s->soc.num_harts * 4);
219 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
220 nodename =
221 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
222 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
223 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
224 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
225 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
226 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
227 g_free(nodename);
228 }
229 nodename = g_strdup_printf("/soc/clint@%lx",
230 (long)memmap[VIRT_CLINT].base);
231 qemu_fdt_add_subnode(fdt, nodename);
232 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
233 qemu_fdt_setprop_cells(fdt, nodename, "reg",
234 0x0, memmap[VIRT_CLINT].base,
235 0x0, memmap[VIRT_CLINT].size);
236 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
237 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
238 g_free(cells);
239 g_free(nodename);
240
241 plic_phandle = phandle++;
242 cells = g_new0(uint32_t, s->soc.num_harts * 4);
243 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
244 nodename =
245 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
246 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
247 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
248 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
249 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
250 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
251 g_free(nodename);
252 }
253 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
254 (long)memmap[VIRT_PLIC].base);
255 qemu_fdt_add_subnode(fdt, nodename);
256 qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
257 FDT_PLIC_ADDR_CELLS);
258 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
259 FDT_PLIC_INT_CELLS);
260 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
261 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
262 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
263 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
264 qemu_fdt_setprop_cells(fdt, nodename, "reg",
265 0x0, memmap[VIRT_PLIC].base,
266 0x0, memmap[VIRT_PLIC].size);
267 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
268 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
269 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
270 qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
271 qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
272 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
273 g_free(cells);
274 g_free(nodename);
275
276 for (i = 0; i < VIRTIO_COUNT; i++) {
277 nodename = g_strdup_printf("/virtio_mmio@%lx",
278 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
279 qemu_fdt_add_subnode(fdt, nodename);
280 qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
281 qemu_fdt_setprop_cells(fdt, nodename, "reg",
282 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
283 0x0, memmap[VIRT_VIRTIO].size);
284 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
285 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
286 g_free(nodename);
287 }
288
289 nodename = g_strdup_printf("/soc/pci@%lx",
290 (long) memmap[VIRT_PCIE_ECAM].base);
291 qemu_fdt_add_subnode(fdt, nodename);
292 qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
293 FDT_PCI_ADDR_CELLS);
294 qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells",
295 FDT_PCI_INT_CELLS);
296 qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
297 qemu_fdt_setprop_string(fdt, nodename, "compatible",
298 "pci-host-ecam-generic");
299 qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
300 qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
301 qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
302 memmap[VIRT_PCIE_ECAM].base /
303 PCIE_MMCFG_SIZE_MIN - 1);
304 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
305 qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
306 0, memmap[VIRT_PCIE_ECAM].size);
307 qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
308 1, FDT_PCI_RANGE_IOPORT, 2, 0,
309 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
310 1, FDT_PCI_RANGE_MMIO,
311 2, memmap[VIRT_PCIE_MMIO].base,
312 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
313 create_pcie_irq_map(fdt, nodename, plic_phandle);
314 g_free(nodename);
315
316 nodename = g_strdup_printf("/test@%lx",
317 (long)memmap[VIRT_TEST].base);
318 qemu_fdt_add_subnode(fdt, nodename);
319 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
320 qemu_fdt_setprop_cells(fdt, nodename, "reg",
321 0x0, memmap[VIRT_TEST].base,
322 0x0, memmap[VIRT_TEST].size);
323 g_free(nodename);
324
325 nodename = g_strdup_printf("/uart@%lx",
326 (long)memmap[VIRT_UART0].base);
327 qemu_fdt_add_subnode(fdt, nodename);
328 qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
329 qemu_fdt_setprop_cells(fdt, nodename, "reg",
330 0x0, memmap[VIRT_UART0].base,
331 0x0, memmap[VIRT_UART0].size);
332 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
333 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
334 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);
335
336 qemu_fdt_add_subnode(fdt, "/chosen");
337 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
338 if (cmdline) {
339 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
340 }
341 g_free(nodename);
342
343 return fdt;
344}
345
346
347static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
348 hwaddr ecam_base, hwaddr ecam_size,
349 hwaddr mmio_base, hwaddr mmio_size,
350 hwaddr pio_base,
351 DeviceState *plic, bool link_up)
352{
353 DeviceState *dev;
354 MemoryRegion *ecam_alias, *ecam_reg;
355 MemoryRegion *mmio_alias, *mmio_reg;
356 qemu_irq irq;
357 int i;
358
359 dev = qdev_create(NULL, TYPE_GPEX_HOST);
360
361 qdev_init_nofail(dev);
362
363 ecam_alias = g_new0(MemoryRegion, 1);
364 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
365 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
366 ecam_reg, 0, ecam_size);
367 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
368
369 mmio_alias = g_new0(MemoryRegion, 1);
370 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
371 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
372 mmio_reg, mmio_base, mmio_size);
373 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
374
375 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
376
377 for (i = 0; i < GPEX_NUM_IRQS; i++) {
378 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
379
380 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
381 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
382 }
383
384 return dev;
385}
386
387static void riscv_virt_board_init(MachineState *machine)
388{
389 const struct MemmapEntry *memmap = virt_memmap;
390
391 RISCVVirtState *s = g_new0(RISCVVirtState, 1);
392 MemoryRegion *system_memory = get_system_memory();
393 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
394 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
395 char *plic_hart_config;
396 size_t plic_hart_config_len;
397 int i;
398 void *fdt;
399
400
401 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
402 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
403 object_property_set_str(OBJECT(&s->soc), VIRT_CPU, "cpu-type",
404 &error_abort);
405 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
406 &error_abort);
407 object_property_set_bool(OBJECT(&s->soc), true, "realized",
408 &error_abort);
409
410
411 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
412 machine->ram_size, &error_fatal);
413 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
414 main_mem);
415
416
417 fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
418
419
420 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
421 memmap[VIRT_MROM].size, &error_fatal);
422 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
423 mask_rom);
424
425 if (machine->kernel_filename) {
426 uint64_t kernel_entry = load_kernel(machine->kernel_filename);
427
428 if (machine->initrd_filename) {
429 hwaddr start;
430 hwaddr end = load_initrd(machine->initrd_filename,
431 machine->ram_size, kernel_entry,
432 &start);
433 qemu_fdt_setprop_cell(fdt, "/chosen",
434 "linux,initrd-start", start);
435 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
436 end);
437 }
438 }
439
440
441 uint32_t reset_vec[8] = {
442 0x00000297,
443 0x02028593,
444 0xf1402573,
445#if defined(TARGET_RISCV32)
446 0x0182a283,
447#elif defined(TARGET_RISCV64)
448 0x0182b283,
449#endif
450 0x00028067,
451 0x00000000,
452 memmap[VIRT_DRAM].base,
453 0x00000000,
454
455 };
456
457
458 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
459 reset_vec[i] = cpu_to_le32(reset_vec[i]);
460 }
461 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
462 memmap[VIRT_MROM].base, &address_space_memory);
463
464
465 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
466 memmap[VIRT_MROM].size - sizeof(reset_vec)) {
467 error_report("not enough space to store device-tree");
468 exit(1);
469 }
470 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
471 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
472 memmap[VIRT_MROM].base + sizeof(reset_vec),
473 &address_space_memory);
474
475
476 plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
477 plic_hart_config = g_malloc0(plic_hart_config_len);
478 for (i = 0; i < smp_cpus; i++) {
479 if (i != 0) {
480 strncat(plic_hart_config, ",", plic_hart_config_len);
481 }
482 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
483 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
484 }
485
486
487 s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
488 plic_hart_config,
489 VIRT_PLIC_NUM_SOURCES,
490 VIRT_PLIC_NUM_PRIORITIES,
491 VIRT_PLIC_PRIORITY_BASE,
492 VIRT_PLIC_PENDING_BASE,
493 VIRT_PLIC_ENABLE_BASE,
494 VIRT_PLIC_ENABLE_STRIDE,
495 VIRT_PLIC_CONTEXT_BASE,
496 VIRT_PLIC_CONTEXT_STRIDE,
497 memmap[VIRT_PLIC].size);
498 sifive_clint_create(memmap[VIRT_CLINT].base,
499 memmap[VIRT_CLINT].size, smp_cpus,
500 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
501 sifive_test_create(memmap[VIRT_TEST].base);
502
503 for (i = 0; i < VIRTIO_COUNT; i++) {
504 sysbus_create_simple("virtio-mmio",
505 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
506 qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
507 }
508
509 gpex_pcie_init(system_memory,
510 memmap[VIRT_PCIE_ECAM].base,
511 memmap[VIRT_PCIE_ECAM].size,
512 memmap[VIRT_PCIE_MMIO].base,
513 memmap[VIRT_PCIE_MMIO].size,
514 memmap[VIRT_PCIE_PIO].base,
515 DEVICE(s->plic), true);
516
517 serial_mm_init(system_memory, memmap[VIRT_UART0].base,
518 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
519 serial_hd(0), DEVICE_LITTLE_ENDIAN);
520
521 g_free(plic_hart_config);
522}
523
524static void riscv_virt_board_machine_init(MachineClass *mc)
525{
526 mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
527 mc->init = riscv_virt_board_init;
528 mc->max_cpus = 8;
529}
530
531DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
532
