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24#include "qemu/osdep.h"
25#include "qemu/units.h"
26#include "qemu/error-report.h"
27#include "qapi/error.h"
28#include "qemu-common.h"
29#include "cpu.h"
30#include "hw/hw.h"
31#include "hw/pci/pci.h"
32#include "hw/pci/pci_bridge.h"
33#include "hw/pci/pci_bus.h"
34#include "hw/pci/pci_host.h"
35#include "hw/pci-host/sabre.h"
36#include "hw/char/serial.h"
37#include "hw/char/parallel.h"
38#include "hw/timer/m48t59.h"
39#include "hw/input/i8042.h"
40#include "hw/block/fdc.h"
41#include "net/net.h"
42#include "qemu/timer.h"
43#include "sysemu/sysemu.h"
44#include "hw/boards.h"
45#include "hw/nvram/sun_nvram.h"
46#include "hw/nvram/chrp_nvram.h"
47#include "hw/sparc/sparc64.h"
48#include "hw/nvram/fw_cfg.h"
49#include "hw/sysbus.h"
50#include "hw/ide.h"
51#include "hw/ide/pci.h"
52#include "hw/loader.h"
53#include "hw/fw-path-provider.h"
54#include "elf.h"
55#include "trace.h"
56
57#define KERNEL_LOAD_ADDR 0x00404000
58#define CMDLINE_ADDR 0x003ff000
59#define PROM_SIZE_MAX (4 * MiB)
60#define PROM_VADDR 0x000ffd00000ULL
61#define PBM_SPECIAL_BASE 0x1fe00000000ULL
62#define PBM_MEM_BASE 0x1ff00000000ULL
63#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
64#define PROM_FILENAME "openbios-sparc64"
65#define NVRAM_SIZE 0x2000
66#define MAX_IDE_BUS 2
67#define BIOS_CFG_IOPORT 0x510
68#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
69#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
70#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
71
72#define IVEC_MAX 0x40
73
74struct hwdef {
75 uint16_t machine_id;
76 uint64_t prom_addr;
77 uint64_t console_serial_base;
78};
79
80typedef struct EbusState {
81
82 PCIDevice parent_obj;
83
84 ISABus *isa_bus;
85 qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
86 uint64_t console_serial_base;
87 MemoryRegion bar0;
88 MemoryRegion bar1;
89} EbusState;
90
91#define TYPE_EBUS "ebus"
92#define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
93
94static void fw_cfg_boot_set(void *opaque, const char *boot_device,
95 Error **errp)
96{
97 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
98}
99
100static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
101 const char *arch, ram_addr_t RAM_size,
102 const char *boot_devices,
103 uint32_t kernel_image, uint32_t kernel_size,
104 const char *cmdline,
105 uint32_t initrd_image, uint32_t initrd_size,
106 uint32_t NVRAM_image,
107 int width, int height, int depth,
108 const uint8_t *macaddr)
109{
110 unsigned int i;
111 int sysp_end;
112 uint8_t image[0x1ff0];
113 NvramClass *k = NVRAM_GET_CLASS(nvram);
114
115 memset(image, '\0', sizeof(image));
116
117
118 sysp_end = chrp_nvram_create_system_partition(image, 0);
119
120
121 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
122
123 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
124
125 for (i = 0; i < sizeof(image); i++) {
126 (k->write)(nvram, i, image[i]);
127 }
128
129 return 0;
130}
131
132static uint64_t sun4u_load_kernel(const char *kernel_filename,
133 const char *initrd_filename,
134 ram_addr_t RAM_size, uint64_t *initrd_size,
135 uint64_t *initrd_addr, uint64_t *kernel_addr,
136 uint64_t *kernel_entry)
137{
138 int linux_boot;
139 unsigned int i;
140 long kernel_size;
141 uint8_t *ptr;
142 uint64_t kernel_top = 0;
143
144 linux_boot = (kernel_filename != NULL);
145
146 kernel_size = 0;
147 if (linux_boot) {
148 int bswap_needed;
149
150#ifdef BSWAP_NEEDED
151 bswap_needed = 1;
152#else
153 bswap_needed = 0;
154#endif
155 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
156 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
157 if (kernel_size < 0) {
158 *kernel_addr = KERNEL_LOAD_ADDR;
159 *kernel_entry = KERNEL_LOAD_ADDR;
160 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
161 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
162 TARGET_PAGE_SIZE);
163 }
164 if (kernel_size < 0) {
165 kernel_size = load_image_targphys(kernel_filename,
166 KERNEL_LOAD_ADDR,
167 RAM_size - KERNEL_LOAD_ADDR);
168 }
169 if (kernel_size < 0) {
170 error_report("could not load kernel '%s'", kernel_filename);
171 exit(1);
172 }
173
174 *initrd_size = 0;
175 if (initrd_filename && kernel_top) {
176 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
177
178 *initrd_size = load_image_targphys(initrd_filename,
179 *initrd_addr,
180 RAM_size - *initrd_addr);
181 if ((int)*initrd_size < 0) {
182 error_report("could not load initial ram disk '%s'",
183 initrd_filename);
184 exit(1);
185 }
186 }
187 if (*initrd_size > 0) {
188 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
189 ptr = rom_ptr(*kernel_addr + i, 32);
190 if (ptr && ldl_p(ptr + 8) == 0x48647253) {
191 stl_p(ptr + 24, *initrd_addr + *kernel_addr);
192 stl_p(ptr + 28, *initrd_size);
193 break;
194 }
195 }
196 }
197 }
198 return kernel_size;
199}
200
201typedef struct ResetData {
202 SPARCCPU *cpu;
203 uint64_t prom_addr;
204} ResetData;
205
206#define TYPE_SUN4U_POWER "power"
207#define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
208
209typedef struct PowerDevice {
210 SysBusDevice parent_obj;
211
212 MemoryRegion power_mmio;
213} PowerDevice;
214
215
216static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
217{
218 return 0;
219}
220
221static void power_mem_write(void *opaque, hwaddr addr,
222 uint64_t val, unsigned size)
223{
224
225 if (val & 0x1000000) {
226 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
227 }
228}
229
230static const MemoryRegionOps power_mem_ops = {
231 .read = power_mem_read,
232 .write = power_mem_write,
233 .endianness = DEVICE_NATIVE_ENDIAN,
234 .valid = {
235 .min_access_size = 4,
236 .max_access_size = 4,
237 },
238};
239
240static void power_realize(DeviceState *dev, Error **errp)
241{
242 PowerDevice *d = SUN4U_POWER(dev);
243 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
244
245 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
246 "power", sizeof(uint32_t));
247
248 sysbus_init_mmio(sbd, &d->power_mmio);
249}
250
251static void power_class_init(ObjectClass *klass, void *data)
252{
253 DeviceClass *dc = DEVICE_CLASS(klass);
254
255 dc->realize = power_realize;
256}
257
258static const TypeInfo power_info = {
259 .name = TYPE_SUN4U_POWER,
260 .parent = TYPE_SYS_BUS_DEVICE,
261 .instance_size = sizeof(PowerDevice),
262 .class_init = power_class_init,
263};
264
265static void ebus_isa_irq_handler(void *opaque, int n, int level)
266{
267 EbusState *s = EBUS(opaque);
268 qemu_irq irq = s->isa_bus_irqs[n];
269
270
271 trace_ebus_isa_irq_handler(n, level);
272 if (irq) {
273 qemu_set_irq(irq, level);
274 }
275}
276
277
278static void ebus_realize(PCIDevice *pci_dev, Error **errp)
279{
280 EbusState *s = EBUS(pci_dev);
281 SysBusDevice *sbd;
282 DeviceState *dev;
283 qemu_irq *isa_irq;
284 DriveInfo *fd[MAX_FD];
285 int i;
286
287 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
288 pci_address_space_io(pci_dev), errp);
289 if (!s->isa_bus) {
290 error_setg(errp, "unable to instantiate EBUS ISA bus");
291 return;
292 }
293
294
295 isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
296 isa_bus_irqs(s->isa_bus, isa_irq);
297 qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
298 ISA_NUM_IRQS);
299
300
301 i = 0;
302 if (s->console_serial_base) {
303 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
304 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
305 i++;
306 }
307 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
308
309
310 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
311
312
313 isa_create_simple(s->isa_bus, "i8042");
314
315
316 for (i = 0; i < MAX_FD; i++) {
317 fd[i] = drive_get(IF_FLOPPY, 0, i);
318 }
319 dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
320 if (fd[0]) {
321 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
322 &error_abort);
323 }
324 if (fd[1]) {
325 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
326 &error_abort);
327 }
328 qdev_prop_set_uint32(dev, "dma", -1);
329 qdev_init_nofail(dev);
330
331
332 dev = qdev_create(NULL, TYPE_SUN4U_POWER);
333 qdev_init_nofail(dev);
334 sbd = SYS_BUS_DEVICE(dev);
335 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
336 sysbus_mmio_get_region(sbd, 0));
337
338
339 pci_dev->config[0x04] = 0x06;
340 pci_dev->config[0x05] = 0x00;
341 pci_dev->config[0x06] = 0xa0;
342 pci_dev->config[0x07] = 0x03;
343 pci_dev->config[0x09] = 0x00;
344 pci_dev->config[0x0D] = 0x0a;
345
346 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
347 0, 0x1000000);
348 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
349 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
350 0, 0x8000);
351 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
352}
353
354static Property ebus_properties[] = {
355 DEFINE_PROP_UINT64("console-serial-base", EbusState,
356 console_serial_base, 0),
357 DEFINE_PROP_END_OF_LIST(),
358};
359
360static void ebus_class_init(ObjectClass *klass, void *data)
361{
362 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
363 DeviceClass *dc = DEVICE_CLASS(klass);
364
365 k->realize = ebus_realize;
366 k->vendor_id = PCI_VENDOR_ID_SUN;
367 k->device_id = PCI_DEVICE_ID_SUN_EBUS;
368 k->revision = 0x01;
369 k->class_id = PCI_CLASS_BRIDGE_OTHER;
370 dc->props = ebus_properties;
371}
372
373static const TypeInfo ebus_info = {
374 .name = TYPE_EBUS,
375 .parent = TYPE_PCI_DEVICE,
376 .class_init = ebus_class_init,
377 .instance_size = sizeof(EbusState),
378 .interfaces = (InterfaceInfo[]) {
379 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
380 { },
381 },
382};
383
384#define TYPE_OPENPROM "openprom"
385#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
386
387typedef struct PROMState {
388 SysBusDevice parent_obj;
389
390 MemoryRegion prom;
391} PROMState;
392
393static uint64_t translate_prom_address(void *opaque, uint64_t addr)
394{
395 hwaddr *base_addr = (hwaddr *)opaque;
396 return addr + *base_addr - PROM_VADDR;
397}
398
399
400static void prom_init(hwaddr addr, const char *bios_name)
401{
402 DeviceState *dev;
403 SysBusDevice *s;
404 char *filename;
405 int ret;
406
407 dev = qdev_create(NULL, TYPE_OPENPROM);
408 qdev_init_nofail(dev);
409 s = SYS_BUS_DEVICE(dev);
410
411 sysbus_mmio_map(s, 0, addr);
412
413
414 if (bios_name == NULL) {
415 bios_name = PROM_FILENAME;
416 }
417 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
418 if (filename) {
419 ret = load_elf(filename, NULL, translate_prom_address, &addr,
420 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
421 if (ret < 0 || ret > PROM_SIZE_MAX) {
422 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
423 }
424 g_free(filename);
425 } else {
426 ret = -1;
427 }
428 if (ret < 0 || ret > PROM_SIZE_MAX) {
429 error_report("could not load prom '%s'", bios_name);
430 exit(1);
431 }
432}
433
434static void prom_realize(DeviceState *ds, Error **errp)
435{
436 PROMState *s = OPENPROM(ds);
437 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
438 Error *local_err = NULL;
439
440 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
441 PROM_SIZE_MAX, &local_err);
442 if (local_err) {
443 error_propagate(errp, local_err);
444 return;
445 }
446
447 vmstate_register_ram_global(&s->prom);
448 memory_region_set_readonly(&s->prom, true);
449 sysbus_init_mmio(dev, &s->prom);
450}
451
452static Property prom_properties[] = {
453 {},
454};
455
456static void prom_class_init(ObjectClass *klass, void *data)
457{
458 DeviceClass *dc = DEVICE_CLASS(klass);
459
460 dc->props = prom_properties;
461 dc->realize = prom_realize;
462}
463
464static const TypeInfo prom_info = {
465 .name = TYPE_OPENPROM,
466 .parent = TYPE_SYS_BUS_DEVICE,
467 .instance_size = sizeof(PROMState),
468 .class_init = prom_class_init,
469};
470
471
472#define TYPE_SUN4U_MEMORY "memory"
473#define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
474
475typedef struct RamDevice {
476 SysBusDevice parent_obj;
477
478 MemoryRegion ram;
479 uint64_t size;
480} RamDevice;
481
482
483static void ram_realize(DeviceState *dev, Error **errp)
484{
485 RamDevice *d = SUN4U_RAM(dev);
486 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
487
488 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
489 &error_fatal);
490 vmstate_register_ram_global(&d->ram);
491 sysbus_init_mmio(sbd, &d->ram);
492}
493
494static void ram_init(hwaddr addr, ram_addr_t RAM_size)
495{
496 DeviceState *dev;
497 SysBusDevice *s;
498 RamDevice *d;
499
500
501 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
502 s = SYS_BUS_DEVICE(dev);
503
504 d = SUN4U_RAM(dev);
505 d->size = RAM_size;
506 qdev_init_nofail(dev);
507
508 sysbus_mmio_map(s, 0, addr);
509}
510
511static Property ram_properties[] = {
512 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
513 DEFINE_PROP_END_OF_LIST(),
514};
515
516static void ram_class_init(ObjectClass *klass, void *data)
517{
518 DeviceClass *dc = DEVICE_CLASS(klass);
519
520 dc->realize = ram_realize;
521 dc->props = ram_properties;
522}
523
524static const TypeInfo ram_info = {
525 .name = TYPE_SUN4U_MEMORY,
526 .parent = TYPE_SYS_BUS_DEVICE,
527 .instance_size = sizeof(RamDevice),
528 .class_init = ram_class_init,
529};
530
531static void sun4uv_init(MemoryRegion *address_space_mem,
532 MachineState *machine,
533 const struct hwdef *hwdef)
534{
535 SPARCCPU *cpu;
536 Nvram *nvram;
537 unsigned int i;
538 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
539 SabreState *sabre;
540 PCIBus *pci_bus, *pci_busA, *pci_busB;
541 PCIDevice *ebus, *pci_dev;
542 SysBusDevice *s;
543 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
544 DeviceState *iommu, *dev;
545 FWCfgState *fw_cfg;
546 NICInfo *nd;
547 MACAddr macaddr;
548 bool onboard_nic;
549
550
551 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
552
553
554 iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
555 qdev_init_nofail(iommu);
556
557
558 ram_init(0, machine->ram_size);
559
560 prom_init(hwdef->prom_addr, bios_name);
561
562
563 sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
564 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
565 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
566 object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
567 &error_abort);
568 qdev_init_nofail(DEVICE(sabre));
569
570
571 for (i = 0; i < IVEC_MAX; i++) {
572 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
573 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
574 }
575
576 pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
577 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
578 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
579
580
581
582
583 pci_bus->slot_reserved_mask = 0xfffffffc;
584 pci_busA->slot_reserved_mask = 0xfffffff1;
585 pci_busB->slot_reserved_mask = 0xfffffff0;
586
587 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
588 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
589 hwdef->console_serial_base);
590 qdev_init_nofail(DEVICE(ebus));
591
592
593 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
594 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
595 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
596 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
597 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
598 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
599 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
600 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
601 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
602 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
603
604 switch (vga_interface_type) {
605 case VGA_STD:
606 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
607 break;
608 case VGA_NONE:
609 break;
610 default:
611 abort();
612 }
613
614 memset(&macaddr, 0, sizeof(MACAddr));
615 onboard_nic = false;
616 for (i = 0; i < nb_nics; i++) {
617 nd = &nd_table[i];
618
619 if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
620 if (!onboard_nic) {
621 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
622 true, "sunhme");
623 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
624 onboard_nic = true;
625 } else {
626 pci_dev = pci_create(pci_busB, -1, "sunhme");
627 }
628 } else {
629 pci_dev = pci_create(pci_busB, -1, nd->model);
630 }
631
632 dev = &pci_dev->qdev;
633 qdev_set_nic_properties(dev, nd);
634 qdev_init_nofail(dev);
635 }
636
637
638
639 if (!onboard_nic) {
640 qemu_macaddr_default_if_unset(&macaddr);
641 }
642
643 ide_drive_get(hd, ARRAY_SIZE(hd));
644
645 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
646 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
647 qdev_init_nofail(&pci_dev->qdev);
648 pci_ide_create_devs(pci_dev, hd);
649
650
651 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
652 s = SYS_BUS_DEVICE(nvram);
653 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
654 sysbus_mmio_get_region(s, 0));
655
656 initrd_size = 0;
657 initrd_addr = 0;
658 kernel_size = sun4u_load_kernel(machine->kernel_filename,
659 machine->initrd_filename,
660 ram_size, &initrd_size, &initrd_addr,
661 &kernel_addr, &kernel_entry);
662
663 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
664 machine->boot_order,
665 kernel_addr, kernel_size,
666 machine->kernel_cmdline,
667 initrd_addr, initrd_size,
668
669 0,
670 graphic_width, graphic_height, graphic_depth,
671 (uint8_t *)&macaddr);
672
673 dev = qdev_create(NULL, TYPE_FW_CFG_IO);
674 qdev_prop_set_bit(dev, "dma_enabled", false);
675 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
676 qdev_init_nofail(dev);
677 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
678 &FW_CFG_IO(dev)->comb_iomem);
679
680 fw_cfg = FW_CFG(dev);
681 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
682 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
683 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
684 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
685 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
686 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
687 if (machine->kernel_cmdline) {
688 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
689 strlen(machine->kernel_cmdline) + 1);
690 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
691 } else {
692 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
693 }
694 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
695 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
696 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
697
698 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
699 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
700 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
701
702 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
703}
704
705enum {
706 sun4u_id = 0,
707 sun4v_id = 64,
708};
709
710
711
712
713
714static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
715 DeviceState *dev)
716{
717 PCIDevice *pci;
718 IDEBus *ide_bus;
719 IDEState *ide_s;
720 int bus_id;
721
722 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
723 pci = PCI_DEVICE(dev);
724
725 if (PCI_FUNC(pci->devfn)) {
726 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
727 PCI_FUNC(pci->devfn));
728 } else {
729 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
730 }
731 }
732
733 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
734 ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
735 ide_s = idebus_active_if(ide_bus);
736 bus_id = ide_bus->bus_id;
737
738 if (ide_s->drive_kind == IDE_CD) {
739 return g_strdup_printf("ide@%x/cdrom", bus_id);
740 }
741
742 return g_strdup_printf("ide@%x/disk", bus_id);
743 }
744
745 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
746 return g_strdup("disk");
747 }
748
749 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
750 return g_strdup("cdrom");
751 }
752
753 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
754 return g_strdup("disk");
755 }
756
757 return NULL;
758}
759
760static const struct hwdef hwdefs[] = {
761
762 {
763 .machine_id = sun4u_id,
764 .prom_addr = 0x1fff0000000ULL,
765 .console_serial_base = 0,
766 },
767
768 {
769 .machine_id = sun4v_id,
770 .prom_addr = 0x1fff0000000ULL,
771 .console_serial_base = 0,
772 },
773};
774
775
776static void sun4u_init(MachineState *machine)
777{
778 sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
779}
780
781
782static void sun4v_init(MachineState *machine)
783{
784 sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
785}
786
787static void sun4u_class_init(ObjectClass *oc, void *data)
788{
789 MachineClass *mc = MACHINE_CLASS(oc);
790 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
791
792 mc->desc = "Sun4u platform";
793 mc->init = sun4u_init;
794 mc->block_default_type = IF_IDE;
795 mc->max_cpus = 1;
796 mc->is_default = 1;
797 mc->default_boot_order = "c";
798 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
799 mc->ignore_boot_device_suffixes = true;
800 mc->default_display = "std";
801 fwc->get_dev_path = sun4u_fw_dev_path;
802}
803
804static const TypeInfo sun4u_type = {
805 .name = MACHINE_TYPE_NAME("sun4u"),
806 .parent = TYPE_MACHINE,
807 .class_init = sun4u_class_init,
808 .interfaces = (InterfaceInfo[]) {
809 { TYPE_FW_PATH_PROVIDER },
810 { }
811 },
812};
813
814static void sun4v_class_init(ObjectClass *oc, void *data)
815{
816 MachineClass *mc = MACHINE_CLASS(oc);
817
818 mc->desc = "Sun4v platform";
819 mc->init = sun4v_init;
820 mc->block_default_type = IF_IDE;
821 mc->max_cpus = 1;
822 mc->default_boot_order = "c";
823 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
824 mc->default_display = "std";
825}
826
827static const TypeInfo sun4v_type = {
828 .name = MACHINE_TYPE_NAME("sun4v"),
829 .parent = TYPE_MACHINE,
830 .class_init = sun4v_class_init,
831};
832
833static void sun4u_register_types(void)
834{
835 type_register_static(&power_info);
836 type_register_static(&ebus_info);
837 type_register_static(&prom_info);
838 type_register_static(&ram_info);
839
840 type_register_static(&sun4u_type);
841 type_register_static(&sun4v_type);
842}
843
844type_init(sun4u_register_types)
845
