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26#include "qemu/osdep.h"
27#include "hw/ssi/mss-spi.h"
28#include "qemu/log.h"
29
30#ifndef MSS_SPI_ERR_DEBUG
31#define MSS_SPI_ERR_DEBUG 0
32#endif
33
34#define DB_PRINT_L(lvl, fmt, args...) do { \
35 if (MSS_SPI_ERR_DEBUG >= lvl) { \
36 qemu_log("%s: " fmt "\n", __func__, ## args); \
37 } \
38} while (0)
39
40#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
41
42#define FIFO_CAPACITY 32
43
44#define R_SPI_CONTROL 0
45#define R_SPI_DFSIZE 1
46#define R_SPI_STATUS 2
47#define R_SPI_INTCLR 3
48#define R_SPI_RX 4
49#define R_SPI_TX 5
50#define R_SPI_CLKGEN 6
51#define R_SPI_SS 7
52#define R_SPI_MIS 8
53#define R_SPI_RIS 9
54
55#define S_TXDONE (1 << 0)
56#define S_RXRDY (1 << 1)
57#define S_RXCHOVRF (1 << 2)
58#define S_RXFIFOFUL (1 << 4)
59#define S_RXFIFOFULNXT (1 << 5)
60#define S_RXFIFOEMP (1 << 6)
61#define S_RXFIFOEMPNXT (1 << 7)
62#define S_TXFIFOFUL (1 << 8)
63#define S_TXFIFOFULNXT (1 << 9)
64#define S_TXFIFOEMP (1 << 10)
65#define S_TXFIFOEMPNXT (1 << 11)
66#define S_FRAMESTART (1 << 12)
67#define S_SSEL (1 << 13)
68#define S_ACTIVE (1 << 14)
69
70#define C_ENABLE (1 << 0)
71#define C_MODE (1 << 1)
72#define C_INTRXDATA (1 << 4)
73#define C_INTTXDATA (1 << 5)
74#define C_INTRXOVRFLO (1 << 6)
75#define C_SPS (1 << 26)
76#define C_BIGFIFO (1 << 29)
77#define C_RESET (1 << 31)
78
79#define FRAMESZ_MASK 0x3F
80#define FMCOUNT_MASK 0x00FFFF00
81#define FMCOUNT_SHIFT 8
82#define FRAMESZ_MAX 32
83
84static void txfifo_reset(MSSSpiState *s)
85{
86 fifo32_reset(&s->tx_fifo);
87
88 s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
89 s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
90}
91
92static void rxfifo_reset(MSSSpiState *s)
93{
94 fifo32_reset(&s->rx_fifo);
95
96 s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
97 s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
98}
99
100static void set_fifodepth(MSSSpiState *s)
101{
102 unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
103
104 if (size <= 8) {
105 s->fifo_depth = 32;
106 } else if (size <= 16) {
107 s->fifo_depth = 16;
108 } else {
109 s->fifo_depth = 8;
110 }
111}
112
113static void update_mis(MSSSpiState *s)
114{
115 uint32_t reg = s->regs[R_SPI_CONTROL];
116 uint32_t tmp;
117
118
119
120
121
122 tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
123 ((reg & C_INTTXDATA) >> 5);
124 s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
125}
126
127static void spi_update_irq(MSSSpiState *s)
128{
129 int irq;
130
131 update_mis(s);
132 irq = !!(s->regs[R_SPI_MIS]);
133
134 qemu_set_irq(s->irq, irq);
135}
136
137static void mss_spi_reset(DeviceState *d)
138{
139 MSSSpiState *s = MSS_SPI(d);
140
141 memset(s->regs, 0, sizeof s->regs);
142 s->regs[R_SPI_CONTROL] = 0x80000102;
143 s->regs[R_SPI_DFSIZE] = 0x4;
144 s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;
145 s->regs[R_SPI_CLKGEN] = 0x7;
146 s->regs[R_SPI_RIS] = 0x0;
147
148 s->fifo_depth = 4;
149 s->frame_count = 1;
150 s->enabled = false;
151
152 rxfifo_reset(s);
153 txfifo_reset(s);
154}
155
156static uint64_t
157spi_read(void *opaque, hwaddr addr, unsigned int size)
158{
159 MSSSpiState *s = opaque;
160 uint32_t ret = 0;
161
162 addr >>= 2;
163 switch (addr) {
164 case R_SPI_RX:
165 s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
166 s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
167 if (fifo32_is_empty(&s->rx_fifo)) {
168 qemu_log_mask(LOG_GUEST_ERROR,
169 "%s: Reading empty RX_FIFO\n",
170 __func__);
171 } else {
172 ret = fifo32_pop(&s->rx_fifo);
173 }
174 if (fifo32_is_empty(&s->rx_fifo)) {
175 s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
176 }
177 break;
178
179 case R_SPI_MIS:
180 update_mis(s);
181 ret = s->regs[R_SPI_MIS];
182 break;
183
184 default:
185 if (addr < ARRAY_SIZE(s->regs)) {
186 ret = s->regs[addr];
187 } else {
188 qemu_log_mask(LOG_GUEST_ERROR,
189 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
190 addr * 4);
191 return ret;
192 }
193 break;
194 }
195
196 DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);
197 spi_update_irq(s);
198 return ret;
199}
200
201static void assert_cs(MSSSpiState *s)
202{
203 qemu_set_irq(s->cs_line, 0);
204}
205
206static void deassert_cs(MSSSpiState *s)
207{
208 qemu_set_irq(s->cs_line, 1);
209}
210
211static void spi_flush_txfifo(MSSSpiState *s)
212{
213 uint32_t tx;
214 uint32_t rx;
215 bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
216
217
218
219
220
221
222
223
224
225
226
227 while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
228 assert_cs(s);
229
230 s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);
231
232 tx = fifo32_pop(&s->tx_fifo);
233 DB_PRINT("data tx:0x%" PRIx32, tx);
234 rx = ssi_transfer(s->spi, tx);
235 DB_PRINT("data rx:0x%" PRIx32, rx);
236
237 if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
238 s->regs[R_SPI_STATUS] |= S_RXCHOVRF;
239 s->regs[R_SPI_RIS] |= S_RXCHOVRF;
240 } else {
241 fifo32_push(&s->rx_fifo, rx);
242 s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
243 if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
244 s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
245 } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
246 s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
247 }
248 }
249 s->frame_count--;
250 if (!sps) {
251 deassert_cs(s);
252 }
253 }
254
255 if (!s->frame_count) {
256 s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
257 FMCOUNT_SHIFT;
258 deassert_cs(s);
259 s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;
260 s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;
261 }
262}
263
264static void spi_write(void *opaque, hwaddr addr,
265 uint64_t val64, unsigned int size)
266{
267 MSSSpiState *s = opaque;
268 uint32_t value = val64;
269
270 DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);
271 addr >>= 2;
272
273 switch (addr) {
274 case R_SPI_TX:
275
276 if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
277 break;
278 }
279 s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
280 fifo32_push(&s->tx_fifo, value);
281 if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
282 s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
283 } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
284 s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
285 }
286 if (s->enabled) {
287 spi_flush_txfifo(s);
288 }
289 break;
290
291 case R_SPI_CONTROL:
292 s->regs[R_SPI_CONTROL] = value;
293 if (value & C_BIGFIFO) {
294 set_fifodepth(s);
295 } else {
296 s->fifo_depth = 4;
297 }
298 s->enabled = value & C_ENABLE;
299 s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
300 if (value & C_RESET) {
301 mss_spi_reset(DEVICE(s));
302 }
303 break;
304
305 case R_SPI_DFSIZE:
306 if (s->enabled) {
307 break;
308 }
309
310
311
312
313
314 if ((value & FRAMESZ_MASK) > FRAMESZ_MAX) {
315 qemu_log_mask(LOG_GUEST_ERROR, "%s: Incorrect size %u provided."
316 "Maximum frame size is %u\n",
317 __func__, value & FRAMESZ_MASK, FRAMESZ_MAX);
318 break;
319 }
320 s->regs[R_SPI_DFSIZE] = value;
321 break;
322
323 case R_SPI_INTCLR:
324 s->regs[R_SPI_INTCLR] = value;
325 if (value & S_TXDONE) {
326 s->regs[R_SPI_RIS] &= ~S_TXDONE;
327 }
328 if (value & S_RXRDY) {
329 s->regs[R_SPI_RIS] &= ~S_RXRDY;
330 }
331 if (value & S_RXCHOVRF) {
332 s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;
333 }
334 break;
335
336 case R_SPI_MIS:
337 case R_SPI_STATUS:
338 case R_SPI_RIS:
339 qemu_log_mask(LOG_GUEST_ERROR,
340 "%s: Write to read only register 0x%" HWADDR_PRIx "\n",
341 __func__, addr * 4);
342 break;
343
344 default:
345 if (addr < ARRAY_SIZE(s->regs)) {
346 s->regs[addr] = value;
347 } else {
348 qemu_log_mask(LOG_GUEST_ERROR,
349 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
350 addr * 4);
351 }
352 break;
353 }
354
355 spi_update_irq(s);
356}
357
358static const MemoryRegionOps spi_ops = {
359 .read = spi_read,
360 .write = spi_write,
361 .endianness = DEVICE_NATIVE_ENDIAN,
362 .valid = {
363 .min_access_size = 1,
364 .max_access_size = 4
365 }
366};
367
368static void mss_spi_realize(DeviceState *dev, Error **errp)
369{
370 MSSSpiState *s = MSS_SPI(dev);
371 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
372
373 s->spi = ssi_create_bus(dev, "spi");
374
375 sysbus_init_irq(sbd, &s->irq);
376 ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
377 sysbus_init_irq(sbd, &s->cs_line);
378
379 memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
380 TYPE_MSS_SPI, R_SPI_MAX * 4);
381 sysbus_init_mmio(sbd, &s->mmio);
382
383 fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
384 fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
385}
386
387static const VMStateDescription vmstate_mss_spi = {
388 .name = TYPE_MSS_SPI,
389 .version_id = 1,
390 .minimum_version_id = 1,
391 .fields = (VMStateField[]) {
392 VMSTATE_FIFO32(tx_fifo, MSSSpiState),
393 VMSTATE_FIFO32(rx_fifo, MSSSpiState),
394 VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
395 VMSTATE_END_OF_LIST()
396 }
397};
398
399static void mss_spi_class_init(ObjectClass *klass, void *data)
400{
401 DeviceClass *dc = DEVICE_CLASS(klass);
402
403 dc->realize = mss_spi_realize;
404 dc->reset = mss_spi_reset;
405 dc->vmsd = &vmstate_mss_spi;
406}
407
408static const TypeInfo mss_spi_info = {
409 .name = TYPE_MSS_SPI,
410 .parent = TYPE_SYS_BUS_DEVICE,
411 .instance_size = sizeof(MSSSpiState),
412 .class_init = mss_spi_class_init,
413};
414
415static void mss_spi_register_types(void)
416{
417 type_register_static(&mss_spi_info);
418}
419
420type_init(mss_spi_register_types)
421