LXR qemu/hw/xtensa/pic

   1/*
   2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3 * All rights reserved.
   4 *
   5 * Redistribution and use in source and binary forms, with or without
   6 * modification, are permitted provided that the following conditions are met:
   7 *     * Redistributions of source code must retain the above copyright
   8 *       notice, this list of conditions and the following disclaimer.
   9 *     * Redistributions in binary form must reproduce the above copyright
  10 *       notice, this list of conditions and the following disclaimer in the
  11 *       documentation and/or other materials provided with the distribution.
  12 *     * Neither the name of the Open Source and Linux Lab nor the
  13 *       names of its contributors may be used to endorse or promote products
  14 *       derived from this software without specific prior written permission.
  15 *
  16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 */
  27
  28#include "qemu/osdep.h"
  29#include "cpu.h"
  30#include "hw/hw.h"
  31#include "qemu/log.h"
  32#include "qemu/timer.h"
  33
  34void check_interrupts(CPUXtensaState *env)
  35{
  36    CPUState *cs = CPU(xtensa_env_get_cpu(env));
  37    int minlevel = xtensa_get_cintlevel(env);
  38    uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
  39    int level;
  40
  41    for (level = env->config->nlevel; level > minlevel; --level) {
  42        if (env->config->level_mask[level] & int_set_enabled) {
  43            env->pending_irq_level = level;
  44            cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  45            qemu_log_mask(CPU_LOG_INT,
  46                    "%s level = %d, cintlevel = %d, "
  47                    "pc = %08x, a0 = %08x, ps = %08x, "
  48                    "intset = %08x, intenable = %08x, "
  49                    "ccount = %08x\n",
  50                    __func__, level, xtensa_get_cintlevel(env),
  51                    env->pc, env->regs[0], env->sregs[PS],
  52                    env->sregs[INTSET], env->sregs[INTENABLE],
  53                    env->sregs[CCOUNT]);
  54            return;
  55        }
  56    }
  57    env->pending_irq_level = 0;
  58    cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  59}
  60
  61static void xtensa_set_irq(void *opaque, int irq, int active)
  62{
  63    CPUXtensaState *env = opaque;
  64
  65    if (irq >= env->config->ninterrupt) {
  66        qemu_log("%s: bad IRQ %d\n", __func__, irq);
  67    } else {
  68        uint32_t irq_bit = 1 << irq;
  69
  70        if (active) {
  71            atomic_or(&env->sregs[INTSET], irq_bit);
  72        } else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) {
  73            atomic_and(&env->sregs[INTSET], ~irq_bit);
  74        }
  75
  76        check_interrupts(env);
  77    }
  78}
  79
  80static void xtensa_ccompare_cb(void *opaque)
  81{
  82    XtensaCcompareTimer *ccompare = opaque;
  83    CPUXtensaState *env = ccompare->env;
  84    unsigned i = ccompare - env->ccompare;
  85
  86    qemu_set_irq(env->irq_inputs[env->config->timerint[i]], 1);
  87}
  88
  89static void xtensa_set_runstall(void *opaque, int irq, int active)
  90{
  91    CPUXtensaState *env = opaque;
  92    xtensa_runstall(env, active);
  93}
  94
  95void xtensa_irq_init(CPUXtensaState *env)
  96{
  97    unsigned i;
  98
  99    env->irq_inputs = qemu_allocate_irqs(xtensa_set_irq, env,
 100                                         env->config->ninterrupt);
 101    if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
 102        env->time_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 103        env->ccount_base = env->sregs[CCOUNT];
 104        for (i = 0; i < env->config->nccompare; ++i) {
 105            env->ccompare[i].env = env;
 106            env->ccompare[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 107                    xtensa_ccompare_cb, env->ccompare + i);
 108        }
 109    }
 110    for (i = 0; i < env->config->nextint; ++i) {
 111        unsigned irq = env->config->extint[i];
 112
 113        env->ext_irq_inputs[i] = env->irq_inputs[irq];
 114    }
 115    env->runstall_irq = qemu_allocate_irq(xtensa_set_runstall, env, 0);
 116}
 117
 118qemu_irq *xtensa_get_extints(CPUXtensaState *env)
 119{
 120    return env->ext_irq_inputs;
 121}
 122
 123qemu_irq xtensa_get_runstall(CPUXtensaState *env)
 124{
 125    return env->runstall_irq;
 126}
 127