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15#ifndef QEMU_ACPI_DEFS_H
16#define QEMU_ACPI_DEFS_H
17
18enum {
19 ACPI_FADT_F_WBINVD,
20 ACPI_FADT_F_WBINVD_FLUSH,
21 ACPI_FADT_F_PROC_C1,
22 ACPI_FADT_F_P_LVL2_UP,
23 ACPI_FADT_F_PWR_BUTTON,
24 ACPI_FADT_F_SLP_BUTTON,
25 ACPI_FADT_F_FIX_RTC,
26 ACPI_FADT_F_RTC_S4,
27 ACPI_FADT_F_TMR_VAL_EXT,
28 ACPI_FADT_F_DCK_CAP,
29 ACPI_FADT_F_RESET_REG_SUP,
30 ACPI_FADT_F_SEALED_CASE,
31 ACPI_FADT_F_HEADLESS,
32 ACPI_FADT_F_CPU_SW_SLP,
33 ACPI_FADT_F_PCI_EXP_WAK,
34 ACPI_FADT_F_USE_PLATFORM_CLOCK,
35 ACPI_FADT_F_S4_RTC_STS_VALID,
36 ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE,
37 ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL,
38 ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE,
39 ACPI_FADT_F_HW_REDUCED_ACPI,
40 ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE,
41};
42
43typedef struct AcpiRsdpData {
44 uint8_t oem_id[6] QEMU_NONSTRING;
45 uint8_t revision;
46
47 unsigned *rsdt_tbl_offset;
48 unsigned *xsdt_tbl_offset;
49} AcpiRsdpData;
50
51
52
53
54
55#define ACPI_TABLE_HEADER_DEF \
56 uint32_t signature; \
57 uint32_t length; \
58 uint8_t revision; \
59 uint8_t checksum; \
60 uint8_t oem_id[6] \
61 QEMU_NONSTRING; \
62 uint8_t oem_table_id[8] \
63 QEMU_NONSTRING; \
64 uint32_t oem_revision; \
65 uint8_t asl_compiler_id[4] \
66 QEMU_NONSTRING; \
67 uint32_t asl_compiler_revision;
68
69
70
71struct AcpiTableHeader {
72 ACPI_TABLE_HEADER_DEF
73} QEMU_PACKED;
74typedef struct AcpiTableHeader AcpiTableHeader;
75
76struct AcpiGenericAddress {
77 uint8_t space_id;
78 uint8_t bit_width;
79 uint8_t bit_offset;
80 uint8_t access_width;
81
82 uint64_t address;
83} QEMU_PACKED;
84
85typedef struct AcpiFadtData {
86 struct AcpiGenericAddress pm1a_cnt;
87 struct AcpiGenericAddress pm1a_evt;
88 struct AcpiGenericAddress pm_tmr;
89 struct AcpiGenericAddress gpe0_blk;
90 struct AcpiGenericAddress reset_reg;
91 uint8_t reset_val;
92 uint8_t rev;
93 uint32_t flags;
94 uint32_t smi_cmd;
95 uint16_t sci_int;
96 uint8_t int_model;
97 uint8_t acpi_enable_cmd;
98 uint8_t acpi_disable_cmd;
99 uint8_t rtc_century;
100 uint16_t plvl2_lat;
101 uint16_t plvl3_lat;
102 uint16_t arm_boot_arch;
103 uint8_t minor_ver;
104
105
106
107
108
109
110 unsigned *facs_tbl_offset;
111 unsigned *dsdt_tbl_offset;
112 unsigned *xdsdt_tbl_offset;
113} AcpiFadtData;
114
115#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
116#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1)
117
118
119
120
121
122
123
124struct AcpiSerialPortConsoleRedirection {
125 ACPI_TABLE_HEADER_DEF
126 uint8_t interface_type;
127 uint8_t reserved1[3];
128 struct AcpiGenericAddress base_address;
129 uint8_t interrupt_types;
130 uint8_t irq;
131 uint32_t gsi;
132 uint8_t baud;
133 uint8_t parity;
134 uint8_t stopbits;
135 uint8_t flowctrl;
136 uint8_t term_type;
137 uint8_t reserved2;
138 uint16_t pci_device_id;
139 uint16_t pci_vendor_id;
140 uint8_t pci_bus;
141 uint8_t pci_slot;
142 uint8_t pci_func;
143 uint32_t pci_flags;
144 uint8_t pci_seg;
145 uint32_t reserved3;
146} QEMU_PACKED;
147typedef struct AcpiSerialPortConsoleRedirection
148 AcpiSerialPortConsoleRedirection;
149
150
151
152
153struct AcpiRsdtDescriptorRev1 {
154 ACPI_TABLE_HEADER_DEF
155 uint32_t table_offset_entry[0];
156
157} QEMU_PACKED;
158typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1;
159
160
161
162
163struct AcpiXsdtDescriptorRev2 {
164 ACPI_TABLE_HEADER_DEF
165 uint64_t table_offset_entry[0];
166
167} QEMU_PACKED;
168typedef struct AcpiXsdtDescriptorRev2 AcpiXsdtDescriptorRev2;
169
170
171
172
173struct AcpiFacsDescriptorRev1 {
174 uint32_t signature;
175 uint32_t length;
176 uint32_t hardware_signature;
177 uint32_t firmware_waking_vector;
178 uint32_t global_lock;
179 uint32_t flags;
180 uint8_t resverved3 [40];
181} QEMU_PACKED;
182typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1;
183
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192
193
194#define ACPI_DUAL_PIC 0
195#define ACPI_MULTIPLE_APIC 1
196
197
198
199struct AcpiMultipleApicTable {
200 ACPI_TABLE_HEADER_DEF
201 uint32_t local_apic_address;
202 uint32_t flags;
203} QEMU_PACKED;
204typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
205
206
207
208#define ACPI_APIC_PROCESSOR 0
209#define ACPI_APIC_IO 1
210#define ACPI_APIC_XRUPT_OVERRIDE 2
211#define ACPI_APIC_NMI 3
212#define ACPI_APIC_LOCAL_NMI 4
213#define ACPI_APIC_ADDRESS_OVERRIDE 5
214#define ACPI_APIC_IO_SAPIC 6
215#define ACPI_APIC_LOCAL_SAPIC 7
216#define ACPI_APIC_XRUPT_SOURCE 8
217#define ACPI_APIC_LOCAL_X2APIC 9
218#define ACPI_APIC_LOCAL_X2APIC_NMI 10
219#define ACPI_APIC_GENERIC_CPU_INTERFACE 11
220#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
221#define ACPI_APIC_GENERIC_MSI_FRAME 13
222#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
223#define ACPI_APIC_GENERIC_TRANSLATOR 15
224#define ACPI_APIC_RESERVED 16
225
226
227
228
229#define ACPI_SUB_HEADER_DEF \
230 uint8_t type; \
231 uint8_t length;
232
233
234
235struct AcpiMadtProcessorApic {
236 ACPI_SUB_HEADER_DEF
237 uint8_t processor_id;
238 uint8_t local_apic_id;
239 uint32_t flags;
240} QEMU_PACKED;
241typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic;
242
243struct AcpiMadtIoApic {
244 ACPI_SUB_HEADER_DEF
245 uint8_t io_apic_id;
246 uint8_t reserved;
247 uint32_t address;
248 uint32_t interrupt;
249
250} QEMU_PACKED;
251typedef struct AcpiMadtIoApic AcpiMadtIoApic;
252
253struct AcpiMadtIntsrcovr {
254 ACPI_SUB_HEADER_DEF
255 uint8_t bus;
256 uint8_t source;
257 uint32_t gsi;
258 uint16_t flags;
259} QEMU_PACKED;
260typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr;
261
262struct AcpiMadtLocalNmi {
263 ACPI_SUB_HEADER_DEF
264 uint8_t processor_id;
265 uint16_t flags;
266 uint8_t lint;
267} QEMU_PACKED;
268typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
269
270struct AcpiMadtProcessorX2Apic {
271 ACPI_SUB_HEADER_DEF
272 uint16_t reserved;
273 uint32_t x2apic_id;
274 uint32_t flags;
275 uint32_t uid;
276} QEMU_PACKED;
277typedef struct AcpiMadtProcessorX2Apic AcpiMadtProcessorX2Apic;
278
279struct AcpiMadtLocalX2ApicNmi {
280 ACPI_SUB_HEADER_DEF
281 uint16_t flags;
282 uint32_t uid;
283 uint8_t lint;
284 uint8_t reserved[3];
285} QEMU_PACKED;
286typedef struct AcpiMadtLocalX2ApicNmi AcpiMadtLocalX2ApicNmi;
287
288struct AcpiMadtGenericCpuInterface {
289 ACPI_SUB_HEADER_DEF
290 uint16_t reserved;
291 uint32_t cpu_interface_number;
292 uint32_t uid;
293 uint32_t flags;
294 uint32_t parking_version;
295 uint32_t performance_interrupt;
296 uint64_t parked_address;
297 uint64_t base_address;
298 uint64_t gicv_base_address;
299 uint64_t gich_base_address;
300 uint32_t vgic_interrupt;
301 uint64_t gicr_base_address;
302 uint64_t arm_mpidr;
303} QEMU_PACKED;
304
305typedef struct AcpiMadtGenericCpuInterface AcpiMadtGenericCpuInterface;
306
307
308#define ACPI_MADT_GICC_ENABLED 1
309
310struct AcpiMadtGenericDistributor {
311 ACPI_SUB_HEADER_DEF
312 uint16_t reserved;
313 uint32_t gic_id;
314 uint64_t base_address;
315 uint32_t global_irq_base;
316
317 uint8_t version;
318 uint8_t reserved2[3];
319} QEMU_PACKED;
320
321typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
322
323struct AcpiMadtGenericMsiFrame {
324 ACPI_SUB_HEADER_DEF
325 uint16_t reserved;
326 uint32_t gic_msi_frame_id;
327 uint64_t base_address;
328 uint32_t flags;
329 uint16_t spi_count;
330 uint16_t spi_base;
331} QEMU_PACKED;
332
333typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame;
334
335struct AcpiMadtGenericRedistributor {
336 ACPI_SUB_HEADER_DEF
337 uint16_t reserved;
338 uint64_t base_address;
339 uint32_t range_length;
340} QEMU_PACKED;
341
342typedef struct AcpiMadtGenericRedistributor AcpiMadtGenericRedistributor;
343
344struct AcpiMadtGenericTranslator {
345 ACPI_SUB_HEADER_DEF
346 uint16_t reserved;
347 uint32_t translation_id;
348 uint64_t base_address;
349 uint32_t reserved2;
350} QEMU_PACKED;
351
352typedef struct AcpiMadtGenericTranslator AcpiMadtGenericTranslator;
353
354
355
356
357#define ACPI_GTDT_INTERRUPT_MODE_LEVEL (0 << 0)
358#define ACPI_GTDT_INTERRUPT_MODE_EDGE (1 << 0)
359#define ACPI_GTDT_CAP_ALWAYS_ON (1 << 2)
360
361struct AcpiGenericTimerTable {
362 ACPI_TABLE_HEADER_DEF
363 uint64_t counter_block_addresss;
364 uint32_t reserved;
365 uint32_t secure_el1_interrupt;
366 uint32_t secure_el1_flags;
367 uint32_t non_secure_el1_interrupt;
368 uint32_t non_secure_el1_flags;
369 uint32_t virtual_timer_interrupt;
370 uint32_t virtual_timer_flags;
371 uint32_t non_secure_el2_interrupt;
372 uint32_t non_secure_el2_flags;
373 uint64_t counter_read_block_address;
374 uint32_t platform_timer_count;
375 uint32_t platform_timer_offset;
376} QEMU_PACKED;
377typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
378
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380
381
382struct Acpi20Hpet {
383 ACPI_TABLE_HEADER_DEF
384 uint32_t timer_block_id;
385 struct AcpiGenericAddress addr;
386 uint8_t hpet_number;
387 uint16_t min_tick;
388 uint8_t page_protect;
389} QEMU_PACKED;
390typedef struct Acpi20Hpet Acpi20Hpet;
391
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394
395
396struct AcpiSystemResourceAffinityTable {
397 ACPI_TABLE_HEADER_DEF
398 uint32_t reserved1;
399 uint32_t reserved2[2];
400} QEMU_PACKED;
401typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
402
403#define ACPI_SRAT_PROCESSOR_APIC 0
404#define ACPI_SRAT_MEMORY 1
405#define ACPI_SRAT_PROCESSOR_x2APIC 2
406#define ACPI_SRAT_PROCESSOR_GICC 3
407
408struct AcpiSratProcessorAffinity {
409 ACPI_SUB_HEADER_DEF
410 uint8_t proximity_lo;
411 uint8_t local_apic_id;
412 uint32_t flags;
413 uint8_t local_sapic_eid;
414 uint8_t proximity_hi[3];
415 uint32_t reserved;
416} QEMU_PACKED;
417typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity;
418
419struct AcpiSratProcessorX2ApicAffinity {
420 ACPI_SUB_HEADER_DEF
421 uint16_t reserved;
422 uint32_t proximity_domain;
423 uint32_t x2apic_id;
424 uint32_t flags;
425 uint32_t clk_domain;
426 uint32_t reserved2;
427} QEMU_PACKED;
428typedef struct AcpiSratProcessorX2ApicAffinity AcpiSratProcessorX2ApicAffinity;
429
430struct AcpiSratMemoryAffinity {
431 ACPI_SUB_HEADER_DEF
432 uint32_t proximity;
433 uint16_t reserved1;
434 uint64_t base_addr;
435 uint64_t range_length;
436 uint32_t reserved2;
437 uint32_t flags;
438 uint32_t reserved3[2];
439} QEMU_PACKED;
440typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity;
441
442struct AcpiSratProcessorGiccAffinity {
443 ACPI_SUB_HEADER_DEF
444 uint32_t proximity;
445 uint32_t acpi_processor_uid;
446 uint32_t flags;
447 uint32_t clock_domain;
448} QEMU_PACKED;
449
450typedef struct AcpiSratProcessorGiccAffinity AcpiSratProcessorGiccAffinity;
451
452
453
454struct AcpiMcfgAllocation {
455 uint64_t address;
456 uint16_t pci_segment;
457 uint8_t start_bus_number;
458 uint8_t end_bus_number;
459 uint32_t reserved;
460} QEMU_PACKED;
461typedef struct AcpiMcfgAllocation AcpiMcfgAllocation;
462
463struct AcpiTableMcfg {
464 ACPI_TABLE_HEADER_DEF;
465 uint8_t reserved[8];
466 AcpiMcfgAllocation allocation[0];
467} QEMU_PACKED;
468typedef struct AcpiTableMcfg AcpiTableMcfg;
469
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472
473
474
475
476struct Acpi20Tcpa {
477 ACPI_TABLE_HEADER_DEF
478 uint16_t platform_class;
479 uint32_t log_area_minimum_length;
480 uint64_t log_area_start_address;
481} QEMU_PACKED;
482typedef struct Acpi20Tcpa Acpi20Tcpa;
483
484
485
486
487
488
489
490struct Acpi20TPM2 {
491 ACPI_TABLE_HEADER_DEF
492 uint16_t platform_class;
493 uint16_t reserved;
494 uint64_t control_area_address;
495 uint32_t start_method;
496 uint8_t start_method_params[12];
497 uint32_t log_area_minimum_length;
498 uint64_t log_area_start_address;
499} QEMU_PACKED;
500typedef struct Acpi20TPM2 Acpi20TPM2;
501
502
503struct AcpiTableDmar {
504 ACPI_TABLE_HEADER_DEF
505 uint8_t host_address_width;
506 uint8_t flags;
507 uint8_t reserved[10];
508} QEMU_PACKED;
509typedef struct AcpiTableDmar AcpiTableDmar;
510
511
512#define ACPI_DMAR_INTR_REMAP 1
513#define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1)
514
515
516enum {
517 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0,
518 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1,
519 ACPI_DMAR_TYPE_ATSR = 2,
520 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3,
521 ACPI_DMAR_TYPE_ANDD = 4,
522 ACPI_DMAR_TYPE_RESERVED = 5
523};
524
525
526
527
528
529
530struct AcpiDmarDeviceScope {
531 uint8_t entry_type;
532 uint8_t length;
533 uint16_t reserved;
534 uint8_t enumeration_id;
535 uint8_t bus;
536 struct {
537 uint8_t device;
538 uint8_t function;
539 } path[0];
540} QEMU_PACKED;
541typedef struct AcpiDmarDeviceScope AcpiDmarDeviceScope;
542
543
544struct AcpiDmarHardwareUnit {
545 uint16_t type;
546 uint16_t length;
547 uint8_t flags;
548 uint8_t reserved;
549 uint16_t pci_segment;
550 uint64_t address;
551 AcpiDmarDeviceScope scope[0];
552} QEMU_PACKED;
553typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
554
555
556struct AcpiDmarRootPortATS {
557 uint16_t type;
558 uint16_t length;
559 uint8_t flags;
560 uint8_t reserved;
561 uint16_t pci_segment;
562 AcpiDmarDeviceScope scope[0];
563} QEMU_PACKED;
564typedef struct AcpiDmarRootPortATS AcpiDmarRootPortATS;
565
566
567#define ACPI_DMAR_INCLUDE_PCI_ALL 1
568#define ACPI_DMAR_ATSR_ALL_PORTS 1
569
570
571
572
573
574
575
576struct AcpiIortTable {
577 ACPI_TABLE_HEADER_DEF
578 uint32_t node_count;
579 uint32_t node_offset;
580 uint32_t reserved;
581} QEMU_PACKED;
582typedef struct AcpiIortTable AcpiIortTable;
583
584
585
586
587
588#define ACPI_IORT_NODE_HEADER_DEF \
589 uint8_t type; \
590 uint16_t length; \
591 uint8_t revision; \
592 uint32_t reserved; \
593 uint32_t mapping_count; \
594 uint32_t mapping_offset;
595
596
597enum {
598 ACPI_IORT_NODE_ITS_GROUP = 0x00,
599 ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
600 ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
601 ACPI_IORT_NODE_SMMU = 0x03,
602 ACPI_IORT_NODE_SMMU_V3 = 0x04
603};
604
605struct AcpiIortIdMapping {
606 uint32_t input_base;
607 uint32_t id_count;
608 uint32_t output_base;
609 uint32_t output_reference;
610 uint32_t flags;
611} QEMU_PACKED;
612typedef struct AcpiIortIdMapping AcpiIortIdMapping;
613
614struct AcpiIortMemoryAccess {
615 uint32_t cache_coherency;
616 uint8_t hints;
617 uint16_t reserved;
618 uint8_t memory_flags;
619} QEMU_PACKED;
620typedef struct AcpiIortMemoryAccess AcpiIortMemoryAccess;
621
622struct AcpiIortItsGroup {
623 ACPI_IORT_NODE_HEADER_DEF
624 uint32_t its_count;
625 uint32_t identifiers[0];
626} QEMU_PACKED;
627typedef struct AcpiIortItsGroup AcpiIortItsGroup;
628
629#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1
630
631struct AcpiIortSmmu3 {
632 ACPI_IORT_NODE_HEADER_DEF
633 uint64_t base_address;
634 uint32_t flags;
635 uint32_t reserved2;
636 uint64_t vatos_address;
637 uint32_t model;
638 uint32_t event_gsiv;
639 uint32_t pri_gsiv;
640 uint32_t gerr_gsiv;
641 uint32_t sync_gsiv;
642 AcpiIortIdMapping id_mapping_array[0];
643} QEMU_PACKED;
644typedef struct AcpiIortSmmu3 AcpiIortSmmu3;
645
646struct AcpiIortRC {
647 ACPI_IORT_NODE_HEADER_DEF
648 AcpiIortMemoryAccess memory_properties;
649 uint32_t ats_attribute;
650 uint32_t pci_segment_number;
651 AcpiIortIdMapping id_mapping_array[0];
652} QEMU_PACKED;
653typedef struct AcpiIortRC AcpiIortRC;
654
655#endif
656