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19#ifndef hw_omap_h
20#include "exec/memory.h"
21# define hw_omap_h "omap.h"
22#include "hw/irq.h"
23#include "target/arm/cpu-qom.h"
24#include "qemu/log.h"
25
26# define OMAP_EMIFS_BASE 0x00000000
27# define OMAP2_Q0_BASE 0x00000000
28# define OMAP_CS0_BASE 0x00000000
29# define OMAP_CS1_BASE 0x04000000
30# define OMAP_CS2_BASE 0x08000000
31# define OMAP_CS3_BASE 0x0c000000
32# define OMAP_EMIFF_BASE 0x10000000
33# define OMAP_IMIF_BASE 0x20000000
34# define OMAP_LOCALBUS_BASE 0x30000000
35# define OMAP2_Q1_BASE 0x40000000
36# define OMAP2_L4_BASE 0x48000000
37# define OMAP2_SRAM_BASE 0x40200000
38# define OMAP2_L3_BASE 0x68000000
39# define OMAP2_Q2_BASE 0x80000000
40# define OMAP2_Q3_BASE 0xc0000000
41# define OMAP_MPUI_BASE 0xe1000000
42
43# define OMAP730_SRAM_SIZE 0x00032000
44# define OMAP15XX_SRAM_SIZE 0x00030000
45# define OMAP16XX_SRAM_SIZE 0x00004000
46# define OMAP1611_SRAM_SIZE 0x0003e800
47# define OMAP242X_SRAM_SIZE 0x000a0000
48# define OMAP243X_SRAM_SIZE 0x00010000
49# define OMAP_CS0_SIZE 0x04000000
50# define OMAP_CS1_SIZE 0x04000000
51# define OMAP_CS2_SIZE 0x04000000
52# define OMAP_CS3_SIZE 0x04000000
53
54
55struct omap_mpu_state_s;
56typedef struct clk *omap_clk;
57omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
58void omap_clk_init(struct omap_mpu_state_s *mpu);
59void omap_clk_adduser(struct clk *clk, qemu_irq user);
60void omap_clk_get(omap_clk clk);
61void omap_clk_put(omap_clk clk);
62void omap_clk_onoff(omap_clk clk, int on);
63void omap_clk_canidle(omap_clk clk, int can);
64void omap_clk_setrate(omap_clk clk, int divide, int multiply);
65int64_t omap_clk_getrate(omap_clk clk);
66void omap_clk_reparent(omap_clk clk, omap_clk parent);
67
68
69struct omap_l4_s;
70struct omap_l4_region_s {
71 hwaddr offset;
72 size_t size;
73 int access;
74};
75struct omap_l4_agent_info_s {
76 int ta;
77 int region;
78 int regions;
79 int ta_region;
80};
81struct omap_target_agent_s {
82 MemoryRegion iomem;
83 struct omap_l4_s *bus;
84 int regions;
85 const struct omap_l4_region_s *start;
86 hwaddr base;
87 uint32_t component;
88 uint32_t control;
89 uint32_t status;
90};
91struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
92 hwaddr base, int ta_num);
93
94struct omap_target_agent_s;
95struct omap_target_agent_s *omap_l4ta_get(
96 struct omap_l4_s *bus,
97 const struct omap_l4_region_s *regions,
98 const struct omap_l4_agent_info_s *agents,
99 int cs);
100hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
101 int region, MemoryRegion *mr);
102hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
103 int region);
104hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
105 int region);
106
107
108struct omap_sdrc_s;
109struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
110 hwaddr base);
111void omap_sdrc_reset(struct omap_sdrc_s *s);
112
113
114struct omap_gpmc_s;
115struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
116 hwaddr base,
117 qemu_irq irq, qemu_irq drq);
118void omap_gpmc_reset(struct omap_gpmc_s *s);
119void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
120void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
121
122
123
124
125
126# define OMAP_INT_CAMERA 1
127# define OMAP_INT_FIQ 3
128# define OMAP_INT_RTDX 6
129# define OMAP_INT_DSP_MMU_ABORT 7
130# define OMAP_INT_HOST 8
131# define OMAP_INT_ABORT 9
132# define OMAP_INT_BRIDGE_PRIV 13
133# define OMAP_INT_GPIO_BANK1 14
134# define OMAP_INT_UART3 15
135# define OMAP_INT_TIMER3 16
136# define OMAP_INT_DMA_CH0_6 19
137# define OMAP_INT_DMA_CH1_7 20
138# define OMAP_INT_DMA_CH2_8 21
139# define OMAP_INT_DMA_CH3 22
140# define OMAP_INT_DMA_CH4 23
141# define OMAP_INT_DMA_CH5 24
142# define OMAP_INT_DMA_LCD 25
143# define OMAP_INT_TIMER1 26
144# define OMAP_INT_WD_TIMER 27
145# define OMAP_INT_BRIDGE_PUB 28
146# define OMAP_INT_TIMER2 30
147# define OMAP_INT_LCD_CTRL 31
148
149
150
151
152# define OMAP_INT_15XX_IH2_IRQ 0
153# define OMAP_INT_15XX_LB_MMU 17
154# define OMAP_INT_15XX_LOCAL_BUS 29
155
156
157
158
159# define OMAP_INT_1510_SPI_TX 4
160# define OMAP_INT_1510_SPI_RX 5
161# define OMAP_INT_1510_DSP_MAILBOX1 10
162# define OMAP_INT_1510_DSP_MAILBOX2 11
163
164
165
166
167# define OMAP_INT_310_McBSP2_TX 4
168# define OMAP_INT_310_McBSP2_RX 5
169# define OMAP_INT_310_HSB_MAILBOX1 12
170# define OMAP_INT_310_HSAB_MMU 18
171
172
173
174
175# define OMAP_INT_1610_IH2_IRQ 0
176# define OMAP_INT_1610_IH2_FIQ 2
177# define OMAP_INT_1610_McBSP2_TX 4
178# define OMAP_INT_1610_McBSP2_RX 5
179# define OMAP_INT_1610_DSP_MAILBOX1 10
180# define OMAP_INT_1610_DSP_MAILBOX2 11
181# define OMAP_INT_1610_LCD_LINE 12
182# define OMAP_INT_1610_GPTIMER1 17
183# define OMAP_INT_1610_GPTIMER2 18
184# define OMAP_INT_1610_SSR_FIFO_0 29
185
186
187
188
189# define OMAP_INT_730_IH2_FIQ 0
190# define OMAP_INT_730_IH2_IRQ 1
191# define OMAP_INT_730_USB_NON_ISO 2
192# define OMAP_INT_730_USB_ISO 3
193# define OMAP_INT_730_ICR 4
194# define OMAP_INT_730_EAC 5
195# define OMAP_INT_730_GPIO_BANK1 6
196# define OMAP_INT_730_GPIO_BANK2 7
197# define OMAP_INT_730_GPIO_BANK3 8
198# define OMAP_INT_730_McBSP2TX 10
199# define OMAP_INT_730_McBSP2RX 11
200# define OMAP_INT_730_McBSP2RX_OVF 12
201# define OMAP_INT_730_LCD_LINE 14
202# define OMAP_INT_730_GSM_PROTECT 15
203# define OMAP_INT_730_TIMER3 16
204# define OMAP_INT_730_GPIO_BANK5 17
205# define OMAP_INT_730_GPIO_BANK6 18
206# define OMAP_INT_730_SPGIO_WR 29
207
208
209
210
211# define OMAP_INT_KEYBOARD 1
212# define OMAP_INT_uWireTX 2
213# define OMAP_INT_uWireRX 3
214# define OMAP_INT_I2C 4
215# define OMAP_INT_MPUIO 5
216# define OMAP_INT_USB_HHC_1 6
217# define OMAP_INT_McBSP3TX 10
218# define OMAP_INT_McBSP3RX 11
219# define OMAP_INT_McBSP1TX 12
220# define OMAP_INT_McBSP1RX 13
221# define OMAP_INT_UART1 14
222# define OMAP_INT_UART2 15
223# define OMAP_INT_USB_W2FC 20
224# define OMAP_INT_1WIRE 21
225# define OMAP_INT_OS_TIMER 22
226# define OMAP_INT_OQN 23
227# define OMAP_INT_GAUGE_32K 24
228# define OMAP_INT_RTC_TIMER 25
229# define OMAP_INT_RTC_ALARM 26
230# define OMAP_INT_DSP_MMU 28
231
232
233
234
235# define OMAP_INT_1510_BT_MCSI1TX 16
236# define OMAP_INT_1510_BT_MCSI1RX 17
237# define OMAP_INT_1510_SoSSI_MATCH 19
238# define OMAP_INT_1510_MEM_STICK 27
239# define OMAP_INT_1510_COM_SPI_RO 31
240
241
242
243
244# define OMAP_INT_310_FAC 0
245# define OMAP_INT_310_USB_HHC_2 7
246# define OMAP_INT_310_MCSI1_FE 16
247# define OMAP_INT_310_MCSI2_FE 17
248# define OMAP_INT_310_USB_W2FC_ISO 29
249# define OMAP_INT_310_USB_W2FC_NON_ISO 30
250# define OMAP_INT_310_McBSP2RX_OF 31
251
252
253
254
255# define OMAP_INT_1610_FAC 0
256# define OMAP_INT_1610_USB_HHC_2 7
257# define OMAP_INT_1610_USB_OTG 8
258# define OMAP_INT_1610_SoSSI 9
259# define OMAP_INT_1610_BT_MCSI1TX 16
260# define OMAP_INT_1610_BT_MCSI1RX 17
261# define OMAP_INT_1610_SoSSI_MATCH 19
262# define OMAP_INT_1610_MEM_STICK 27
263# define OMAP_INT_1610_McBSP2RX_OF 31
264# define OMAP_INT_1610_STI 32
265# define OMAP_INT_1610_STI_WAKEUP 33
266# define OMAP_INT_1610_GPTIMER3 34
267# define OMAP_INT_1610_GPTIMER4 35
268# define OMAP_INT_1610_GPTIMER5 36
269# define OMAP_INT_1610_GPTIMER6 37
270# define OMAP_INT_1610_GPTIMER7 38
271# define OMAP_INT_1610_GPTIMER8 39
272# define OMAP_INT_1610_GPIO_BANK2 40
273# define OMAP_INT_1610_GPIO_BANK3 41
274# define OMAP_INT_1610_MMC2 42
275# define OMAP_INT_1610_CF 43
276# define OMAP_INT_1610_WAKE_UP_REQ 46
277# define OMAP_INT_1610_GPIO_BANK4 48
278# define OMAP_INT_1610_SPI 49
279# define OMAP_INT_1610_DMA_CH6 53
280# define OMAP_INT_1610_DMA_CH7 54
281# define OMAP_INT_1610_DMA_CH8 55
282# define OMAP_INT_1610_DMA_CH9 56
283# define OMAP_INT_1610_DMA_CH10 57
284# define OMAP_INT_1610_DMA_CH11 58
285# define OMAP_INT_1610_DMA_CH12 59
286# define OMAP_INT_1610_DMA_CH13 60
287# define OMAP_INT_1610_DMA_CH14 61
288# define OMAP_INT_1610_DMA_CH15 62
289# define OMAP_INT_1610_NAND 63
290
291
292
293
294# define OMAP_INT_730_HW_ERRORS 0
295# define OMAP_INT_730_NFIQ_PWR_FAIL 1
296# define OMAP_INT_730_CFCD 2
297# define OMAP_INT_730_CFIREQ 3
298# define OMAP_INT_730_I2C 4
299# define OMAP_INT_730_PCC 5
300# define OMAP_INT_730_MPU_EXT_NIRQ 6
301# define OMAP_INT_730_SPI_100K_1 7
302# define OMAP_INT_730_SYREN_SPI 8
303# define OMAP_INT_730_VLYNQ 9
304# define OMAP_INT_730_GPIO_BANK4 10
305# define OMAP_INT_730_McBSP1TX 11
306# define OMAP_INT_730_McBSP1RX 12
307# define OMAP_INT_730_McBSP1RX_OF 13
308# define OMAP_INT_730_UART_MODEM_IRDA_2 14
309# define OMAP_INT_730_UART_MODEM_1 15
310# define OMAP_INT_730_MCSI 16
311# define OMAP_INT_730_uWireTX 17
312# define OMAP_INT_730_uWireRX 18
313# define OMAP_INT_730_SMC_CD 19
314# define OMAP_INT_730_SMC_IREQ 20
315# define OMAP_INT_730_HDQ_1WIRE 21
316# define OMAP_INT_730_TIMER32K 22
317# define OMAP_INT_730_MMC_SDIO 23
318# define OMAP_INT_730_UPLD 24
319# define OMAP_INT_730_USB_HHC_1 27
320# define OMAP_INT_730_USB_HHC_2 28
321# define OMAP_INT_730_USB_GENI 29
322# define OMAP_INT_730_USB_OTG 30
323# define OMAP_INT_730_CAMERA_IF 31
324# define OMAP_INT_730_RNG 32
325# define OMAP_INT_730_DUAL_MODE_TIMER 33
326# define OMAP_INT_730_DBB_RF_EN 34
327# define OMAP_INT_730_MPUIO_KEYPAD 35
328# define OMAP_INT_730_SHA1_MD5 36
329# define OMAP_INT_730_SPI_100K_2 37
330# define OMAP_INT_730_RNG_IDLE 38
331# define OMAP_INT_730_MPUIO 39
332# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
333# define OMAP_INT_730_LLPC_OE_FALLING 41
334# define OMAP_INT_730_LLPC_OE_RISING 42
335# define OMAP_INT_730_LLPC_VSYNC 43
336# define OMAP_INT_730_WAKE_UP_REQ 46
337# define OMAP_INT_730_DMA_CH6 53
338# define OMAP_INT_730_DMA_CH7 54
339# define OMAP_INT_730_DMA_CH8 55
340# define OMAP_INT_730_DMA_CH9 56
341# define OMAP_INT_730_DMA_CH10 57
342# define OMAP_INT_730_DMA_CH11 58
343# define OMAP_INT_730_DMA_CH12 59
344# define OMAP_INT_730_DMA_CH13 60
345# define OMAP_INT_730_DMA_CH14 61
346# define OMAP_INT_730_DMA_CH15 62
347# define OMAP_INT_730_NAND 63
348
349
350
351
352# define OMAP_INT_24XX_STI 4
353# define OMAP_INT_24XX_SYS_NIRQ 7
354# define OMAP_INT_24XX_L3_IRQ 10
355# define OMAP_INT_24XX_PRCM_MPU_IRQ 11
356# define OMAP_INT_24XX_SDMA_IRQ0 12
357# define OMAP_INT_24XX_SDMA_IRQ1 13
358# define OMAP_INT_24XX_SDMA_IRQ2 14
359# define OMAP_INT_24XX_SDMA_IRQ3 15
360# define OMAP_INT_243X_MCBSP2_IRQ 16
361# define OMAP_INT_243X_MCBSP3_IRQ 17
362# define OMAP_INT_243X_MCBSP4_IRQ 18
363# define OMAP_INT_243X_MCBSP5_IRQ 19
364# define OMAP_INT_24XX_GPMC_IRQ 20
365# define OMAP_INT_24XX_GUFFAW_IRQ 21
366# define OMAP_INT_24XX_IVA_IRQ 22
367# define OMAP_INT_24XX_EAC_IRQ 23
368# define OMAP_INT_24XX_CAM_IRQ 24
369# define OMAP_INT_24XX_DSS_IRQ 25
370# define OMAP_INT_24XX_MAIL_U0_MPU 26
371# define OMAP_INT_24XX_DSP_UMA 27
372# define OMAP_INT_24XX_DSP_MMU 28
373# define OMAP_INT_24XX_GPIO_BANK1 29
374# define OMAP_INT_24XX_GPIO_BANK2 30
375# define OMAP_INT_24XX_GPIO_BANK3 31
376# define OMAP_INT_24XX_GPIO_BANK4 32
377# define OMAP_INT_243X_GPIO_BANK5 33
378# define OMAP_INT_24XX_MAIL_U3_MPU 34
379# define OMAP_INT_24XX_WDT3 35
380# define OMAP_INT_24XX_WDT4 36
381# define OMAP_INT_24XX_GPTIMER1 37
382# define OMAP_INT_24XX_GPTIMER2 38
383# define OMAP_INT_24XX_GPTIMER3 39
384# define OMAP_INT_24XX_GPTIMER4 40
385# define OMAP_INT_24XX_GPTIMER5 41
386# define OMAP_INT_24XX_GPTIMER6 42
387# define OMAP_INT_24XX_GPTIMER7 43
388# define OMAP_INT_24XX_GPTIMER8 44
389# define OMAP_INT_24XX_GPTIMER9 45
390# define OMAP_INT_24XX_GPTIMER10 46
391# define OMAP_INT_24XX_GPTIMER11 47
392# define OMAP_INT_24XX_GPTIMER12 48
393# define OMAP_INT_24XX_PKA_IRQ 50
394# define OMAP_INT_24XX_SHA1MD5_IRQ 51
395# define OMAP_INT_24XX_RNG_IRQ 52
396# define OMAP_INT_24XX_MG_IRQ 53
397# define OMAP_INT_24XX_I2C1_IRQ 56
398# define OMAP_INT_24XX_I2C2_IRQ 57
399# define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
400# define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
401# define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
402# define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
403# define OMAP_INT_243X_MCBSP1_IRQ 64
404# define OMAP_INT_24XX_MCSPI1_IRQ 65
405# define OMAP_INT_24XX_MCSPI2_IRQ 66
406# define OMAP_INT_24XX_SSI1_IRQ0 67
407# define OMAP_INT_24XX_SSI1_IRQ1 68
408# define OMAP_INT_24XX_SSI2_IRQ0 69
409# define OMAP_INT_24XX_SSI2_IRQ1 70
410# define OMAP_INT_24XX_SSI_GDD_IRQ 71
411# define OMAP_INT_24XX_UART1_IRQ 72
412# define OMAP_INT_24XX_UART2_IRQ 73
413# define OMAP_INT_24XX_UART3_IRQ 74
414# define OMAP_INT_24XX_USB_IRQ_GEN 75
415# define OMAP_INT_24XX_USB_IRQ_NISO 76
416# define OMAP_INT_24XX_USB_IRQ_ISO 77
417# define OMAP_INT_24XX_USB_IRQ_HGEN 78
418# define OMAP_INT_24XX_USB_IRQ_HSOF 79
419# define OMAP_INT_24XX_USB_IRQ_OTG 80
420# define OMAP_INT_24XX_VLYNQ_IRQ 81
421# define OMAP_INT_24XX_MMC_IRQ 83
422# define OMAP_INT_24XX_MS_IRQ 84
423# define OMAP_INT_24XX_FAC_IRQ 85
424# define OMAP_INT_24XX_MCSPI3_IRQ 91
425# define OMAP_INT_243X_HS_USB_MC 92
426# define OMAP_INT_243X_HS_USB_DMA 93
427# define OMAP_INT_243X_CARKIT 94
428# define OMAP_INT_34XX_GPTIMER12 95
429
430
431enum omap_dma_model {
432 omap_dma_3_0,
433 omap_dma_3_1,
434 omap_dma_3_2,
435 omap_dma_4,
436};
437
438struct soc_dma_s;
439struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
440 MemoryRegion *sysmem,
441 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
442 enum omap_dma_model model);
443struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
444 MemoryRegion *sysmem,
445 struct omap_mpu_state_s *mpu, int fifo,
446 int chans, omap_clk iclk, omap_clk fclk);
447void omap_dma_reset(struct soc_dma_s *s);
448
449struct dma_irq_map {
450 int ih;
451 int intr;
452};
453
454
455enum omap_dma_port {
456 emiff = 0,
457 emifs,
458 imif,
459 tipb,
460 local,
461 tipb_mpui,
462 __omap_dma_port_last,
463};
464
465typedef enum {
466 constant = 0,
467 post_incremented,
468 single_index,
469 double_index,
470} omap_dma_addressing_t;
471
472
473struct omap_dma_lcd_channel_s {
474 enum omap_dma_port src;
475 hwaddr src_f1_top;
476 hwaddr src_f1_bottom;
477 hwaddr src_f2_top;
478 hwaddr src_f2_bottom;
479
480
481 unsigned char brust_f1;
482 unsigned char pack_f1;
483 unsigned char data_type_f1;
484 unsigned char brust_f2;
485 unsigned char pack_f2;
486 unsigned char data_type_f2;
487 unsigned char end_prog;
488 unsigned char repeat;
489 unsigned char auto_init;
490 unsigned char priority;
491 unsigned char fs;
492 unsigned char running;
493 unsigned char bs;
494 unsigned char omap_3_1_compatible_disable;
495 unsigned char dst;
496 unsigned char lch_type;
497 int16_t element_index_f1;
498 int16_t element_index_f2;
499 int32_t frame_index_f1;
500 int32_t frame_index_f2;
501 uint16_t elements_f1;
502 uint16_t frames_f1;
503 uint16_t elements_f2;
504 uint16_t frames_f2;
505 omap_dma_addressing_t mode_f1;
506 omap_dma_addressing_t mode_f2;
507
508
509 int interrupts;
510 int condition;
511 int dual;
512
513 int current_frame;
514 hwaddr phys_framebuffer[2];
515 qemu_irq irq;
516 struct omap_mpu_state_s *mpu;
517} *omap_dma_get_lcdch(struct soc_dma_s *s);
518
519
520
521
522
523# define OMAP_DMA_NO_DEVICE 0
524# define OMAP_DMA_MCSI1_TX 1
525# define OMAP_DMA_MCSI1_RX 2
526# define OMAP_DMA_I2C_RX 3
527# define OMAP_DMA_I2C_TX 4
528# define OMAP_DMA_EXT_NDMA_REQ0 5
529# define OMAP_DMA_EXT_NDMA_REQ1 6
530# define OMAP_DMA_UWIRE_TX 7
531# define OMAP_DMA_MCBSP1_TX 8
532# define OMAP_DMA_MCBSP1_RX 9
533# define OMAP_DMA_MCBSP3_TX 10
534# define OMAP_DMA_MCBSP3_RX 11
535# define OMAP_DMA_UART1_TX 12
536# define OMAP_DMA_UART1_RX 13
537# define OMAP_DMA_UART2_TX 14
538# define OMAP_DMA_UART2_RX 15
539# define OMAP_DMA_MCBSP2_TX 16
540# define OMAP_DMA_MCBSP2_RX 17
541# define OMAP_DMA_UART3_TX 18
542# define OMAP_DMA_UART3_RX 19
543# define OMAP_DMA_CAMERA_IF_RX 20
544# define OMAP_DMA_MMC_TX 21
545# define OMAP_DMA_MMC_RX 22
546# define OMAP_DMA_NAND 23
547# define OMAP_DMA_IRQ_LCD_LINE 24
548# define OMAP_DMA_MEMORY_STICK 25
549# define OMAP_DMA_USB_W2FC_RX0 26
550# define OMAP_DMA_USB_W2FC_RX1 27
551# define OMAP_DMA_USB_W2FC_RX2 28
552# define OMAP_DMA_USB_W2FC_TX0 29
553# define OMAP_DMA_USB_W2FC_TX1 30
554# define OMAP_DMA_USB_W2FC_TX2 31
555
556
557# define OMAP_DMA_CRYPTO_DES_IN 32
558# define OMAP_DMA_SPI_TX 33
559# define OMAP_DMA_SPI_RX 34
560# define OMAP_DMA_CRYPTO_HASH 35
561# define OMAP_DMA_CCP_ATTN 36
562# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
563# define OMAP_DMA_CMT_APE_TX_CHAN_0 38
564# define OMAP_DMA_CMT_APE_RV_CHAN_0 39
565# define OMAP_DMA_CMT_APE_TX_CHAN_1 40
566# define OMAP_DMA_CMT_APE_RV_CHAN_1 41
567# define OMAP_DMA_CMT_APE_TX_CHAN_2 42
568# define OMAP_DMA_CMT_APE_RV_CHAN_2 43
569# define OMAP_DMA_CMT_APE_TX_CHAN_3 44
570# define OMAP_DMA_CMT_APE_RV_CHAN_3 45
571# define OMAP_DMA_CMT_APE_TX_CHAN_4 46
572# define OMAP_DMA_CMT_APE_RV_CHAN_4 47
573# define OMAP_DMA_CMT_APE_TX_CHAN_5 48
574# define OMAP_DMA_CMT_APE_RV_CHAN_5 49
575# define OMAP_DMA_CMT_APE_TX_CHAN_6 50
576# define OMAP_DMA_CMT_APE_RV_CHAN_6 51
577# define OMAP_DMA_CMT_APE_TX_CHAN_7 52
578# define OMAP_DMA_CMT_APE_RV_CHAN_7 53
579# define OMAP_DMA_MMC2_TX 54
580# define OMAP_DMA_MMC2_RX 55
581# define OMAP_DMA_CRYPTO_DES_OUT 56
582
583
584
585
586# define OMAP24XX_DMA_NO_DEVICE 0
587# define OMAP24XX_DMA_XTI_DMA 1
588# define OMAP24XX_DMA_EXT_DMAREQ0 2
589# define OMAP24XX_DMA_EXT_DMAREQ1 3
590# define OMAP24XX_DMA_GPMC 4
591# define OMAP24XX_DMA_GFX 5
592# define OMAP24XX_DMA_DSS 6
593# define OMAP24XX_DMA_VLYNQ_TX 7
594# define OMAP24XX_DMA_CWT 8
595# define OMAP24XX_DMA_AES_TX 9
596# define OMAP24XX_DMA_AES_RX 10
597# define OMAP24XX_DMA_DES_TX 11
598# define OMAP24XX_DMA_DES_RX 12
599# define OMAP24XX_DMA_SHA1MD5_RX 13
600# define OMAP24XX_DMA_EXT_DMAREQ2 14
601# define OMAP24XX_DMA_EXT_DMAREQ3 15
602# define OMAP24XX_DMA_EXT_DMAREQ4 16
603# define OMAP24XX_DMA_EAC_AC_RD 17
604# define OMAP24XX_DMA_EAC_AC_WR 18
605# define OMAP24XX_DMA_EAC_MD_UL_RD 19
606# define OMAP24XX_DMA_EAC_MD_UL_WR 20
607# define OMAP24XX_DMA_EAC_MD_DL_RD 21
608# define OMAP24XX_DMA_EAC_MD_DL_WR 22
609# define OMAP24XX_DMA_EAC_BT_UL_RD 23
610# define OMAP24XX_DMA_EAC_BT_UL_WR 24
611# define OMAP24XX_DMA_EAC_BT_DL_RD 25
612# define OMAP24XX_DMA_EAC_BT_DL_WR 26
613# define OMAP24XX_DMA_I2C1_TX 27
614# define OMAP24XX_DMA_I2C1_RX 28
615# define OMAP24XX_DMA_I2C2_TX 29
616# define OMAP24XX_DMA_I2C2_RX 30
617# define OMAP24XX_DMA_MCBSP1_TX 31
618# define OMAP24XX_DMA_MCBSP1_RX 32
619# define OMAP24XX_DMA_MCBSP2_TX 33
620# define OMAP24XX_DMA_MCBSP2_RX 34
621# define OMAP24XX_DMA_SPI1_TX0 35
622# define OMAP24XX_DMA_SPI1_RX0 36
623# define OMAP24XX_DMA_SPI1_TX1 37
624# define OMAP24XX_DMA_SPI1_RX1 38
625# define OMAP24XX_DMA_SPI1_TX2 39
626# define OMAP24XX_DMA_SPI1_RX2 40
627# define OMAP24XX_DMA_SPI1_TX3 41
628# define OMAP24XX_DMA_SPI1_RX3 42
629# define OMAP24XX_DMA_SPI2_TX0 43
630# define OMAP24XX_DMA_SPI2_RX0 44
631# define OMAP24XX_DMA_SPI2_TX1 45
632# define OMAP24XX_DMA_SPI2_RX1 46
633
634# define OMAP24XX_DMA_UART1_TX 49
635# define OMAP24XX_DMA_UART1_RX 50
636# define OMAP24XX_DMA_UART2_TX 51
637# define OMAP24XX_DMA_UART2_RX 52
638# define OMAP24XX_DMA_UART3_TX 53
639# define OMAP24XX_DMA_UART3_RX 54
640# define OMAP24XX_DMA_USB_W2FC_TX0 55
641# define OMAP24XX_DMA_USB_W2FC_RX0 56
642# define OMAP24XX_DMA_USB_W2FC_TX1 57
643# define OMAP24XX_DMA_USB_W2FC_RX1 58
644# define OMAP24XX_DMA_USB_W2FC_TX2 59
645# define OMAP24XX_DMA_USB_W2FC_RX2 60
646# define OMAP24XX_DMA_MMC1_TX 61
647# define OMAP24XX_DMA_MMC1_RX 62
648# define OMAP24XX_DMA_MS 63
649# define OMAP24XX_DMA_EXT_DMAREQ5 64
650
651
652
653struct omap_gp_timer_s;
654struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
655 qemu_irq irq, omap_clk fclk, omap_clk iclk);
656void omap_gp_timer_reset(struct omap_gp_timer_s *s);
657
658
659struct omap_synctimer_s;
660struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
661 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
662void omap_synctimer_reset(struct omap_synctimer_s *s);
663
664struct omap_uart_s;
665struct omap_uart_s *omap_uart_init(hwaddr base,
666 qemu_irq irq, omap_clk fclk, omap_clk iclk,
667 qemu_irq txdma, qemu_irq rxdma,
668 const char *label, Chardev *chr);
669struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
670 struct omap_target_agent_s *ta,
671 qemu_irq irq, omap_clk fclk, omap_clk iclk,
672 qemu_irq txdma, qemu_irq rxdma,
673 const char *label, Chardev *chr);
674void omap_uart_reset(struct omap_uart_s *s);
675void omap_uart_attach(struct omap_uart_s *s, Chardev *chr);
676
677struct omap_mpuio_s;
678qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
679void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
680void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
681
682struct uWireSlave {
683 uint16_t (*receive)(void *opaque);
684 void (*send)(void *opaque, uint16_t data);
685 void *opaque;
686};
687struct omap_uwire_s;
688void omap_uwire_attach(struct omap_uwire_s *s,
689 uWireSlave *slave, int chipselect);
690
691
692struct omap_mcspi_s;
693struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
694 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
695void omap_mcspi_attach(struct omap_mcspi_s *s,
696 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
697 int chipselect);
698void omap_mcspi_reset(struct omap_mcspi_s *s);
699
700struct I2SCodec {
701 void *opaque;
702
703
704
705
706 void (*set_rate)(void *opaque, int in, int out);
707
708 void (*tx_swallow)(void *opaque);
709 qemu_irq rx_swallow;
710 qemu_irq tx_start;
711
712 int tx_rate;
713 int cts;
714 int rx_rate;
715 int rts;
716
717 struct i2s_fifo_s {
718 uint8_t *fifo;
719 int len;
720 int start;
721 int size;
722 } in, out;
723};
724struct omap_mcbsp_s;
725void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
726
727void omap_tap_init(struct omap_target_agent_s *ta,
728 struct omap_mpu_state_s *mpu);
729
730
731struct omap_lcd_panel_s;
732void omap_lcdc_reset(struct omap_lcd_panel_s *s);
733struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
734 hwaddr base,
735 qemu_irq irq,
736 struct omap_dma_lcd_channel_s *dma,
737 omap_clk clk);
738
739
740struct rfbi_chip_s {
741 void *opaque;
742 void (*write)(void *opaque, int dc, uint16_t value);
743 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
744 uint16_t (*read)(void *opaque, int dc);
745};
746struct omap_dss_s;
747void omap_dss_reset(struct omap_dss_s *s);
748struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
749 MemoryRegion *sysmem,
750 hwaddr l3_base,
751 qemu_irq irq, qemu_irq drq,
752 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
753 omap_clk ick1, omap_clk ick2);
754void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
755
756
757struct omap_mmc_s;
758struct omap_mmc_s *omap_mmc_init(hwaddr base,
759 MemoryRegion *sysmem,
760 BlockBackend *blk,
761 qemu_irq irq, qemu_irq dma[], omap_clk clk);
762struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
763 BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
764 omap_clk fclk, omap_clk iclk);
765void omap_mmc_reset(struct omap_mmc_s *s);
766void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
767void omap_mmc_enable(struct omap_mmc_s *s, int enable);
768
769
770I2CBus *omap_i2c_bus(DeviceState *omap_i2c);
771
772# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
773# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
774# define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
775# define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
776# define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
777# define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
778# define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
779# define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
780# define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630)
781
782# define cpu_is_omap15xx(cpu) \
783 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
784# define cpu_is_omap16xx(cpu) \
785 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
786# define cpu_is_omap24xx(cpu) \
787 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
788
789# define cpu_class_omap1(cpu) \
790 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
791# define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
792# define cpu_class_omap3(cpu) \
793 (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
794
795struct omap_mpu_state_s {
796 enum omap_mpu_model {
797 omap310,
798 omap1510,
799 omap1610,
800 omap1710,
801 omap2410,
802 omap2420,
803 omap2422,
804 omap2423,
805 omap2430,
806 omap3430,
807 omap3630,
808 } mpu_model;
809
810 ARMCPU *cpu;
811
812 qemu_irq *drq;
813
814 qemu_irq wakeup;
815
816 MemoryRegion ulpd_pm_iomem;
817 MemoryRegion pin_cfg_iomem;
818 MemoryRegion id_iomem;
819 MemoryRegion id_iomem_e18;
820 MemoryRegion id_iomem_ed4;
821 MemoryRegion id_iomem_e20;
822 MemoryRegion mpui_iomem;
823 MemoryRegion tcmi_iomem;
824 MemoryRegion clkm_iomem;
825 MemoryRegion clkdsp_iomem;
826 MemoryRegion mpui_io_iomem;
827 MemoryRegion tap_iomem;
828 MemoryRegion imif_ram;
829 MemoryRegion emiff_ram;
830 MemoryRegion sdram;
831 MemoryRegion sram;
832
833 struct omap_dma_port_if_s {
834 uint32_t (*read[3])(struct omap_mpu_state_s *s,
835 hwaddr offset);
836 void (*write[3])(struct omap_mpu_state_s *s,
837 hwaddr offset, uint32_t value);
838 int (*addr_valid)(struct omap_mpu_state_s *s,
839 hwaddr addr);
840 } port[__omap_dma_port_last];
841
842 unsigned long sdram_size;
843 unsigned long sram_size;
844
845
846 struct omap_uart_s *uart[3];
847
848 DeviceState *gpio;
849
850 struct omap_mcbsp_s *mcbsp1;
851 struct omap_mcbsp_s *mcbsp3;
852
853
854 struct omap_32khz_timer_s *os_timer;
855
856 struct omap_mmc_s *mmc;
857
858 struct omap_mpuio_s *mpuio;
859
860 struct omap_uwire_s *microwire;
861
862 struct omap_pwl_s *pwl;
863 struct omap_pwt_s *pwt;
864 DeviceState *i2c[2];
865
866 struct omap_rtc_s *rtc;
867
868 struct omap_mcbsp_s *mcbsp2;
869
870 struct omap_lpg_s *led[2];
871
872
873 DeviceState *ih[2];
874
875 struct soc_dma_s *dma;
876
877 struct omap_mpu_timer_s *timer[3];
878 struct omap_watchdog_timer_s *wdt;
879
880 struct omap_lcd_panel_s *lcd;
881
882 uint32_t ulpd_pm_regs[21];
883 int64_t ulpd_gauge_start;
884
885 uint32_t func_mux_ctrl[14];
886 uint32_t comp_mode_ctrl[1];
887 uint32_t pull_dwn_ctrl[4];
888 uint32_t gate_inh_ctrl[1];
889 uint32_t voltage_ctrl[1];
890 uint32_t test_dbg_ctrl[1];
891 uint32_t mod_conf_ctrl[1];
892 int compat1509;
893
894 uint32_t mpui_ctrl;
895
896 struct omap_tipb_bridge_s *private_tipb;
897 struct omap_tipb_bridge_s *public_tipb;
898
899 uint32_t tcmi_regs[17];
900
901 struct dpll_ctl_s *dpll[3];
902
903 omap_clk clks;
904 struct {
905 int cold_start;
906 int clocking_scheme;
907 uint16_t arm_ckctl;
908 uint16_t arm_idlect1;
909 uint16_t arm_idlect2;
910 uint16_t arm_ewupct;
911 uint16_t arm_rstct1;
912 uint16_t arm_rstct2;
913 uint16_t arm_ckout1;
914 int dpll1_mode;
915 uint16_t dsp_idlect1;
916 uint16_t dsp_idlect2;
917 uint16_t dsp_rstct2;
918 } clkm;
919
920
921 struct omap_l4_s *l4;
922
923 struct omap_gp_timer_s *gptimer[12];
924 struct omap_synctimer_s *synctimer;
925
926 struct omap_prcm_s *prcm;
927 struct omap_sdrc_s *sdrc;
928 struct omap_gpmc_s *gpmc;
929 struct omap_sysctl_s *sysc;
930
931 struct omap_mcspi_s *mcspi[2];
932
933 struct omap_dss_s *dss;
934
935 struct omap_eac_s *eac;
936};
937
938
939struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
940 unsigned long sdram_size,
941 const char *core);
942
943
944struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
945 unsigned long sdram_size,
946 const char *core);
947
948uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
949void omap_badwidth_write8(void *opaque, hwaddr addr,
950 uint32_t value);
951uint32_t omap_badwidth_read16(void *opaque, hwaddr addr);
952void omap_badwidth_write16(void *opaque, hwaddr addr,
953 uint32_t value);
954uint32_t omap_badwidth_read32(void *opaque, hwaddr addr);
955void omap_badwidth_write32(void *opaque, hwaddr addr,
956 uint32_t value);
957
958void omap_mpu_wakeup(void *opaque, int irq, int req);
959
960# define OMAP_BAD_REG(paddr) \
961 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \
962 __func__, paddr)
963# define OMAP_RO_REG(paddr) \
964 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \
965 HWADDR_PRIx "\n", \
966 __func__, paddr)
967
968
969
970#define OMAP_TAG_CLOCK 0x4f01
971#define OMAP_TAG_MMC 0x4f02
972#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
973#define OMAP_TAG_USB 0x4f04
974#define OMAP_TAG_LCD 0x4f05
975#define OMAP_TAG_GPIO_SWITCH 0x4f06
976#define OMAP_TAG_UART 0x4f07
977#define OMAP_TAG_FBMEM 0x4f08
978#define OMAP_TAG_STI_CONSOLE 0x4f09
979#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
980#define OMAP_TAG_PARTITION 0x4f0b
981#define OMAP_TAG_TEA5761 0x4f10
982#define OMAP_TAG_TMP105 0x4f11
983#define OMAP_TAG_BOOT_REASON 0x4f80
984#define OMAP_TAG_FLASH_PART_STR 0x4f81
985#define OMAP_TAG_VERSION_STR 0x4f82
986
987enum {
988 OMAP_GPIOSW_TYPE_COVER = 0 << 4,
989 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
990 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
991};
992
993#define OMAP_GPIOSW_INVERTED 0x0001
994#define OMAP_GPIOSW_OUTPUT 0x0002
995
996# define OMAP_MPUI_REG_MASK 0x000007ff
997
998#endif
999