LXR qemu/include/hw/arm/smmu-common.h

   1/*
   2 * ARM SMMU Support
   3 *
   4 * Copyright (C) 2015-2016 Broadcom Corporation
   5 * Copyright (c) 2017 Red Hat, Inc.
   6 * Written by Prem Mallappa, Eric Auger
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 */
  18
  19#ifndef HW_ARM_SMMU_COMMON_H
  20#define HW_ARM_SMMU_COMMON_H
  21
  22#include "hw/sysbus.h"
  23#include "hw/pci/pci.h"
  24
  25#define SMMU_PCI_BUS_MAX      256
  26#define SMMU_PCI_DEVFN_MAX    256
  27#define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
  28
  29#define SMMU_MAX_VA_BITS      48
  30
  31/*
  32 * Page table walk error types
  33 */
  34typedef enum {
  35    SMMU_PTW_ERR_NONE,
  36    SMMU_PTW_ERR_WALK_EABT,   /* Translation walk external abort */
  37    SMMU_PTW_ERR_TRANSLATION, /* Translation fault */
  38    SMMU_PTW_ERR_ADDR_SIZE,   /* Address Size fault */
  39    SMMU_PTW_ERR_ACCESS,      /* Access fault */
  40    SMMU_PTW_ERR_PERMISSION,  /* Permission fault */
  41} SMMUPTWEventType;
  42
  43typedef struct SMMUPTWEventInfo {
  44    SMMUPTWEventType type;
  45    dma_addr_t addr; /* fetched address that induced an abort, if any */
  46} SMMUPTWEventInfo;
  47
  48typedef struct SMMUTransTableInfo {
  49    bool disabled;             /* is the translation table disabled? */
  50    uint64_t ttb;              /* TT base address */
  51    uint8_t tsz;               /* input range, ie. 2^(64 -tsz)*/
  52    uint8_t granule_sz;        /* granule page shift */
  53} SMMUTransTableInfo;
  54
  55/*
  56 * Generic structure populated by derived SMMU devices
  57 * after decoding the configuration information and used as
  58 * input to the page table walk
  59 */
  60typedef struct SMMUTransCfg {
  61    int stage;                 /* translation stage */
  62    bool aa64;                 /* arch64 or aarch32 translation table */
  63    bool disabled;             /* smmu is disabled */
  64    bool bypassed;             /* translation is bypassed */
  65    bool aborted;              /* translation is aborted */
  66    uint64_t ttb;              /* TT base address */
  67    uint8_t oas;               /* output address width */
  68    uint8_t tbi;               /* Top Byte Ignore */
  69    uint16_t asid;
  70    SMMUTransTableInfo tt[2];
  71    uint32_t iotlb_hits;       /* counts IOTLB hits for this asid */
  72    uint32_t iotlb_misses;     /* counts IOTLB misses for this asid */
  73} SMMUTransCfg;
  74
  75typedef struct SMMUDevice {
  76    void               *smmu;
  77    PCIBus             *bus;
  78    int                devfn;
  79    IOMMUMemoryRegion  iommu;
  80    AddressSpace       as;
  81    uint32_t           cfg_cache_hits;
  82    uint32_t           cfg_cache_misses;
  83} SMMUDevice;
  84
  85typedef struct SMMUNotifierNode {
  86    SMMUDevice *sdev;
  87    QLIST_ENTRY(SMMUNotifierNode) next;
  88} SMMUNotifierNode;
  89
  90typedef struct SMMUPciBus {
  91    PCIBus       *bus;
  92    SMMUDevice   *pbdev[0]; /* Parent array is sparse, so dynamically alloc */
  93} SMMUPciBus;
  94
  95typedef struct SMMUIOTLBKey {
  96    uint64_t iova;
  97    uint16_t asid;
  98} SMMUIOTLBKey;
  99
 100typedef struct SMMUState {
 101    /* <private> */
 102    SysBusDevice  dev;
 103    const char *mrtypename;
 104    MemoryRegion iomem;
 105
 106    GHashTable *smmu_pcibus_by_busptr;
 107    GHashTable *configs; /* cache for configuration data */
 108    GHashTable *iotlb;
 109    SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX];
 110    PCIBus *pci_bus;
 111    QLIST_HEAD(, SMMUNotifierNode) notifiers_list;
 112    uint8_t bus_num;
 113    PCIBus *primary_bus;
 114} SMMUState;
 115
 116typedef struct {
 117    /* <private> */
 118    SysBusDeviceClass parent_class;
 119
 120    /*< public >*/
 121
 122    DeviceRealize parent_realize;
 123
 124} SMMUBaseClass;
 125
 126#define TYPE_ARM_SMMU "arm-smmu"
 127#define ARM_SMMU(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_ARM_SMMU)
 128#define ARM_SMMU_CLASS(klass)                                    \
 129    OBJECT_CLASS_CHECK(SMMUBaseClass, (klass), TYPE_ARM_SMMU)
 130#define ARM_SMMU_GET_CLASS(obj)                              \
 131    OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_ARM_SMMU)
 132
 133/* Return the SMMUPciBus handle associated to a PCI bus number */
 134SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num);
 135
 136/* Return the stream ID of an SMMU device */
 137static inline uint16_t smmu_get_sid(SMMUDevice *sdev)
 138{
 139    return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn);
 140}
 141
 142/**
 143 * smmu_ptw - Perform the page table walk for a given iova / access flags
 144 * pair, according to @cfg translation config
 145 */
 146int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
 147             IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info);
 148
 149/**
 150 * select_tt - compute which translation table shall be used according to
 151 * the input iova and translation config and return the TT specific info
 152 */
 153SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
 154
 155/* Return the iommu mr associated to @sid, or NULL if none */
 156IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
 157
 158#define SMMU_IOTLB_MAX_SIZE 256
 159
 160void smmu_iotlb_inv_all(SMMUState *s);
 161void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
 162void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova);
 163
 164/* Unmap the range of all the notifiers registered to any IOMMU mr */
 165void smmu_inv_notifiers_all(SMMUState *s);
 166
 167/* Unmap the range of all the notifiers registered to @mr */
 168void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
 169
 170#endif  /* HW_ARM_SMMU_COMMON */
 171