LXR qemu/include/hw/block/flash.h

   1#ifndef HW_FLASH_H
   2#define HW_FLASH_H
   3
   4/* NOR flash devices */
   5
   6#include "exec/memory.h"
   7
   8/* pflash_cfi01.c */
   9
  10#define TYPE_PFLASH_CFI01 "cfi.pflash01"
  11#define PFLASH_CFI01(obj) \
  12    OBJECT_CHECK(PFlashCFI01, (obj), TYPE_PFLASH_CFI01)
  13
  14typedef struct PFlashCFI01 PFlashCFI01;
  15
  16PFlashCFI01 *pflash_cfi01_register(hwaddr base,
  17                                   const char *name,
  18                                   hwaddr size,
  19                                   BlockBackend *blk,
  20                                   uint32_t sector_len,
  21                                   int width,
  22                                   uint16_t id0, uint16_t id1,
  23                                   uint16_t id2, uint16_t id3,
  24                                   int be);
  25BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl);
  26MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl);
  27
  28/* pflash_cfi02.c */
  29
  30#define TYPE_PFLASH_CFI02 "cfi.pflash02"
  31#define PFLASH_CFI02(obj) \
  32    OBJECT_CHECK(PFlashCFI02, (obj), TYPE_PFLASH_CFI02)
  33
  34typedef struct PFlashCFI02 PFlashCFI02;
  35
  36PFlashCFI02 *pflash_cfi02_register(hwaddr base,
  37                                   const char *name,
  38                                   hwaddr size,
  39                                   BlockBackend *blk,
  40                                   uint32_t sector_len,
  41                                   int nb_mappings,
  42                                   int width,
  43                                   uint16_t id0, uint16_t id1,
  44                                   uint16_t id2, uint16_t id3,
  45                                   uint16_t unlock_addr0,
  46                                   uint16_t unlock_addr1,
  47                                   int be);
  48
  49/* nand.c */
  50DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id);
  51void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
  52                  uint8_t ce, uint8_t wp, uint8_t gnd);
  53void nand_getpins(DeviceState *dev, int *rb);
  54void nand_setio(DeviceState *dev, uint32_t value);
  55uint32_t nand_getio(DeviceState *dev);
  56uint32_t nand_getbuswidth(DeviceState *dev);
  57
  58#define NAND_MFR_TOSHIBA        0x98
  59#define NAND_MFR_SAMSUNG        0xec
  60#define NAND_MFR_FUJITSU        0x04
  61#define NAND_MFR_NATIONAL       0x8f
  62#define NAND_MFR_RENESAS        0x07
  63#define NAND_MFR_STMICRO        0x20
  64#define NAND_MFR_HYNIX          0xad
  65#define NAND_MFR_MICRON         0x2c
  66
  67/* onenand.c */
  68void *onenand_raw_otp(DeviceState *onenand_device);
  69
  70/* ecc.c */
  71typedef struct {
  72    uint8_t cp;         /* Column parity */
  73    uint16_t lp[2];     /* Line parity */
  74    uint16_t count;
  75} ECCState;
  76
  77uint8_t ecc_digest(ECCState *s, uint8_t sample);
  78void ecc_reset(ECCState *s);
  79extern VMStateDescription vmstate_ecc_state;
  80
  81#endif
  82