LXR qemu/include/hw/intc/bcm2836

   1/*
   2 * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
   4 *
   5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
   6 * Written by Andrew Baumann
   7 *
   8 * ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti
   9 * Added basic IRQ_TIMER interrupt support
  10 *
  11 * This code is licensed under the GNU GPLv2 and later.
  12 */
  13
  14#ifndef BCM2836_CONTROL_H
  15#define BCM2836_CONTROL_H
  16
  17#include "hw/sysbus.h"
  18#include "qemu/timer.h"
  19
  20/* 4 mailboxes per core, for 16 total */
  21#define BCM2836_NCORES 4
  22#define BCM2836_MBPERCORE 4
  23
  24#define TYPE_BCM2836_CONTROL "bcm2836-control"
  25#define BCM2836_CONTROL(obj) \
  26    OBJECT_CHECK(BCM2836ControlState, (obj), TYPE_BCM2836_CONTROL)
  27
  28typedef struct BCM2836ControlState {
  29    /*< private >*/
  30    SysBusDevice busdev;
  31    /*< public >*/
  32    MemoryRegion iomem;
  33
  34    /* mailbox state */
  35    uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE];
  36
  37    /* interrupt routing/control registers */
  38    uint8_t route_gpu_irq, route_gpu_fiq;
  39    uint32_t timercontrol[BCM2836_NCORES];
  40    uint32_t mailboxcontrol[BCM2836_NCORES];
  41
  42    /* interrupt status regs (derived from input pins; not visible to user) */
  43    bool gpu_irq, gpu_fiq;
  44    uint8_t timerirqs[BCM2836_NCORES];
  45
  46    /* local timer */
  47    QEMUTimer timer;
  48    uint32_t local_timer_control;
  49    uint8_t route_localtimer;
  50
  51    /* interrupt source registers, post-routing (also input-derived; visible) */
  52    uint32_t irqsrc[BCM2836_NCORES];
  53    uint32_t fiqsrc[BCM2836_NCORES];
  54
  55    /* outputs to CPU cores */
  56    qemu_irq irq[BCM2836_NCORES];
  57    qemu_irq fiq[BCM2836_NCORES];
  58} BCM2836ControlState;
  59
  60#endif
  61