1#ifndef QEMU_PCI_H
2#define QEMU_PCI_H
3
4#include "hw/qdev.h"
5#include "exec/memory.h"
6#include "sysemu/dma.h"
7
8
9#include "hw/isa/isa.h"
10
11#include "hw/pci/pcie.h"
12
13extern bool pci_available;
14
15
16
17#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
19#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
20#define PCI_FUNC(devfn) ((devfn) & 0x07)
21#define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
22#define PCI_BUS_MAX 256
23#define PCI_DEVFN_MAX 256
24#define PCI_SLOT_MAX 32
25#define PCI_FUNC_MAX 8
26
27
28#include "hw/pci/pci_ids.h"
29
30
31
32
33#define PCI_DEVICE_ID_IBM_440GX 0x027f
34#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
35
36
37#define PCI_VENDOR_ID_HITACHI 0x1054
38#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
39
40
41#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
42#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
43#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
44#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
45#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
46
47
48#define PCI_DEVICE_ID_REALTEK_8029 0x8029
49
50
51#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
52
53
54#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
55
56
57#define PCI_VENDOR_ID_QEMU 0x1234
58#define PCI_DEVICE_ID_QEMU_VGA 0x1111
59
60
61#define PCI_VENDOR_ID_VMWARE 0x15ad
62#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
63#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
64#define PCI_DEVICE_ID_VMWARE_NET 0x0720
65#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
66#define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
67#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
68#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
69
70
71#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
72#define PCI_DEVICE_ID_INTEL_82557 0x1229
73#define PCI_DEVICE_ID_INTEL_82801IR 0x2922
74
75
76#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
77#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
78#define PCI_SUBDEVICE_ID_QEMU 0x1100
79
80#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
81#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
82#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
83#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
84#define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
85#define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
86#define PCI_DEVICE_ID_VIRTIO_9P 0x1009
87#define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
88
89#define PCI_VENDOR_ID_REDHAT 0x1b36
90#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
91#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
92#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
93#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
94#define PCI_DEVICE_ID_REDHAT_TEST 0x0005
95#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
96#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
97#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
98#define PCI_DEVICE_ID_REDHAT_PXB 0x0009
99#define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
100#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
101#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
102#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
103#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
104#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
105#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
106
107#define FMT_PCIBUS PRIx64
108
109typedef uint64_t pcibus_t;
110
111struct PCIHostDeviceAddress {
112 unsigned int domain;
113 unsigned int bus;
114 unsigned int slot;
115 unsigned int function;
116};
117
118typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
119 uint32_t address, uint32_t data, int len);
120typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
121 uint32_t address, int len);
122typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
123 pcibus_t addr, pcibus_t size, int type);
124typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
125
126typedef struct PCIIORegion {
127 pcibus_t addr;
128#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
129 pcibus_t size;
130 uint8_t type;
131 MemoryRegion *memory;
132 MemoryRegion *address_space;
133} PCIIORegion;
134
135#define PCI_ROM_SLOT 6
136#define PCI_NUM_REGIONS 7
137
138enum {
139 QEMU_PCI_VGA_MEM,
140 QEMU_PCI_VGA_IO_LO,
141 QEMU_PCI_VGA_IO_HI,
142 QEMU_PCI_VGA_NUM_REGIONS,
143};
144
145#define QEMU_PCI_VGA_MEM_BASE 0xa0000
146#define QEMU_PCI_VGA_MEM_SIZE 0x20000
147#define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
148#define QEMU_PCI_VGA_IO_LO_SIZE 0xc
149#define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
150#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
151
152#include "hw/pci/pci_regs.h"
153
154
155#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
156
157
158#define PCI_CONFIG_HEADER_SIZE 0x40
159
160#define PCI_CONFIG_SPACE_SIZE 0x100
161
162#define PCIE_CONFIG_SPACE_SIZE 0x1000
163
164#define PCI_NUM_PINS 4
165
166
167enum {
168 QEMU_PCI_CAP_MSI = 0x1,
169 QEMU_PCI_CAP_MSIX = 0x2,
170 QEMU_PCI_CAP_EXPRESS = 0x4,
171
172
173#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
174 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
175
176
177#define QEMU_PCI_CAP_SERR_BITNR 4
178 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
179
180#define QEMU_PCI_SHPC_BITNR 5
181 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
182#define QEMU_PCI_SLOTID_BITNR 6
183 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
184
185#define QEMU_PCIE_SLTCAP_PCP_BITNR 7
186 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
187
188#define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
189 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
190#define QEMU_PCIE_EXTCAP_INIT_BITNR 9
191 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
192};
193
194#define TYPE_PCI_DEVICE "pci-device"
195#define PCI_DEVICE(obj) \
196 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
197#define PCI_DEVICE_CLASS(klass) \
198 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
199#define PCI_DEVICE_GET_CLASS(obj) \
200 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
201
202
203#define INTERFACE_PCIE_DEVICE "pci-express-device"
204
205
206#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
207
208typedef struct PCIINTxRoute {
209 enum {
210 PCI_INTX_ENABLED,
211 PCI_INTX_INVERTED,
212 PCI_INTX_DISABLED,
213 } mode;
214 int irq;
215} PCIINTxRoute;
216
217typedef struct PCIDeviceClass {
218 DeviceClass parent_class;
219
220 void (*realize)(PCIDevice *dev, Error **errp);
221 PCIUnregisterFunc *exit;
222 PCIConfigReadFunc *config_read;
223 PCIConfigWriteFunc *config_write;
224
225 uint16_t vendor_id;
226 uint16_t device_id;
227 uint8_t revision;
228 uint16_t class_id;
229 uint16_t subsystem_vendor_id;
230 uint16_t subsystem_id;
231
232
233
234
235
236
237 int is_bridge;
238
239
240 const char *romfile;
241} PCIDeviceClass;
242
243typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
244typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
245 MSIMessage msg);
246typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
247typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
248 unsigned int vector_start,
249 unsigned int vector_end);
250
251enum PCIReqIDType {
252 PCI_REQ_ID_INVALID = 0,
253 PCI_REQ_ID_BDF,
254 PCI_REQ_ID_SECONDARY_BUS,
255 PCI_REQ_ID_MAX,
256};
257typedef enum PCIReqIDType PCIReqIDType;
258
259struct PCIReqIDCache {
260 PCIDevice *dev;
261 PCIReqIDType type;
262};
263typedef struct PCIReqIDCache PCIReqIDCache;
264
265struct PCIDevice {
266 DeviceState qdev;
267
268
269 uint8_t *config;
270
271
272
273 uint8_t *cmask;
274
275
276 uint8_t *wmask;
277
278
279 uint8_t *w1cmask;
280
281
282 uint8_t *used;
283
284
285 int32_t devfn;
286
287
288
289
290 PCIReqIDCache requester_id_cache;
291 char name[64];
292 PCIIORegion io_regions[PCI_NUM_REGIONS];
293 AddressSpace bus_master_as;
294 MemoryRegion bus_master_container_region;
295 MemoryRegion bus_master_enable_region;
296
297
298 PCIConfigReadFunc *config_read;
299 PCIConfigWriteFunc *config_write;
300
301
302 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
303 bool has_vga;
304
305
306 uint8_t irq_state;
307
308
309 uint32_t cap_present;
310
311
312 uint8_t msix_cap;
313
314
315 int msix_entries_nr;
316
317
318 uint8_t *msix_table;
319 uint8_t *msix_pba;
320
321 MemoryRegion msix_exclusive_bar;
322
323 MemoryRegion msix_table_mmio;
324 MemoryRegion msix_pba_mmio;
325
326 unsigned *msix_entry_used;
327
328 bool msix_function_masked;
329
330 int32_t version_id;
331
332
333 uint8_t msi_cap;
334
335
336 PCIExpressDevice exp;
337
338
339 SHPCDevice *shpc;
340
341
342 char *romfile;
343 bool has_rom;
344 MemoryRegion rom;
345 uint32_t rom_bar;
346
347
348 PCIINTxRoutingNotifier intx_routing_notifier;
349
350
351 MSIVectorUseNotifier msix_vector_use_notifier;
352 MSIVectorReleaseNotifier msix_vector_release_notifier;
353 MSIVectorPollNotifier msix_vector_poll_notifier;
354};
355
356void pci_register_bar(PCIDevice *pci_dev, int region_num,
357 uint8_t attr, MemoryRegion *memory);
358void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
359 MemoryRegion *io_lo, MemoryRegion *io_hi);
360void pci_unregister_vga(PCIDevice *pci_dev);
361pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
362
363int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
364 uint8_t offset, uint8_t size,
365 Error **errp);
366
367void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
368
369uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
370
371
372uint32_t pci_default_read_config(PCIDevice *d,
373 uint32_t address, int len);
374void pci_default_write_config(PCIDevice *d,
375 uint32_t address, uint32_t val, int len);
376void pci_device_save(PCIDevice *s, QEMUFile *f);
377int pci_device_load(PCIDevice *s, QEMUFile *f);
378MemoryRegion *pci_address_space(PCIDevice *dev);
379MemoryRegion *pci_address_space_io(PCIDevice *dev);
380
381
382
383
384
385int pci_bar(PCIDevice *d, int reg);
386
387typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
388typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
389typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
390
391#define TYPE_PCI_BUS "PCI"
392#define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
393#define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
394#define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
395#define TYPE_PCIE_BUS "PCIE"
396
397bool pci_bus_is_express(PCIBus *bus);
398bool pci_bus_is_root(PCIBus *bus);
399bool pci_bus_allows_extended_config_space(PCIBus *bus);
400
401void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
402 const char *name,
403 MemoryRegion *address_space_mem,
404 MemoryRegion *address_space_io,
405 uint8_t devfn_min, const char *typename);
406PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
407 MemoryRegion *address_space_mem,
408 MemoryRegion *address_space_io,
409 uint8_t devfn_min, const char *typename);
410void pci_root_bus_cleanup(PCIBus *bus);
411void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
412 void *irq_opaque, int nirq);
413void pci_bus_irqs_cleanup(PCIBus *bus);
414int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
415
416int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
417PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
418 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
419 void *irq_opaque,
420 MemoryRegion *address_space_mem,
421 MemoryRegion *address_space_io,
422 uint8_t devfn_min, int nirq,
423 const char *typename);
424void pci_unregister_root_bus(PCIBus *bus);
425void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
426PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
427bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
428void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
429void pci_device_set_intx_routing_notifier(PCIDevice *dev,
430 PCIINTxRoutingNotifier notifier);
431void pci_device_reset(PCIDevice *dev);
432
433PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
434 const char *default_model,
435 const char *default_devaddr);
436
437PCIDevice *pci_vga_init(PCIBus *bus);
438
439static inline PCIBus *pci_get_bus(const PCIDevice *dev)
440{
441 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
442}
443int pci_bus_num(PCIBus *s);
444static inline int pci_dev_bus_num(const PCIDevice *dev)
445{
446 return pci_bus_num(pci_get_bus(dev));
447}
448
449int pci_bus_numa_node(PCIBus *bus);
450void pci_for_each_device(PCIBus *bus, int bus_num,
451 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
452 void *opaque);
453void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
454 void (*fn)(PCIBus *bus, PCIDevice *d,
455 void *opaque),
456 void *opaque);
457void pci_for_each_bus_depth_first(PCIBus *bus,
458 void *(*begin)(PCIBus *bus, void *parent_state),
459 void (*end)(PCIBus *bus, void *state),
460 void *parent_state);
461PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
462
463
464static inline
465void pci_for_each_bus(PCIBus *bus,
466 void (*fn)(PCIBus *bus, void *opaque),
467 void *opaque)
468{
469 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
470}
471
472PCIBus *pci_device_root_bus(const PCIDevice *d);
473const char *pci_root_bus_path(PCIDevice *dev);
474PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
475int pci_qdev_find_device(const char *id, PCIDevice **pdev);
476void pci_bus_get_w64_range(PCIBus *bus, Range *range);
477
478void pci_device_deassert_intx(PCIDevice *dev);
479
480typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
481
482AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
483void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
484
485static inline void
486pci_set_byte(uint8_t *config, uint8_t val)
487{
488 *config = val;
489}
490
491static inline uint8_t
492pci_get_byte(const uint8_t *config)
493{
494 return *config;
495}
496
497static inline void
498pci_set_word(uint8_t *config, uint16_t val)
499{
500 stw_le_p(config, val);
501}
502
503static inline uint16_t
504pci_get_word(const uint8_t *config)
505{
506 return lduw_le_p(config);
507}
508
509static inline void
510pci_set_long(uint8_t *config, uint32_t val)
511{
512 stl_le_p(config, val);
513}
514
515static inline uint32_t
516pci_get_long(const uint8_t *config)
517{
518 return ldl_le_p(config);
519}
520
521
522
523
524
525
526
527
528static inline void
529pci_set_quad(uint8_t *config, uint64_t val)
530{
531 stq_le_p(config, val);
532}
533
534static inline uint64_t
535pci_get_quad(const uint8_t *config)
536{
537 return ldq_le_p(config);
538}
539
540static inline void
541pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
542{
543 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
544}
545
546static inline void
547pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
548{
549 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
550}
551
552static inline void
553pci_config_set_revision(uint8_t *pci_config, uint8_t val)
554{
555 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
556}
557
558static inline void
559pci_config_set_class(uint8_t *pci_config, uint16_t val)
560{
561 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
562}
563
564static inline void
565pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
566{
567 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
568}
569
570static inline void
571pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
572{
573 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
574}
575
576
577
578
579
580
581
582static inline uint8_t
583pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
584{
585 uint8_t val = pci_get_byte(config);
586 pci_set_byte(config, val & ~mask);
587 return val & mask;
588}
589
590static inline uint8_t
591pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
592{
593 uint8_t val = pci_get_byte(config);
594 pci_set_byte(config, val | mask);
595 return val & mask;
596}
597
598static inline uint16_t
599pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
600{
601 uint16_t val = pci_get_word(config);
602 pci_set_word(config, val & ~mask);
603 return val & mask;
604}
605
606static inline uint16_t
607pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
608{
609 uint16_t val = pci_get_word(config);
610 pci_set_word(config, val | mask);
611 return val & mask;
612}
613
614static inline uint32_t
615pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
616{
617 uint32_t val = pci_get_long(config);
618 pci_set_long(config, val & ~mask);
619 return val & mask;
620}
621
622static inline uint32_t
623pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
624{
625 uint32_t val = pci_get_long(config);
626 pci_set_long(config, val | mask);
627 return val & mask;
628}
629
630static inline uint64_t
631pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
632{
633 uint64_t val = pci_get_quad(config);
634 pci_set_quad(config, val & ~mask);
635 return val & mask;
636}
637
638static inline uint64_t
639pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
640{
641 uint64_t val = pci_get_quad(config);
642 pci_set_quad(config, val | mask);
643 return val & mask;
644}
645
646
647static inline void
648pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
649{
650 uint8_t val = pci_get_byte(config);
651 uint8_t rval = reg << ctz32(mask);
652 pci_set_byte(config, (~mask & val) | (mask & rval));
653}
654
655static inline uint8_t
656pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
657{
658 uint8_t val = pci_get_byte(config);
659 return (val & mask) >> ctz32(mask);
660}
661
662static inline void
663pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
664{
665 uint16_t val = pci_get_word(config);
666 uint16_t rval = reg << ctz32(mask);
667 pci_set_word(config, (~mask & val) | (mask & rval));
668}
669
670static inline uint16_t
671pci_get_word_by_mask(uint8_t *config, uint16_t mask)
672{
673 uint16_t val = pci_get_word(config);
674 return (val & mask) >> ctz32(mask);
675}
676
677static inline void
678pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
679{
680 uint32_t val = pci_get_long(config);
681 uint32_t rval = reg << ctz32(mask);
682 pci_set_long(config, (~mask & val) | (mask & rval));
683}
684
685static inline uint32_t
686pci_get_long_by_mask(uint8_t *config, uint32_t mask)
687{
688 uint32_t val = pci_get_long(config);
689 return (val & mask) >> ctz32(mask);
690}
691
692static inline void
693pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
694{
695 uint64_t val = pci_get_quad(config);
696 uint64_t rval = reg << ctz32(mask);
697 pci_set_quad(config, (~mask & val) | (mask & rval));
698}
699
700static inline uint64_t
701pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
702{
703 uint64_t val = pci_get_quad(config);
704 return (val & mask) >> ctz32(mask);
705}
706
707PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
708 const char *name);
709PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
710 bool multifunction,
711 const char *name);
712PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
713PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
714
715void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
716
717qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
718void pci_set_irq(PCIDevice *pci_dev, int level);
719
720static inline void pci_irq_assert(PCIDevice *pci_dev)
721{
722 pci_set_irq(pci_dev, 1);
723}
724
725static inline void pci_irq_deassert(PCIDevice *pci_dev)
726{
727 pci_set_irq(pci_dev, 0);
728}
729
730
731
732
733
734static inline void pci_irq_pulse(PCIDevice *pci_dev)
735{
736 pci_irq_assert(pci_dev);
737 pci_irq_deassert(pci_dev);
738}
739
740static inline int pci_is_express(const PCIDevice *d)
741{
742 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
743}
744
745static inline int pci_is_express_downstream_port(const PCIDevice *d)
746{
747 uint8_t type;
748
749 if (!pci_is_express(d) || !d->exp.exp_cap) {
750 return 0;
751 }
752
753 type = pcie_cap_get_type(d);
754
755 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
756}
757
758static inline uint32_t pci_config_size(const PCIDevice *d)
759{
760 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
761}
762
763static inline uint16_t pci_get_bdf(PCIDevice *dev)
764{
765 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
766}
767
768uint16_t pci_requester_id(PCIDevice *dev);
769
770
771static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
772{
773 return &dev->bus_master_as;
774}
775
776static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
777 void *buf, dma_addr_t len, DMADirection dir)
778{
779 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
780 return 0;
781}
782
783static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
784 void *buf, dma_addr_t len)
785{
786 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
787}
788
789static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
790 const void *buf, dma_addr_t len)
791{
792 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
793}
794
795#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
796 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
797 dma_addr_t addr) \
798 { \
799 return ld##_l##_dma(pci_get_address_space(dev), addr); \
800 } \
801 static inline void st##_s##_pci_dma(PCIDevice *dev, \
802 dma_addr_t addr, uint##_bits##_t val) \
803 { \
804 st##_s##_dma(pci_get_address_space(dev), addr, val); \
805 }
806
807PCI_DMA_DEFINE_LDST(ub, b, 8);
808PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
809PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
810PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
811PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
812PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
813PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
814
815#undef PCI_DMA_DEFINE_LDST
816
817static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
818 dma_addr_t *plen, DMADirection dir)
819{
820 void *buf;
821
822 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
823 return buf;
824}
825
826static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
827 DMADirection dir, dma_addr_t access_len)
828{
829 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
830}
831
832static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
833 int alloc_hint)
834{
835 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
836}
837
838extern const VMStateDescription vmstate_pci_device;
839
840#define VMSTATE_PCI_DEVICE(_field, _state) { \
841 .name = (stringify(_field)), \
842 .size = sizeof(PCIDevice), \
843 .vmsd = &vmstate_pci_device, \
844 .flags = VMS_STRUCT, \
845 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
846}
847
848#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
849 .name = (stringify(_field)), \
850 .size = sizeof(PCIDevice), \
851 .vmsd = &vmstate_pci_device, \
852 .flags = VMS_STRUCT|VMS_POINTER, \
853 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
854}
855
856MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
857
858#endif
859