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19#ifndef _PPC_PNV_LPC_H
20#define _PPC_PNV_LPC_H
21
22#include "hw/ppc/pnv_psi.h"
23
24#define TYPE_PNV_LPC "pnv-lpc"
25#define PNV_LPC(obj) \
26 OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC)
27#define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8"
28#define PNV8_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV8_LPC)
29
30#define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9"
31#define PNV9_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV9_LPC)
32
33typedef struct PnvLpcController {
34 DeviceState parent;
35
36 uint64_t eccb_stat_reg;
37 uint32_t eccb_data_reg;
38
39
40 MemoryRegion opb_mr;
41 AddressSpace opb_as;
42
43
44 MemoryRegion isa_io;
45 MemoryRegion isa_mem;
46 MemoryRegion isa_fw;
47
48
49 MemoryRegion opb_isa_io;
50 MemoryRegion opb_isa_mem;
51 MemoryRegion opb_isa_fw;
52
53
54 MemoryRegion lpc_hc_regs;
55 MemoryRegion opb_master_regs;
56
57
58 uint32_t opb_irq_route0;
59 uint32_t opb_irq_route1;
60 uint32_t opb_irq_stat;
61 uint32_t opb_irq_mask;
62 uint32_t opb_irq_pol;
63 uint32_t opb_irq_input;
64
65
66 uint32_t lpc_hc_fw_seg_idsel;
67 uint32_t lpc_hc_fw_rd_acc_size;
68 uint32_t lpc_hc_irqser_ctrl;
69 uint32_t lpc_hc_irqmask;
70 uint32_t lpc_hc_irqstat;
71 uint32_t lpc_hc_error_addr;
72
73
74 MemoryRegion xscom_regs;
75
76
77 PnvPsi *psi;
78} PnvLpcController;
79
80#define PNV_LPC_CLASS(klass) \
81 OBJECT_CLASS_CHECK(PnvLpcClass, (klass), TYPE_PNV_LPC)
82#define PNV_LPC_GET_CLASS(obj) \
83 OBJECT_GET_CLASS(PnvLpcClass, (obj), TYPE_PNV_LPC)
84
85typedef struct PnvLpcClass {
86 DeviceClass parent_class;
87
88 int psi_irq;
89
90 DeviceRealize parent_realize;
91} PnvLpcClass;
92
93
94
95
96struct PnvChip;
97
98ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
99int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset);
100
101#endif
102