LXR qemu/include/hw/ppc/pnv

   1/*
   2 * QEMU PowerPC XIVE interrupt controller model
   3 *
   4 * Copyright (c) 2017-2019, IBM Corporation.
   5 *
   6 * This code is licensed under the GPL version 2 or later. See the
   7 * COPYING file in the top-level directory.
   8 */
   9
  10#ifndef PPC_PNV_XIVE_H
  11#define PPC_PNV_XIVE_H
  12
  13#include "hw/ppc/xive.h"
  14
  15struct PnvChip;
  16
  17#define TYPE_PNV_XIVE "pnv-xive"
  18#define PNV_XIVE(obj) OBJECT_CHECK(PnvXive, (obj), TYPE_PNV_XIVE)
  19
  20#define XIVE_BLOCK_MAX      16
  21
  22#define XIVE_TABLE_BLK_MAX  16  /* Block Scope Table (0-15) */
  23#define XIVE_TABLE_MIG_MAX  16  /* Migration Register Table (1-15) */
  24#define XIVE_TABLE_VDT_MAX  16  /* VDT Domain Table (0-15) */
  25#define XIVE_TABLE_EDT_MAX  64  /* EDT Domain Table (0-63) */
  26
  27typedef struct PnvXive {
  28    XiveRouter    parent_obj;
  29
  30    /* Owning chip */
  31    struct PnvChip *chip;
  32
  33    /* XSCOM addresses giving access to the controller registers */
  34    MemoryRegion  xscom_regs;
  35
  36    /* Main MMIO regions that can be configured by FW */
  37    MemoryRegion  ic_mmio;
  38    MemoryRegion    ic_reg_mmio;
  39    MemoryRegion    ic_notify_mmio;
  40    MemoryRegion    ic_lsi_mmio;
  41    MemoryRegion    tm_indirect_mmio;
  42    MemoryRegion  vc_mmio;
  43    MemoryRegion  pc_mmio;
  44    MemoryRegion  tm_mmio;
  45
  46    /*
  47     * IPI and END address spaces modeling the EDT segmentation in the
  48     * VC region
  49     */
  50    AddressSpace  ipi_as;
  51    MemoryRegion  ipi_mmio;
  52    MemoryRegion    ipi_edt_mmio;
  53
  54    AddressSpace  end_as;
  55    MemoryRegion  end_mmio;
  56    MemoryRegion    end_edt_mmio;
  57
  58    /* Shortcut values for the Main MMIO regions */
  59    hwaddr        ic_base;
  60    uint32_t      ic_shift;
  61    hwaddr        vc_base;
  62    uint32_t      vc_shift;
  63    hwaddr        pc_base;
  64    uint32_t      pc_shift;
  65    hwaddr        tm_base;
  66    uint32_t      tm_shift;
  67
  68    /* Our XIVE source objects for IPIs and ENDs */
  69    XiveSource    ipi_source;
  70    XiveENDSource end_source;
  71
  72    /* Interrupt controller registers */
  73    uint64_t      regs[0x300];
  74
  75    /* Can be configured by FW */
  76    uint32_t      tctx_chipid;
  77
  78    /*
  79     * Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
  80     * These are in a SRAM protected by ECC.
  81     */
  82    uint64_t      vsds[5][XIVE_BLOCK_MAX];
  83
  84    /* Translation tables */
  85    uint64_t      blk[XIVE_TABLE_BLK_MAX];
  86    uint64_t      mig[XIVE_TABLE_MIG_MAX];
  87    uint64_t      vdt[XIVE_TABLE_VDT_MAX];
  88    uint64_t      edt[XIVE_TABLE_EDT_MAX];
  89} PnvXive;
  90
  91void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon);
  92
  93#endif /* PPC_PNV_XIVE_H */
  94