1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef __ARM_KVM_H__
24#define __ARM_KVM_H__
25
26#define KVM_SPSR_EL1 0
27#define KVM_SPSR_SVC KVM_SPSR_EL1
28#define KVM_SPSR_ABT 1
29#define KVM_SPSR_UND 2
30#define KVM_SPSR_IRQ 3
31#define KVM_SPSR_FIQ 4
32#define KVM_NR_SPSR 5
33
34#ifndef __ASSEMBLY__
35#include <linux/psci.h>
36#include <linux/types.h>
37#include <asm/ptrace.h>
38
39#define __KVM_HAVE_GUEST_DEBUG
40#define __KVM_HAVE_IRQ_LINE
41#define __KVM_HAVE_READONLY_MEM
42#define __KVM_HAVE_VCPU_EVENTS
43
44#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
45
46#define KVM_REG_SIZE(id) \
47 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
48
49struct kvm_regs {
50 struct user_pt_regs regs;
51
52 __u64 sp_el1;
53 __u64 elr_el1;
54
55 __u64 spsr[KVM_NR_SPSR];
56
57 struct user_fpsimd_state fp_regs;
58};
59
60
61
62
63
64
65#define KVM_ARM_TARGET_AEM_V8 0
66#define KVM_ARM_TARGET_FOUNDATION_V8 1
67#define KVM_ARM_TARGET_CORTEX_A57 2
68#define KVM_ARM_TARGET_XGENE_POTENZA 3
69#define KVM_ARM_TARGET_CORTEX_A53 4
70
71#define KVM_ARM_TARGET_GENERIC_V8 5
72
73#define KVM_ARM_NUM_TARGETS 6
74
75
76#define KVM_ARM_DEVICE_TYPE_SHIFT 0
77#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
78#define KVM_ARM_DEVICE_ID_SHIFT 16
79#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
80
81
82#define KVM_ARM_DEVICE_VGIC_V2 0
83
84
85#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
86#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
87
88#define KVM_VGIC_V2_DIST_SIZE 0x1000
89#define KVM_VGIC_V2_CPU_SIZE 0x2000
90
91
92#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
93#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
94#define KVM_VGIC_ITS_ADDR_TYPE 4
95#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
96
97#define KVM_VGIC_V3_DIST_SIZE SZ_64K
98#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
99#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
100
101#define KVM_ARM_VCPU_POWER_OFF 0
102#define KVM_ARM_VCPU_EL1_32BIT 1
103#define KVM_ARM_VCPU_PSCI_0_2 2
104#define KVM_ARM_VCPU_PMU_V3 3
105
106struct kvm_vcpu_init {
107 __u32 target;
108 __u32 features[7];
109};
110
111struct kvm_sregs {
112};
113
114struct kvm_fpu {
115};
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130#define KVM_ARM_MAX_DBG_REGS 16
131struct kvm_guest_debug_arch {
132 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
133 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
134 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
135 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
136};
137
138struct kvm_debug_exit_arch {
139 __u32 hsr;
140 __u64 far;
141};
142
143
144
145
146
147#define KVM_GUESTDBG_USE_SW_BP (1 << 16)
148#define KVM_GUESTDBG_USE_HW (1 << 17)
149
150struct kvm_sync_regs {
151
152 __u64 device_irq_level;
153};
154
155struct kvm_arch_memory_slot {
156};
157
158
159struct kvm_vcpu_events {
160 struct {
161 __u8 serror_pending;
162 __u8 serror_has_esr;
163
164 __u8 pad[6];
165 __u64 serror_esr;
166 } exception;
167 __u32 reserved[12];
168};
169
170
171#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
172#define KVM_REG_ARM_COPROC_SHIFT 16
173
174
175#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
176#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
177
178
179#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
180#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
181#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
182#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
183#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
184#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
185
186
187#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
188#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
189#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
190#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
191#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
192#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
193#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
194#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
195#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
196#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
197#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
198
199#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
200 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
201 KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
202
203#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
204 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
205 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
206 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
207 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
208 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
209 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
210
211#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
212
213
214#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1)
215#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
216#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
217
218
219#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
220#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
221#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
222
223
224#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
225#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
226 KVM_REG_ARM_FW | ((r) & 0xffff))
227#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
228
229
230#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
231#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
232#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
233#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
234#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
235#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
236#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
237 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
238#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
239#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
240#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
241#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
242#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
243#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
244#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
245#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
246#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
247#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
248#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
249 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
250#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
251#define VGIC_LEVEL_INFO_LINE_LEVEL 0
252
253#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
254#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
255#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
256#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
257#define KVM_DEV_ARM_ITS_CTRL_RESET 4
258
259
260#define KVM_ARM_VCPU_PMU_V3_CTRL 0
261#define KVM_ARM_VCPU_PMU_V3_IRQ 0
262#define KVM_ARM_VCPU_PMU_V3_INIT 1
263#define KVM_ARM_VCPU_TIMER_CTRL 1
264#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
265#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
266
267
268#define KVM_ARM_IRQ_TYPE_SHIFT 24
269#define KVM_ARM_IRQ_TYPE_MASK 0xff
270#define KVM_ARM_IRQ_VCPU_SHIFT 16
271#define KVM_ARM_IRQ_VCPU_MASK 0xff
272#define KVM_ARM_IRQ_NUM_SHIFT 0
273#define KVM_ARM_IRQ_NUM_MASK 0xffff
274
275
276#define KVM_ARM_IRQ_TYPE_CPU 0
277#define KVM_ARM_IRQ_TYPE_SPI 1
278#define KVM_ARM_IRQ_TYPE_PPI 2
279
280
281#define KVM_ARM_IRQ_CPU_IRQ 0
282#define KVM_ARM_IRQ_CPU_FIQ 1
283
284
285
286
287
288
289#define KVM_ARM_IRQ_GIC_MAX 127
290
291
292#define KVM_NR_IRQCHIPS 1
293
294
295#define KVM_PSCI_FN_BASE 0x95c1ba5e
296#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
297
298#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
299#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
300#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
301#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
302
303#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
304#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
305#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
306#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
307
308#endif
309
310#endif
311