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11#include "qemu/osdep.h"
12#include <sys/ioctl.h>
13
14#include <linux/kvm.h>
15
16#include "qemu-common.h"
17#include "cpu.h"
18#include "qemu/timer.h"
19#include "sysemu/sysemu.h"
20#include "sysemu/kvm.h"
21#include "kvm_arm.h"
22#include "internals.h"
23#include "hw/arm/arm.h"
24#include "qemu/log.h"
25
26static inline void set_feature(uint64_t *features, int feature)
27{
28 *features |= 1ULL << feature;
29}
30
31static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
32{
33 struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
34
35 assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
36 return ioctl(fd, KVM_GET_ONE_REG, &idreg);
37}
38
39bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
40{
41
42
43
44
45
46 int err = 0, fdarray[3];
47 uint32_t midr, id_pfr0;
48 uint64_t features = 0;
49
50
51
52
53
54 static const uint32_t cpus_to_try[] = {
55 QEMU_KVM_ARM_TARGET_CORTEX_A15,
56 QEMU_KVM_ARM_TARGET_NONE
57 };
58 struct kvm_vcpu_init init;
59
60 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
61 return false;
62 }
63
64 ahcf->target = init.target;
65
66
67
68
69
70 ahcf->dtb_compatible = "arm,arm-v7";
71
72 err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
73 err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
74
75 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
76 ARM_CP15_REG32(0, 0, 2, 0));
77 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
78 ARM_CP15_REG32(0, 0, 2, 1));
79 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
80 ARM_CP15_REG32(0, 0, 2, 2));
81 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
82 ARM_CP15_REG32(0, 0, 2, 3));
83 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
84 ARM_CP15_REG32(0, 0, 2, 4));
85 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
86 ARM_CP15_REG32(0, 0, 2, 5));
87 if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
88 ARM_CP15_REG32(0, 0, 2, 7))) {
89
90
91
92
93
94 ahcf->isar.id_isar6 = 0;
95 }
96
97 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
98 KVM_REG_ARM | KVM_REG_SIZE_U32 |
99 KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
100 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
101 KVM_REG_ARM | KVM_REG_SIZE_U32 |
102 KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
103
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106
107
108 kvm_arm_destroy_scratch_host_vcpu(fdarray);
109
110 if (err < 0) {
111 return false;
112 }
113
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118
119
120
121 set_feature(&features, ARM_FEATURE_V7VE);
122 set_feature(&features, ARM_FEATURE_VFP3);
123 set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
124
125 if (extract32(id_pfr0, 12, 4) == 1) {
126 set_feature(&features, ARM_FEATURE_THUMB2EE);
127 }
128 if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
129 set_feature(&features, ARM_FEATURE_NEON);
130 }
131 if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
132
133 set_feature(&features, ARM_FEATURE_VFP4);
134 }
135
136 ahcf->features = features;
137
138 return true;
139}
140
141bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
142{
143
144
145
146
147 switch (regidx & KVM_REG_ARM_COPROC_MASK) {
148 case KVM_REG_ARM_CORE:
149 case KVM_REG_ARM_VFP:
150 return false;
151 default:
152 return true;
153 }
154}
155
156typedef struct CPRegStateLevel {
157 uint64_t regidx;
158 int level;
159} CPRegStateLevel;
160
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164
165
166static const CPRegStateLevel non_runtime_cpregs[] = {
167 { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
168};
169
170int kvm_arm_cpreg_level(uint64_t regidx)
171{
172 int i;
173
174 for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
175 const CPRegStateLevel *l = &non_runtime_cpregs[i];
176 if (l->regidx == regidx) {
177 return l->level;
178 }
179 }
180
181 return KVM_PUT_RUNTIME_STATE;
182}
183
184#define ARM_CPU_ID_MPIDR 0, 0, 0, 5
185
186int kvm_arch_init_vcpu(CPUState *cs)
187{
188 int ret;
189 uint64_t v;
190 uint32_t mpidr;
191 struct kvm_one_reg r;
192 ARMCPU *cpu = ARM_CPU(cs);
193
194 if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
195 fprintf(stderr, "KVM is not supported for this guest CPU type\n");
196 return -EINVAL;
197 }
198
199
200 memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
201 if (cpu->start_powered_off) {
202 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
203 }
204 if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
205 cpu->psci_version = 2;
206 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
207 }
208
209
210 ret = kvm_arm_vcpu_init(cs);
211 if (ret) {
212 return ret;
213 }
214
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219
220 r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
221 r.addr = (uintptr_t)(&v);
222 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
223 if (ret == -ENOENT) {
224 return -EINVAL;
225 }
226
227
228
229
230
231
232 ret = kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr);
233 if (ret) {
234 return ret;
235 }
236 cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
237
238
239 kvm_arm_init_serror_injection(cs);
240
241 return kvm_arm_init_cpreg_list(cpu);
242}
243
244typedef struct Reg {
245 uint64_t id;
246 int offset;
247} Reg;
248
249#define COREREG(KERNELNAME, QEMUFIELD) \
250 { \
251 KVM_REG_ARM | KVM_REG_SIZE_U32 | \
252 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
253 offsetof(CPUARMState, QEMUFIELD) \
254 }
255
256#define VFPSYSREG(R) \
257 { \
258 KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
259 KVM_REG_ARM_VFP_##R, \
260 offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \
261 }
262
263
264#define COREREG64(KERNELNAME, QEMUFIELD) \
265 { \
266 KVM_REG_ARM | KVM_REG_SIZE_U32 | \
267 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
268 offsetoflow32(CPUARMState, QEMUFIELD) \
269 }
270
271static const Reg regs[] = {
272
273 COREREG(usr_regs.uregs[0], regs[0]),
274 COREREG(usr_regs.uregs[1], regs[1]),
275 COREREG(usr_regs.uregs[2], regs[2]),
276 COREREG(usr_regs.uregs[3], regs[3]),
277 COREREG(usr_regs.uregs[4], regs[4]),
278 COREREG(usr_regs.uregs[5], regs[5]),
279 COREREG(usr_regs.uregs[6], regs[6]),
280 COREREG(usr_regs.uregs[7], regs[7]),
281 COREREG(usr_regs.uregs[8], usr_regs[0]),
282 COREREG(usr_regs.uregs[9], usr_regs[1]),
283 COREREG(usr_regs.uregs[10], usr_regs[2]),
284 COREREG(usr_regs.uregs[11], usr_regs[3]),
285 COREREG(usr_regs.uregs[12], usr_regs[4]),
286 COREREG(usr_regs.uregs[13], banked_r13[BANK_USRSYS]),
287 COREREG(usr_regs.uregs[14], banked_r14[BANK_USRSYS]),
288
289 COREREG(svc_regs[0], banked_r13[BANK_SVC]),
290 COREREG(svc_regs[1], banked_r14[BANK_SVC]),
291 COREREG64(svc_regs[2], banked_spsr[BANK_SVC]),
292 COREREG(abt_regs[0], banked_r13[BANK_ABT]),
293 COREREG(abt_regs[1], banked_r14[BANK_ABT]),
294 COREREG64(abt_regs[2], banked_spsr[BANK_ABT]),
295 COREREG(und_regs[0], banked_r13[BANK_UND]),
296 COREREG(und_regs[1], banked_r14[BANK_UND]),
297 COREREG64(und_regs[2], banked_spsr[BANK_UND]),
298 COREREG(irq_regs[0], banked_r13[BANK_IRQ]),
299 COREREG(irq_regs[1], banked_r14[BANK_IRQ]),
300 COREREG64(irq_regs[2], banked_spsr[BANK_IRQ]),
301
302 COREREG(fiq_regs[0], fiq_regs[0]),
303 COREREG(fiq_regs[1], fiq_regs[1]),
304 COREREG(fiq_regs[2], fiq_regs[2]),
305 COREREG(fiq_regs[3], fiq_regs[3]),
306 COREREG(fiq_regs[4], fiq_regs[4]),
307 COREREG(fiq_regs[5], banked_r13[BANK_FIQ]),
308 COREREG(fiq_regs[6], banked_r14[BANK_FIQ]),
309 COREREG64(fiq_regs[7], banked_spsr[BANK_FIQ]),
310
311 COREREG(usr_regs.uregs[15], regs[15]),
312
313 VFPSYSREG(FPSID),
314 VFPSYSREG(MVFR1),
315 VFPSYSREG(MVFR0),
316 VFPSYSREG(FPEXC),
317 VFPSYSREG(FPINST),
318 VFPSYSREG(FPINST2),
319};
320
321int kvm_arch_put_registers(CPUState *cs, int level)
322{
323 ARMCPU *cpu = ARM_CPU(cs);
324 CPUARMState *env = &cpu->env;
325 struct kvm_one_reg r;
326 int mode, bn;
327 int ret, i;
328 uint32_t cpsr, fpscr;
329
330
331 mode = env->uncached_cpsr & CPSR_M;
332 bn = bank_number(mode);
333 if (mode == ARM_CPU_MODE_FIQ) {
334 memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
335 } else {
336 memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
337 }
338 env->banked_r13[bn] = env->regs[13];
339 env->banked_spsr[bn] = env->spsr;
340 env->banked_r14[r14_bank_number(mode)] = env->regs[14];
341
342
343 for (i = 0; i < ARRAY_SIZE(regs); i++) {
344 r.id = regs[i].id;
345 r.addr = (uintptr_t)(env) + regs[i].offset;
346 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
347 if (ret) {
348 return ret;
349 }
350 }
351
352
353 cpsr = cpsr_read(env);
354 r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
355 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
356 r.addr = (uintptr_t)(&cpsr);
357 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
358 if (ret) {
359 return ret;
360 }
361
362
363 r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
364 for (i = 0; i < 32; i++) {
365 r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
366 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
367 if (ret) {
368 return ret;
369 }
370 r.id++;
371 }
372
373 r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
374 KVM_REG_ARM_VFP_FPSCR;
375 fpscr = vfp_get_fpscr(env);
376 r.addr = (uintptr_t)&fpscr;
377 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
378 if (ret) {
379 return ret;
380 }
381
382 ret = kvm_put_vcpu_events(cpu);
383 if (ret) {
384 return ret;
385 }
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404
405 if (!write_list_to_kvmstate(cpu, level)) {
406 return EINVAL;
407 }
408
409 kvm_arm_sync_mpstate_to_kvm(cpu);
410
411 return ret;
412}
413
414int kvm_arch_get_registers(CPUState *cs)
415{
416 ARMCPU *cpu = ARM_CPU(cs);
417 CPUARMState *env = &cpu->env;
418 struct kvm_one_reg r;
419 int mode, bn;
420 int ret, i;
421 uint32_t cpsr, fpscr;
422
423 for (i = 0; i < ARRAY_SIZE(regs); i++) {
424 r.id = regs[i].id;
425 r.addr = (uintptr_t)(env) + regs[i].offset;
426 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
427 if (ret) {
428 return ret;
429 }
430 }
431
432
433 r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
434 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
435 r.addr = (uintptr_t)(&cpsr);
436 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
437 if (ret) {
438 return ret;
439 }
440 cpsr_write(env, cpsr, 0xffffffff, CPSRWriteRaw);
441
442
443 mode = env->uncached_cpsr & CPSR_M;
444 bn = bank_number(mode);
445 if (mode == ARM_CPU_MODE_FIQ) {
446 memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
447 } else {
448 memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
449 }
450 env->regs[13] = env->banked_r13[bn];
451 env->spsr = env->banked_spsr[bn];
452 env->regs[14] = env->banked_r14[r14_bank_number(mode)];
453
454
455 r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
456 for (i = 0; i < 32; i++) {
457 r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
458 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
459 if (ret) {
460 return ret;
461 }
462 r.id++;
463 }
464
465 r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
466 KVM_REG_ARM_VFP_FPSCR;
467 r.addr = (uintptr_t)&fpscr;
468 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
469 if (ret) {
470 return ret;
471 }
472 vfp_set_fpscr(env, fpscr);
473
474 ret = kvm_get_vcpu_events(cpu);
475 if (ret) {
476 return ret;
477 }
478
479 if (!write_kvmstate_to_list(cpu)) {
480 return EINVAL;
481 }
482
483
484
485 write_list_to_cpustate(cpu);
486
487 kvm_arm_sync_mpstate_to_qemu(cpu);
488
489 return 0;
490}
491
492int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
493{
494 qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
495 return -EINVAL;
496}
497
498int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
499{
500 qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
501 return -EINVAL;
502}
503
504bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
505{
506 qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
507 return false;
508}
509
510int kvm_arch_insert_hw_breakpoint(target_ulong addr,
511 target_ulong len, int type)
512{
513 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
514 return -EINVAL;
515}
516
517int kvm_arch_remove_hw_breakpoint(target_ulong addr,
518 target_ulong len, int type)
519{
520 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
521 return -EINVAL;
522}
523
524void kvm_arch_remove_all_hw_breakpoints(void)
525{
526 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
527}
528
529void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
530{
531 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
532}
533
534bool kvm_arm_hw_debug_active(CPUState *cs)
535{
536 return false;
537}
538
539void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
540{
541 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
542}
543
544void kvm_arm_pmu_init(CPUState *cs)
545{
546 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
547}
548