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21#ifndef I386_CPU_H
22#define I386_CPU_H
23
24#include "qemu-common.h"
25#include "cpu-qom.h"
26#include "hyperv-proto.h"
27
28#ifdef TARGET_X86_64
29#define TARGET_LONG_BITS 64
30#else
31#define TARGET_LONG_BITS 32
32#endif
33
34#include "exec/cpu-defs.h"
35
36
37#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
38
39
40#define TARGET_MAX_INSN_SIZE 16
41
42
43
44#define TARGET_HAS_PRECISE_SMC
45
46#ifdef TARGET_X86_64
47#define I386_ELF_MACHINE EM_X86_64
48#define ELF_MACHINE_UNAME "x86_64"
49#else
50#define I386_ELF_MACHINE EM_386
51#define ELF_MACHINE_UNAME "i686"
52#endif
53
54#define CPUArchState struct CPUX86State
55
56enum {
57 R_EAX = 0,
58 R_ECX = 1,
59 R_EDX = 2,
60 R_EBX = 3,
61 R_ESP = 4,
62 R_EBP = 5,
63 R_ESI = 6,
64 R_EDI = 7,
65 R_R8 = 8,
66 R_R9 = 9,
67 R_R10 = 10,
68 R_R11 = 11,
69 R_R12 = 12,
70 R_R13 = 13,
71 R_R14 = 14,
72 R_R15 = 15,
73
74 R_AL = 0,
75 R_CL = 1,
76 R_DL = 2,
77 R_BL = 3,
78 R_AH = 4,
79 R_CH = 5,
80 R_DH = 6,
81 R_BH = 7,
82};
83
84typedef enum X86Seg {
85 R_ES = 0,
86 R_CS = 1,
87 R_SS = 2,
88 R_DS = 3,
89 R_FS = 4,
90 R_GS = 5,
91 R_LDTR = 6,
92 R_TR = 7,
93} X86Seg;
94
95
96#define DESC_G_SHIFT 23
97#define DESC_G_MASK (1 << DESC_G_SHIFT)
98#define DESC_B_SHIFT 22
99#define DESC_B_MASK (1 << DESC_B_SHIFT)
100#define DESC_L_SHIFT 21
101#define DESC_L_MASK (1 << DESC_L_SHIFT)
102#define DESC_AVL_SHIFT 20
103#define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
104#define DESC_P_SHIFT 15
105#define DESC_P_MASK (1 << DESC_P_SHIFT)
106#define DESC_DPL_SHIFT 13
107#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
108#define DESC_S_SHIFT 12
109#define DESC_S_MASK (1 << DESC_S_SHIFT)
110#define DESC_TYPE_SHIFT 8
111#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
112#define DESC_A_MASK (1 << 8)
113
114#define DESC_CS_MASK (1 << 11)
115#define DESC_C_MASK (1 << 10)
116#define DESC_R_MASK (1 << 9)
117
118#define DESC_E_MASK (1 << 10)
119#define DESC_W_MASK (1 << 9)
120
121#define DESC_TSS_BUSY_MASK (1 << 9)
122
123
124#define CC_C 0x0001
125#define CC_P 0x0004
126#define CC_A 0x0010
127#define CC_Z 0x0040
128#define CC_S 0x0080
129#define CC_O 0x0800
130
131#define TF_SHIFT 8
132#define IOPL_SHIFT 12
133#define VM_SHIFT 17
134
135#define TF_MASK 0x00000100
136#define IF_MASK 0x00000200
137#define DF_MASK 0x00000400
138#define IOPL_MASK 0x00003000
139#define NT_MASK 0x00004000
140#define RF_MASK 0x00010000
141#define VM_MASK 0x00020000
142#define AC_MASK 0x00040000
143#define VIF_MASK 0x00080000
144#define VIP_MASK 0x00100000
145#define ID_MASK 0x00200000
146
147
148
149
150
151
152#define HF_CPL_SHIFT 0
153
154#define HF_INHIBIT_IRQ_SHIFT 3
155
156#define HF_CS32_SHIFT 4
157#define HF_SS32_SHIFT 5
158
159#define HF_ADDSEG_SHIFT 6
160
161#define HF_PE_SHIFT 7
162#define HF_TF_SHIFT 8
163#define HF_MP_SHIFT 9
164#define HF_EM_SHIFT 10
165#define HF_TS_SHIFT 11
166#define HF_IOPL_SHIFT 12
167#define HF_LMA_SHIFT 14
168#define HF_CS64_SHIFT 15
169#define HF_RF_SHIFT 16
170#define HF_VM_SHIFT 17
171#define HF_AC_SHIFT 18
172#define HF_SMM_SHIFT 19
173#define HF_SVME_SHIFT 20
174#define HF_GUEST_SHIFT 21
175#define HF_OSFXSR_SHIFT 22
176#define HF_SMAP_SHIFT 23
177#define HF_IOBPT_SHIFT 24
178#define HF_MPX_EN_SHIFT 25
179#define HF_MPX_IU_SHIFT 26
180
181#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
182#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
183#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
184#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
185#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
186#define HF_PE_MASK (1 << HF_PE_SHIFT)
187#define HF_TF_MASK (1 << HF_TF_SHIFT)
188#define HF_MP_MASK (1 << HF_MP_SHIFT)
189#define HF_EM_MASK (1 << HF_EM_SHIFT)
190#define HF_TS_MASK (1 << HF_TS_SHIFT)
191#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
192#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
193#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
194#define HF_RF_MASK (1 << HF_RF_SHIFT)
195#define HF_VM_MASK (1 << HF_VM_SHIFT)
196#define HF_AC_MASK (1 << HF_AC_SHIFT)
197#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
198#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
199#define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
200#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
201#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
202#define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
203#define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
204#define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
205
206
207
208#define HF2_GIF_SHIFT 0
209#define HF2_HIF_SHIFT 1
210#define HF2_NMI_SHIFT 2
211#define HF2_VINTR_SHIFT 3
212#define HF2_SMM_INSIDE_NMI_SHIFT 4
213#define HF2_MPX_PR_SHIFT 5
214#define HF2_NPT_SHIFT 6
215
216#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
217#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
218#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
219#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
220#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
221#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
222#define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
223
224#define CR0_PE_SHIFT 0
225#define CR0_MP_SHIFT 1
226
227#define CR0_PE_MASK (1U << 0)
228#define CR0_MP_MASK (1U << 1)
229#define CR0_EM_MASK (1U << 2)
230#define CR0_TS_MASK (1U << 3)
231#define CR0_ET_MASK (1U << 4)
232#define CR0_NE_MASK (1U << 5)
233#define CR0_WP_MASK (1U << 16)
234#define CR0_AM_MASK (1U << 18)
235#define CR0_PG_MASK (1U << 31)
236
237#define CR4_VME_MASK (1U << 0)
238#define CR4_PVI_MASK (1U << 1)
239#define CR4_TSD_MASK (1U << 2)
240#define CR4_DE_MASK (1U << 3)
241#define CR4_PSE_MASK (1U << 4)
242#define CR4_PAE_MASK (1U << 5)
243#define CR4_MCE_MASK (1U << 6)
244#define CR4_PGE_MASK (1U << 7)
245#define CR4_PCE_MASK (1U << 8)
246#define CR4_OSFXSR_SHIFT 9
247#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
248#define CR4_OSXMMEXCPT_MASK (1U << 10)
249#define CR4_LA57_MASK (1U << 12)
250#define CR4_VMXE_MASK (1U << 13)
251#define CR4_SMXE_MASK (1U << 14)
252#define CR4_FSGSBASE_MASK (1U << 16)
253#define CR4_PCIDE_MASK (1U << 17)
254#define CR4_OSXSAVE_MASK (1U << 18)
255#define CR4_SMEP_MASK (1U << 20)
256#define CR4_SMAP_MASK (1U << 21)
257#define CR4_PKE_MASK (1U << 22)
258
259#define DR6_BD (1 << 13)
260#define DR6_BS (1 << 14)
261#define DR6_BT (1 << 15)
262#define DR6_FIXED_1 0xffff0ff0
263
264#define DR7_GD (1 << 13)
265#define DR7_TYPE_SHIFT 16
266#define DR7_LEN_SHIFT 18
267#define DR7_FIXED_1 0x00000400
268#define DR7_GLOBAL_BP_MASK 0xaa
269#define DR7_LOCAL_BP_MASK 0x55
270#define DR7_MAX_BP 4
271#define DR7_TYPE_BP_INST 0x0
272#define DR7_TYPE_DATA_WR 0x1
273#define DR7_TYPE_IO_RW 0x2
274#define DR7_TYPE_DATA_RW 0x3
275
276#define PG_PRESENT_BIT 0
277#define PG_RW_BIT 1
278#define PG_USER_BIT 2
279#define PG_PWT_BIT 3
280#define PG_PCD_BIT 4
281#define PG_ACCESSED_BIT 5
282#define PG_DIRTY_BIT 6
283#define PG_PSE_BIT 7
284#define PG_GLOBAL_BIT 8
285#define PG_PSE_PAT_BIT 12
286#define PG_PKRU_BIT 59
287#define PG_NX_BIT 63
288
289#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
290#define PG_RW_MASK (1 << PG_RW_BIT)
291#define PG_USER_MASK (1 << PG_USER_BIT)
292#define PG_PWT_MASK (1 << PG_PWT_BIT)
293#define PG_PCD_MASK (1 << PG_PCD_BIT)
294#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
295#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
296#define PG_PSE_MASK (1 << PG_PSE_BIT)
297#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
298#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
299#define PG_ADDRESS_MASK 0x000ffffffffff000LL
300#define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
301#define PG_HI_USER_MASK 0x7ff0000000000000LL
302#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
303#define PG_NX_MASK (1ULL << PG_NX_BIT)
304
305#define PG_ERROR_W_BIT 1
306
307#define PG_ERROR_P_MASK 0x01
308#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
309#define PG_ERROR_U_MASK 0x04
310#define PG_ERROR_RSVD_MASK 0x08
311#define PG_ERROR_I_D_MASK 0x10
312#define PG_ERROR_PK_MASK 0x20
313
314#define MCG_CTL_P (1ULL<<8)
315#define MCG_SER_P (1ULL<<24)
316#define MCG_LMCE_P (1ULL<<27)
317
318#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
319#define MCE_BANKS_DEF 10
320
321#define MCG_CAP_BANKS_MASK 0xff
322
323#define MCG_STATUS_RIPV (1ULL<<0)
324#define MCG_STATUS_EIPV (1ULL<<1)
325#define MCG_STATUS_MCIP (1ULL<<2)
326#define MCG_STATUS_LMCE (1ULL<<3)
327
328#define MCG_EXT_CTL_LMCE_EN (1ULL<<0)
329
330#define MCI_STATUS_VAL (1ULL<<63)
331#define MCI_STATUS_OVER (1ULL<<62)
332#define MCI_STATUS_UC (1ULL<<61)
333#define MCI_STATUS_EN (1ULL<<60)
334#define MCI_STATUS_MISCV (1ULL<<59)
335#define MCI_STATUS_ADDRV (1ULL<<58)
336#define MCI_STATUS_PCC (1ULL<<57)
337#define MCI_STATUS_S (1ULL<<56)
338#define MCI_STATUS_AR (1ULL<<55)
339
340
341#define MCM_ADDR_SEGOFF 0
342#define MCM_ADDR_LINEAR 1
343#define MCM_ADDR_PHYS 2
344#define MCM_ADDR_MEM 3
345#define MCM_ADDR_GENERIC 7
346
347#define MSR_IA32_TSC 0x10
348#define MSR_IA32_APICBASE 0x1b
349#define MSR_IA32_APICBASE_BSP (1<<8)
350#define MSR_IA32_APICBASE_ENABLE (1<<11)
351#define MSR_IA32_APICBASE_EXTD (1 << 10)
352#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
353#define MSR_IA32_FEATURE_CONTROL 0x0000003a
354#define MSR_TSC_ADJUST 0x0000003b
355#define MSR_IA32_SPEC_CTRL 0x48
356#define MSR_VIRT_SSBD 0xc001011f
357#define MSR_IA32_PRED_CMD 0x49
358#define MSR_IA32_ARCH_CAPABILITIES 0x10a
359#define MSR_IA32_TSCDEADLINE 0x6e0
360
361#define FEATURE_CONTROL_LOCKED (1<<0)
362#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
363#define FEATURE_CONTROL_LMCE (1<<20)
364
365#define MSR_P6_PERFCTR0 0xc1
366
367#define MSR_IA32_SMBASE 0x9e
368#define MSR_SMI_COUNT 0x34
369#define MSR_MTRRcap 0xfe
370#define MSR_MTRRcap_VCNT 8
371#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
372#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
373
374#define MSR_IA32_SYSENTER_CS 0x174
375#define MSR_IA32_SYSENTER_ESP 0x175
376#define MSR_IA32_SYSENTER_EIP 0x176
377
378#define MSR_MCG_CAP 0x179
379#define MSR_MCG_STATUS 0x17a
380#define MSR_MCG_CTL 0x17b
381#define MSR_MCG_EXT_CTL 0x4d0
382
383#define MSR_P6_EVNTSEL0 0x186
384
385#define MSR_IA32_PERF_STATUS 0x198
386
387#define MSR_IA32_MISC_ENABLE 0x1a0
388
389#define MSR_IA32_MISC_ENABLE_DEFAULT 1
390
391#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
392#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
393
394#define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
395
396#define MSR_MTRRfix64K_00000 0x250
397#define MSR_MTRRfix16K_80000 0x258
398#define MSR_MTRRfix16K_A0000 0x259
399#define MSR_MTRRfix4K_C0000 0x268
400#define MSR_MTRRfix4K_C8000 0x269
401#define MSR_MTRRfix4K_D0000 0x26a
402#define MSR_MTRRfix4K_D8000 0x26b
403#define MSR_MTRRfix4K_E0000 0x26c
404#define MSR_MTRRfix4K_E8000 0x26d
405#define MSR_MTRRfix4K_F0000 0x26e
406#define MSR_MTRRfix4K_F8000 0x26f
407
408#define MSR_PAT 0x277
409
410#define MSR_MTRRdefType 0x2ff
411
412#define MSR_CORE_PERF_FIXED_CTR0 0x309
413#define MSR_CORE_PERF_FIXED_CTR1 0x30a
414#define MSR_CORE_PERF_FIXED_CTR2 0x30b
415#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
416#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
417#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
418#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
419
420#define MSR_MC0_CTL 0x400
421#define MSR_MC0_STATUS 0x401
422#define MSR_MC0_ADDR 0x402
423#define MSR_MC0_MISC 0x403
424
425#define MSR_IA32_RTIT_OUTPUT_BASE 0x560
426#define MSR_IA32_RTIT_OUTPUT_MASK 0x561
427#define MSR_IA32_RTIT_CTL 0x570
428#define MSR_IA32_RTIT_STATUS 0x571
429#define MSR_IA32_RTIT_CR3_MATCH 0x572
430#define MSR_IA32_RTIT_ADDR0_A 0x580
431#define MSR_IA32_RTIT_ADDR0_B 0x581
432#define MSR_IA32_RTIT_ADDR1_A 0x582
433#define MSR_IA32_RTIT_ADDR1_B 0x583
434#define MSR_IA32_RTIT_ADDR2_A 0x584
435#define MSR_IA32_RTIT_ADDR2_B 0x585
436#define MSR_IA32_RTIT_ADDR3_A 0x586
437#define MSR_IA32_RTIT_ADDR3_B 0x587
438#define MAX_RTIT_ADDRS 8
439
440#define MSR_EFER 0xc0000080
441
442#define MSR_EFER_SCE (1 << 0)
443#define MSR_EFER_LME (1 << 8)
444#define MSR_EFER_LMA (1 << 10)
445#define MSR_EFER_NXE (1 << 11)
446#define MSR_EFER_SVME (1 << 12)
447#define MSR_EFER_FFXSR (1 << 14)
448
449#define MSR_STAR 0xc0000081
450#define MSR_LSTAR 0xc0000082
451#define MSR_CSTAR 0xc0000083
452#define MSR_FMASK 0xc0000084
453#define MSR_FSBASE 0xc0000100
454#define MSR_GSBASE 0xc0000101
455#define MSR_KERNELGSBASE 0xc0000102
456#define MSR_TSC_AUX 0xc0000103
457
458#define MSR_VM_HSAVE_PA 0xc0010117
459
460#define MSR_IA32_BNDCFGS 0x00000d90
461#define MSR_IA32_XSS 0x00000da0
462
463#define XSTATE_FP_BIT 0
464#define XSTATE_SSE_BIT 1
465#define XSTATE_YMM_BIT 2
466#define XSTATE_BNDREGS_BIT 3
467#define XSTATE_BNDCSR_BIT 4
468#define XSTATE_OPMASK_BIT 5
469#define XSTATE_ZMM_Hi256_BIT 6
470#define XSTATE_Hi16_ZMM_BIT 7
471#define XSTATE_PKRU_BIT 9
472
473#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
474#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
475#define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
476#define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
477#define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
478#define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
479#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
480#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
481#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
482
483
484typedef enum FeatureWord {
485 FEAT_1_EDX,
486 FEAT_1_ECX,
487 FEAT_7_0_EBX,
488 FEAT_7_0_ECX,
489 FEAT_7_0_EDX,
490 FEAT_8000_0001_EDX,
491 FEAT_8000_0001_ECX,
492 FEAT_8000_0007_EDX,
493 FEAT_8000_0008_EBX,
494 FEAT_C000_0001_EDX,
495 FEAT_KVM,
496 FEAT_KVM_HINTS,
497 FEAT_HYPERV_EAX,
498 FEAT_HYPERV_EBX,
499 FEAT_HYPERV_EDX,
500 FEAT_HV_RECOMM_EAX,
501 FEAT_HV_NESTED_EAX,
502 FEAT_SVM,
503 FEAT_XSAVE,
504 FEAT_6_EAX,
505 FEAT_XSAVE_COMP_LO,
506 FEAT_XSAVE_COMP_HI,
507 FEAT_ARCH_CAPABILITIES,
508 FEATURE_WORDS,
509} FeatureWord;
510
511typedef uint32_t FeatureWordArray[FEATURE_WORDS];
512
513
514#define CPUID_FP87 (1U << 0)
515#define CPUID_VME (1U << 1)
516#define CPUID_DE (1U << 2)
517#define CPUID_PSE (1U << 3)
518#define CPUID_TSC (1U << 4)
519#define CPUID_MSR (1U << 5)
520#define CPUID_PAE (1U << 6)
521#define CPUID_MCE (1U << 7)
522#define CPUID_CX8 (1U << 8)
523#define CPUID_APIC (1U << 9)
524#define CPUID_SEP (1U << 11)
525#define CPUID_MTRR (1U << 12)
526#define CPUID_PGE (1U << 13)
527#define CPUID_MCA (1U << 14)
528#define CPUID_CMOV (1U << 15)
529#define CPUID_PAT (1U << 16)
530#define CPUID_PSE36 (1U << 17)
531#define CPUID_PN (1U << 18)
532#define CPUID_CLFLUSH (1U << 19)
533#define CPUID_DTS (1U << 21)
534#define CPUID_ACPI (1U << 22)
535#define CPUID_MMX (1U << 23)
536#define CPUID_FXSR (1U << 24)
537#define CPUID_SSE (1U << 25)
538#define CPUID_SSE2 (1U << 26)
539#define CPUID_SS (1U << 27)
540#define CPUID_HT (1U << 28)
541#define CPUID_TM (1U << 29)
542#define CPUID_IA64 (1U << 30)
543#define CPUID_PBE (1U << 31)
544
545#define CPUID_EXT_SSE3 (1U << 0)
546#define CPUID_EXT_PCLMULQDQ (1U << 1)
547#define CPUID_EXT_DTES64 (1U << 2)
548#define CPUID_EXT_MONITOR (1U << 3)
549#define CPUID_EXT_DSCPL (1U << 4)
550#define CPUID_EXT_VMX (1U << 5)
551#define CPUID_EXT_SMX (1U << 6)
552#define CPUID_EXT_EST (1U << 7)
553#define CPUID_EXT_TM2 (1U << 8)
554#define CPUID_EXT_SSSE3 (1U << 9)
555#define CPUID_EXT_CID (1U << 10)
556#define CPUID_EXT_FMA (1U << 12)
557#define CPUID_EXT_CX16 (1U << 13)
558#define CPUID_EXT_XTPR (1U << 14)
559#define CPUID_EXT_PDCM (1U << 15)
560#define CPUID_EXT_PCID (1U << 17)
561#define CPUID_EXT_DCA (1U << 18)
562#define CPUID_EXT_SSE41 (1U << 19)
563#define CPUID_EXT_SSE42 (1U << 20)
564#define CPUID_EXT_X2APIC (1U << 21)
565#define CPUID_EXT_MOVBE (1U << 22)
566#define CPUID_EXT_POPCNT (1U << 23)
567#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
568#define CPUID_EXT_AES (1U << 25)
569#define CPUID_EXT_XSAVE (1U << 26)
570#define CPUID_EXT_OSXSAVE (1U << 27)
571#define CPUID_EXT_AVX (1U << 28)
572#define CPUID_EXT_F16C (1U << 29)
573#define CPUID_EXT_RDRAND (1U << 30)
574#define CPUID_EXT_HYPERVISOR (1U << 31)
575
576#define CPUID_EXT2_FPU (1U << 0)
577#define CPUID_EXT2_VME (1U << 1)
578#define CPUID_EXT2_DE (1U << 2)
579#define CPUID_EXT2_PSE (1U << 3)
580#define CPUID_EXT2_TSC (1U << 4)
581#define CPUID_EXT2_MSR (1U << 5)
582#define CPUID_EXT2_PAE (1U << 6)
583#define CPUID_EXT2_MCE (1U << 7)
584#define CPUID_EXT2_CX8 (1U << 8)
585#define CPUID_EXT2_APIC (1U << 9)
586#define CPUID_EXT2_SYSCALL (1U << 11)
587#define CPUID_EXT2_MTRR (1U << 12)
588#define CPUID_EXT2_PGE (1U << 13)
589#define CPUID_EXT2_MCA (1U << 14)
590#define CPUID_EXT2_CMOV (1U << 15)
591#define CPUID_EXT2_PAT (1U << 16)
592#define CPUID_EXT2_PSE36 (1U << 17)
593#define CPUID_EXT2_MP (1U << 19)
594#define CPUID_EXT2_NX (1U << 20)
595#define CPUID_EXT2_MMXEXT (1U << 22)
596#define CPUID_EXT2_MMX (1U << 23)
597#define CPUID_EXT2_FXSR (1U << 24)
598#define CPUID_EXT2_FFXSR (1U << 25)
599#define CPUID_EXT2_PDPE1GB (1U << 26)
600#define CPUID_EXT2_RDTSCP (1U << 27)
601#define CPUID_EXT2_LM (1U << 29)
602#define CPUID_EXT2_3DNOWEXT (1U << 30)
603#define CPUID_EXT2_3DNOW (1U << 31)
604
605
606#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
607 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
608 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
609 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
610 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
611 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
612 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
613 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
614 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
615
616#define CPUID_EXT3_LAHF_LM (1U << 0)
617#define CPUID_EXT3_CMP_LEG (1U << 1)
618#define CPUID_EXT3_SVM (1U << 2)
619#define CPUID_EXT3_EXTAPIC (1U << 3)
620#define CPUID_EXT3_CR8LEG (1U << 4)
621#define CPUID_EXT3_ABM (1U << 5)
622#define CPUID_EXT3_SSE4A (1U << 6)
623#define CPUID_EXT3_MISALIGNSSE (1U << 7)
624#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
625#define CPUID_EXT3_OSVW (1U << 9)
626#define CPUID_EXT3_IBS (1U << 10)
627#define CPUID_EXT3_XOP (1U << 11)
628#define CPUID_EXT3_SKINIT (1U << 12)
629#define CPUID_EXT3_WDT (1U << 13)
630#define CPUID_EXT3_LWP (1U << 15)
631#define CPUID_EXT3_FMA4 (1U << 16)
632#define CPUID_EXT3_TCE (1U << 17)
633#define CPUID_EXT3_NODEID (1U << 19)
634#define CPUID_EXT3_TBM (1U << 21)
635#define CPUID_EXT3_TOPOEXT (1U << 22)
636#define CPUID_EXT3_PERFCORE (1U << 23)
637#define CPUID_EXT3_PERFNB (1U << 24)
638
639#define CPUID_SVM_NPT (1U << 0)
640#define CPUID_SVM_LBRV (1U << 1)
641#define CPUID_SVM_SVMLOCK (1U << 2)
642#define CPUID_SVM_NRIPSAVE (1U << 3)
643#define CPUID_SVM_TSCSCALE (1U << 4)
644#define CPUID_SVM_VMCBCLEAN (1U << 5)
645#define CPUID_SVM_FLUSHASID (1U << 6)
646#define CPUID_SVM_DECODEASSIST (1U << 7)
647#define CPUID_SVM_PAUSEFILTER (1U << 10)
648#define CPUID_SVM_PFTHRESHOLD (1U << 12)
649
650#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
651#define CPUID_7_0_EBX_BMI1 (1U << 3)
652#define CPUID_7_0_EBX_HLE (1U << 4)
653#define CPUID_7_0_EBX_AVX2 (1U << 5)
654#define CPUID_7_0_EBX_SMEP (1U << 7)
655#define CPUID_7_0_EBX_BMI2 (1U << 8)
656#define CPUID_7_0_EBX_ERMS (1U << 9)
657#define CPUID_7_0_EBX_INVPCID (1U << 10)
658#define CPUID_7_0_EBX_RTM (1U << 11)
659#define CPUID_7_0_EBX_MPX (1U << 14)
660#define CPUID_7_0_EBX_AVX512F (1U << 16)
661#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
662#define CPUID_7_0_EBX_RDSEED (1U << 18)
663#define CPUID_7_0_EBX_ADX (1U << 19)
664#define CPUID_7_0_EBX_SMAP (1U << 20)
665#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
666#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
667#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
668#define CPUID_7_0_EBX_CLWB (1U << 24)
669#define CPUID_7_0_EBX_INTEL_PT (1U << 25)
670#define CPUID_7_0_EBX_AVX512PF (1U << 26)
671#define CPUID_7_0_EBX_AVX512ER (1U << 27)
672#define CPUID_7_0_EBX_AVX512CD (1U << 28)
673#define CPUID_7_0_EBX_SHA_NI (1U << 29)
674#define CPUID_7_0_EBX_AVX512BW (1U << 30)
675#define CPUID_7_0_EBX_AVX512VL (1U << 31)
676
677#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
678#define CPUID_7_0_ECX_VBMI (1U << 1)
679#define CPUID_7_0_ECX_UMIP (1U << 2)
680#define CPUID_7_0_ECX_PKU (1U << 3)
681#define CPUID_7_0_ECX_OSPKE (1U << 4)
682#define CPUID_7_0_ECX_VBMI2 (1U << 6)
683#define CPUID_7_0_ECX_GFNI (1U << 8)
684#define CPUID_7_0_ECX_VAES (1U << 9)
685#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
686#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
687#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
688#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
689#define CPUID_7_0_ECX_LA57 (1U << 16)
690#define CPUID_7_0_ECX_RDPID (1U << 22)
691#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
692#define CPUID_7_0_ECX_MOVDIRI (1U << 27)
693#define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
694
695#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
696#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
697#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
698#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
699#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
700
701#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
702
703#define CPUID_8000_0008_EBX_IBPB (1U << 12)
704
705#define CPUID_XSAVE_XSAVEOPT (1U << 0)
706#define CPUID_XSAVE_XSAVEC (1U << 1)
707#define CPUID_XSAVE_XGETBV1 (1U << 2)
708#define CPUID_XSAVE_XSAVES (1U << 3)
709
710#define CPUID_6_EAX_ARAT (1U << 2)
711
712
713#define CPUID_APM_INVTSC (1U << 8)
714
715#define CPUID_VENDOR_SZ 12
716
717#define CPUID_VENDOR_INTEL_1 0x756e6547
718#define CPUID_VENDOR_INTEL_2 0x49656e69
719#define CPUID_VENDOR_INTEL_3 0x6c65746e
720#define CPUID_VENDOR_INTEL "GenuineIntel"
721
722#define CPUID_VENDOR_AMD_1 0x68747541
723#define CPUID_VENDOR_AMD_2 0x69746e65
724#define CPUID_VENDOR_AMD_3 0x444d4163
725#define CPUID_VENDOR_AMD "AuthenticAMD"
726
727#define CPUID_VENDOR_VIA "CentaurHauls"
728
729#define CPUID_MWAIT_IBE (1U << 1)
730#define CPUID_MWAIT_EMX (1U << 0)
731
732
733#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
734#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
735#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
736
737
738#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
739#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
740#define MSR_ARCH_CAP_RSBA (1U << 2)
741#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
742#define MSR_ARCH_CAP_SSB_NO (1U << 4)
743
744#ifndef HYPERV_SPINLOCK_NEVER_RETRY
745#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
746#endif
747
748#define EXCP00_DIVZ 0
749#define EXCP01_DB 1
750#define EXCP02_NMI 2
751#define EXCP03_INT3 3
752#define EXCP04_INTO 4
753#define EXCP05_BOUND 5
754#define EXCP06_ILLOP 6
755#define EXCP07_PREX 7
756#define EXCP08_DBLE 8
757#define EXCP09_XERR 9
758#define EXCP0A_TSS 10
759#define EXCP0B_NOSEG 11
760#define EXCP0C_STACK 12
761#define EXCP0D_GPF 13
762#define EXCP0E_PAGE 14
763#define EXCP10_COPR 16
764#define EXCP11_ALGN 17
765#define EXCP12_MCHK 18
766
767#define EXCP_SYSCALL 0x100
768
769#define EXCP_VMEXIT 0x100
770
771
772#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
773#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
774#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
775#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
776#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
777#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
778#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
779
780
781#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
782
783
784
785
786
787
788
789
790typedef enum {
791 CC_OP_DYNAMIC,
792 CC_OP_EFLAGS,
793
794 CC_OP_MULB,
795 CC_OP_MULW,
796 CC_OP_MULL,
797 CC_OP_MULQ,
798
799 CC_OP_ADDB,
800 CC_OP_ADDW,
801 CC_OP_ADDL,
802 CC_OP_ADDQ,
803
804 CC_OP_ADCB,
805 CC_OP_ADCW,
806 CC_OP_ADCL,
807 CC_OP_ADCQ,
808
809 CC_OP_SUBB,
810 CC_OP_SUBW,
811 CC_OP_SUBL,
812 CC_OP_SUBQ,
813
814 CC_OP_SBBB,
815 CC_OP_SBBW,
816 CC_OP_SBBL,
817 CC_OP_SBBQ,
818
819 CC_OP_LOGICB,
820 CC_OP_LOGICW,
821 CC_OP_LOGICL,
822 CC_OP_LOGICQ,
823
824 CC_OP_INCB,
825 CC_OP_INCW,
826 CC_OP_INCL,
827 CC_OP_INCQ,
828
829 CC_OP_DECB,
830 CC_OP_DECW,
831 CC_OP_DECL,
832 CC_OP_DECQ,
833
834 CC_OP_SHLB,
835 CC_OP_SHLW,
836 CC_OP_SHLL,
837 CC_OP_SHLQ,
838
839 CC_OP_SARB,
840 CC_OP_SARW,
841 CC_OP_SARL,
842 CC_OP_SARQ,
843
844 CC_OP_BMILGB,
845 CC_OP_BMILGW,
846 CC_OP_BMILGL,
847 CC_OP_BMILGQ,
848
849 CC_OP_ADCX,
850 CC_OP_ADOX,
851 CC_OP_ADCOX,
852
853 CC_OP_CLR,
854 CC_OP_POPCNT,
855
856 CC_OP_NB,
857} CCOp;
858
859typedef struct SegmentCache {
860 uint32_t selector;
861 target_ulong base;
862 uint32_t limit;
863 uint32_t flags;
864} SegmentCache;
865
866#define MMREG_UNION(n, bits) \
867 union n { \
868 uint8_t _b_##n[(bits)/8]; \
869 uint16_t _w_##n[(bits)/16]; \
870 uint32_t _l_##n[(bits)/32]; \
871 uint64_t _q_##n[(bits)/64]; \
872 float32 _s_##n[(bits)/32]; \
873 float64 _d_##n[(bits)/64]; \
874 }
875
876typedef union {
877 uint8_t _b[16];
878 uint16_t _w[8];
879 uint32_t _l[4];
880 uint64_t _q[2];
881} XMMReg;
882
883typedef union {
884 uint8_t _b[32];
885 uint16_t _w[16];
886 uint32_t _l[8];
887 uint64_t _q[4];
888} YMMReg;
889
890typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
891typedef MMREG_UNION(MMXReg, 64) MMXReg;
892
893typedef struct BNDReg {
894 uint64_t lb;
895 uint64_t ub;
896} BNDReg;
897
898typedef struct BNDCSReg {
899 uint64_t cfgu;
900 uint64_t sts;
901} BNDCSReg;
902
903#define BNDCFG_ENABLE 1ULL
904#define BNDCFG_BNDPRESERVE 2ULL
905#define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
906
907#ifdef HOST_WORDS_BIGENDIAN
908#define ZMM_B(n) _b_ZMMReg[63 - (n)]
909#define ZMM_W(n) _w_ZMMReg[31 - (n)]
910#define ZMM_L(n) _l_ZMMReg[15 - (n)]
911#define ZMM_S(n) _s_ZMMReg[15 - (n)]
912#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
913#define ZMM_D(n) _d_ZMMReg[7 - (n)]
914
915#define MMX_B(n) _b_MMXReg[7 - (n)]
916#define MMX_W(n) _w_MMXReg[3 - (n)]
917#define MMX_L(n) _l_MMXReg[1 - (n)]
918#define MMX_S(n) _s_MMXReg[1 - (n)]
919#else
920#define ZMM_B(n) _b_ZMMReg[n]
921#define ZMM_W(n) _w_ZMMReg[n]
922#define ZMM_L(n) _l_ZMMReg[n]
923#define ZMM_S(n) _s_ZMMReg[n]
924#define ZMM_Q(n) _q_ZMMReg[n]
925#define ZMM_D(n) _d_ZMMReg[n]
926
927#define MMX_B(n) _b_MMXReg[n]
928#define MMX_W(n) _w_MMXReg[n]
929#define MMX_L(n) _l_MMXReg[n]
930#define MMX_S(n) _s_MMXReg[n]
931#endif
932#define MMX_Q(n) _q_MMXReg[n]
933
934typedef union {
935 floatx80 d __attribute__((aligned(16)));
936 MMXReg mmx;
937} FPReg;
938
939typedef struct {
940 uint64_t base;
941 uint64_t mask;
942} MTRRVar;
943
944#define CPU_NB_REGS64 16
945#define CPU_NB_REGS32 8
946
947#ifdef TARGET_X86_64
948#define CPU_NB_REGS CPU_NB_REGS64
949#else
950#define CPU_NB_REGS CPU_NB_REGS32
951#endif
952
953#define MAX_FIXED_COUNTERS 3
954#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
955
956#define NB_MMU_MODES 3
957#define TARGET_INSN_START_EXTRA_WORDS 1
958
959#define NB_OPMASK_REGS 8
960
961
962
963
964#define UNASSIGNED_APIC_ID 0xFFFFFFFF
965
966typedef union X86LegacyXSaveArea {
967 struct {
968 uint16_t fcw;
969 uint16_t fsw;
970 uint8_t ftw;
971 uint8_t reserved;
972 uint16_t fpop;
973 uint64_t fpip;
974 uint64_t fpdp;
975 uint32_t mxcsr;
976 uint32_t mxcsr_mask;
977 FPReg fpregs[8];
978 uint8_t xmm_regs[16][16];
979 };
980 uint8_t data[512];
981} X86LegacyXSaveArea;
982
983typedef struct X86XSaveHeader {
984 uint64_t xstate_bv;
985 uint64_t xcomp_bv;
986 uint64_t reserve0;
987 uint8_t reserved[40];
988} X86XSaveHeader;
989
990
991typedef struct XSaveAVX {
992 uint8_t ymmh[16][16];
993} XSaveAVX;
994
995
996typedef struct XSaveBNDREG {
997 BNDReg bnd_regs[4];
998} XSaveBNDREG;
999
1000
1001typedef union XSaveBNDCSR {
1002 BNDCSReg bndcsr;
1003 uint8_t data[64];
1004} XSaveBNDCSR;
1005
1006
1007typedef struct XSaveOpmask {
1008 uint64_t opmask_regs[NB_OPMASK_REGS];
1009} XSaveOpmask;
1010
1011
1012typedef struct XSaveZMM_Hi256 {
1013 uint8_t zmm_hi256[16][32];
1014} XSaveZMM_Hi256;
1015
1016
1017typedef struct XSaveHi16_ZMM {
1018 uint8_t hi16_zmm[16][64];
1019} XSaveHi16_ZMM;
1020
1021
1022typedef struct XSavePKRU {
1023 uint32_t pkru;
1024 uint32_t padding;
1025} XSavePKRU;
1026
1027typedef struct X86XSaveArea {
1028 X86LegacyXSaveArea legacy;
1029 X86XSaveHeader header;
1030
1031
1032
1033
1034 XSaveAVX avx_state;
1035 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
1036
1037 XSaveBNDREG bndreg_state;
1038 XSaveBNDCSR bndcsr_state;
1039
1040 XSaveOpmask opmask_state;
1041 XSaveZMM_Hi256 zmm_hi256_state;
1042 XSaveHi16_ZMM hi16_zmm_state;
1043
1044 XSavePKRU pkru_state;
1045} X86XSaveArea;
1046
1047QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
1048QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1049QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
1050QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1051QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
1052QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1053QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
1054QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1055QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
1056QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1057QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
1058QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1059QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
1060QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1061
1062typedef enum TPRAccess {
1063 TPR_ACCESS_READ,
1064 TPR_ACCESS_WRITE,
1065} TPRAccess;
1066
1067
1068
1069enum CacheType {
1070 DATA_CACHE,
1071 INSTRUCTION_CACHE,
1072 UNIFIED_CACHE
1073};
1074
1075typedef struct CPUCacheInfo {
1076 enum CacheType type;
1077 uint8_t level;
1078
1079 uint32_t size;
1080
1081 uint16_t line_size;
1082
1083
1084
1085
1086 uint8_t associativity;
1087
1088 uint8_t partitions;
1089
1090 uint32_t sets;
1091
1092
1093
1094
1095
1096 uint8_t lines_per_tag;
1097
1098
1099 bool self_init;
1100
1101
1102
1103
1104
1105 bool no_invd_sharing;
1106
1107
1108
1109
1110 bool inclusive;
1111
1112
1113
1114
1115 bool complex_indexing;
1116} CPUCacheInfo;
1117
1118
1119typedef struct CPUCaches {
1120 CPUCacheInfo *l1d_cache;
1121 CPUCacheInfo *l1i_cache;
1122 CPUCacheInfo *l2_cache;
1123 CPUCacheInfo *l3_cache;
1124} CPUCaches;
1125
1126typedef struct CPUX86State {
1127
1128 target_ulong regs[CPU_NB_REGS];
1129 target_ulong eip;
1130 target_ulong eflags;
1131
1132
1133
1134
1135 target_ulong cc_dst;
1136 target_ulong cc_src;
1137 target_ulong cc_src2;
1138 uint32_t cc_op;
1139 int32_t df;
1140 uint32_t hflags;
1141
1142 uint32_t hflags2;
1143
1144
1145 SegmentCache segs[6];
1146 SegmentCache ldt;
1147 SegmentCache tr;
1148 SegmentCache gdt;
1149 SegmentCache idt;
1150
1151 target_ulong cr[5];
1152 int32_t a20_mask;
1153
1154 BNDReg bnd_regs[4];
1155 BNDCSReg bndcs_regs;
1156 uint64_t msr_bndcfgs;
1157 uint64_t efer;
1158
1159
1160 struct {} start_init_save;
1161
1162
1163 unsigned int fpstt;
1164 uint16_t fpus;
1165 uint16_t fpuc;
1166 uint8_t fptags[8];
1167 FPReg fpregs[8];
1168
1169 uint16_t fpop;
1170 uint64_t fpip;
1171 uint64_t fpdp;
1172
1173
1174 float_status fp_status;
1175 floatx80 ft0;
1176
1177 float_status mmx_status;
1178 float_status sse_status;
1179 uint32_t mxcsr;
1180 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1181 ZMMReg xmm_t0;
1182 MMXReg mmx_t0;
1183
1184 XMMReg ymmh_regs[CPU_NB_REGS];
1185
1186 uint64_t opmask_regs[NB_OPMASK_REGS];
1187 YMMReg zmmh_regs[CPU_NB_REGS];
1188 ZMMReg hi16_zmm_regs[CPU_NB_REGS];
1189
1190
1191 uint32_t sysenter_cs;
1192 target_ulong sysenter_esp;
1193 target_ulong sysenter_eip;
1194 uint64_t star;
1195
1196 uint64_t vm_hsave;
1197
1198#ifdef TARGET_X86_64
1199 target_ulong lstar;
1200 target_ulong cstar;
1201 target_ulong fmask;
1202 target_ulong kernelgsbase;
1203#endif
1204
1205 uint64_t tsc;
1206 uint64_t tsc_adjust;
1207 uint64_t tsc_deadline;
1208 uint64_t tsc_aux;
1209
1210 uint64_t xcr0;
1211
1212 uint64_t mcg_status;
1213 uint64_t msr_ia32_misc_enable;
1214 uint64_t msr_ia32_feature_control;
1215
1216 uint64_t msr_fixed_ctr_ctrl;
1217 uint64_t msr_global_ctrl;
1218 uint64_t msr_global_status;
1219 uint64_t msr_global_ovf_ctrl;
1220 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1221 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1222 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1223
1224 uint64_t pat;
1225 uint32_t smbase;
1226 uint64_t msr_smi_count;
1227
1228 uint32_t pkru;
1229
1230 uint64_t spec_ctrl;
1231 uint64_t virt_ssbd;
1232
1233
1234 struct {} end_init_save;
1235
1236 uint64_t system_time_msr;
1237 uint64_t wall_clock_msr;
1238 uint64_t steal_time_msr;
1239 uint64_t async_pf_en_msr;
1240 uint64_t pv_eoi_en_msr;
1241
1242
1243 uint64_t msr_hv_hypercall;
1244 uint64_t msr_hv_guest_os_id;
1245 uint64_t msr_hv_tsc;
1246
1247
1248 uint64_t msr_hv_vapic;
1249 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1250 uint64_t msr_hv_runtime;
1251 uint64_t msr_hv_synic_control;
1252 uint64_t msr_hv_synic_evt_page;
1253 uint64_t msr_hv_synic_msg_page;
1254 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1255 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1256 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1257 uint64_t msr_hv_reenlightenment_control;
1258 uint64_t msr_hv_tsc_emulation_control;
1259 uint64_t msr_hv_tsc_emulation_status;
1260
1261 uint64_t msr_rtit_ctrl;
1262 uint64_t msr_rtit_status;
1263 uint64_t msr_rtit_output_base;
1264 uint64_t msr_rtit_output_mask;
1265 uint64_t msr_rtit_cr3_match;
1266 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1267
1268
1269 int error_code;
1270 int exception_is_int;
1271 target_ulong exception_next_eip;
1272 target_ulong dr[8];
1273 union {
1274 struct CPUBreakpoint *cpu_breakpoint[4];
1275 struct CPUWatchpoint *cpu_watchpoint[4];
1276 };
1277 int old_exception;
1278
1279 uint64_t vm_vmcb;
1280 uint64_t tsc_offset;
1281 uint64_t intercept;
1282 uint16_t intercept_cr_read;
1283 uint16_t intercept_cr_write;
1284 uint16_t intercept_dr_read;
1285 uint16_t intercept_dr_write;
1286 uint32_t intercept_exceptions;
1287 uint64_t nested_cr3;
1288 uint32_t nested_pg_mode;
1289 uint8_t v_tpr;
1290
1291
1292 uint8_t nmi_injected;
1293 uint8_t nmi_pending;
1294
1295 uintptr_t retaddr;
1296
1297
1298 struct {} end_reset_fields;
1299
1300 CPU_COMMON
1301
1302
1303
1304
1305
1306 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1307
1308 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1309
1310 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1311 uint32_t cpuid_vendor1;
1312 uint32_t cpuid_vendor2;
1313 uint32_t cpuid_vendor3;
1314 uint32_t cpuid_version;
1315 FeatureWordArray features;
1316
1317 FeatureWordArray user_features;
1318 uint32_t cpuid_model[12];
1319
1320
1321
1322
1323 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1324
1325
1326 uint64_t mtrr_fixed[11];
1327 uint64_t mtrr_deftype;
1328 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1329
1330
1331 uint32_t mp_state;
1332 int32_t exception_injected;
1333 int32_t interrupt_injected;
1334 uint8_t soft_interrupt;
1335 uint8_t has_error_code;
1336 uint32_t ins_len;
1337 uint32_t sipi_vector;
1338 bool tsc_valid;
1339 int64_t tsc_khz;
1340 int64_t user_tsc_khz;
1341#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1342 void *xsave_buf;
1343#endif
1344#if defined(CONFIG_HVF)
1345 HVFX86EmulatorState *hvf_emul;
1346#endif
1347
1348 uint64_t mcg_cap;
1349 uint64_t mcg_ctl;
1350 uint64_t mcg_ext_ctl;
1351 uint64_t mce_banks[MCE_BANKS_DEF*4];
1352 uint64_t xstate_bv;
1353
1354
1355 uint16_t fpus_vmstate;
1356 uint16_t fptag_vmstate;
1357 uint16_t fpregs_format_vmstate;
1358
1359 uint64_t xss;
1360
1361 TPRAccess tpr_access_type;
1362} CPUX86State;
1363
1364struct kvm_msrs;
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375struct X86CPU {
1376
1377 CPUState parent_obj;
1378
1379
1380 CPUX86State env;
1381
1382 bool hyperv_vapic;
1383 bool hyperv_relaxed_timing;
1384 int hyperv_spinlock_attempts;
1385 char *hyperv_vendor_id;
1386 bool hyperv_time;
1387 bool hyperv_crash;
1388 bool hyperv_reset;
1389 bool hyperv_vpindex;
1390 bool hyperv_runtime;
1391 bool hyperv_synic;
1392 bool hyperv_synic_kvm_only;
1393 bool hyperv_stimer;
1394 bool hyperv_frequencies;
1395 bool hyperv_reenlightenment;
1396 bool hyperv_tlbflush;
1397 bool hyperv_evmcs;
1398 bool hyperv_ipi;
1399 bool check_cpuid;
1400 bool enforce_cpuid;
1401 bool expose_kvm;
1402 bool expose_tcg;
1403 bool migratable;
1404 bool migrate_smi_count;
1405 bool max_features;
1406 uint32_t apic_id;
1407
1408
1409
1410 bool vmware_cpuid_freq;
1411
1412
1413 bool cache_info_passthrough;
1414
1415
1416
1417 struct {
1418 uint32_t eax;
1419 uint32_t ebx;
1420 uint32_t ecx;
1421 uint32_t edx;
1422 } mwait;
1423
1424
1425 uint32_t filtered_features[FEATURE_WORDS];
1426
1427
1428
1429
1430
1431
1432 bool enable_pmu;
1433
1434
1435
1436
1437
1438 bool enable_lmce;
1439
1440
1441
1442
1443
1444 bool enable_l3_cache;
1445
1446
1447
1448
1449 bool legacy_cache;
1450
1451
1452 bool enable_cpuid_0xb;
1453
1454
1455 bool full_cpuid_auto_level;
1456
1457
1458 bool intel_pt_auto_level;
1459
1460
1461 bool fill_mtrr_mask;
1462
1463
1464 bool host_phys_bits;
1465
1466
1467 uint8_t host_phys_bits_limit;
1468
1469
1470 bool kvm_no_smi_migration;
1471
1472
1473 uint32_t phys_bits;
1474
1475
1476
1477 struct DeviceState *apic_state;
1478 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1479 Notifier machine_done;
1480
1481 struct kvm_msrs *kvm_msr_buf;
1482
1483 int32_t node_id;
1484 int32_t socket_id;
1485 int32_t core_id;
1486 int32_t thread_id;
1487
1488 int32_t hv_max_vps;
1489};
1490
1491static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
1492{
1493 return container_of(env, X86CPU, env);
1494}
1495
1496#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
1497
1498#define ENV_OFFSET offsetof(X86CPU, env)
1499
1500#ifndef CONFIG_USER_ONLY
1501extern struct VMStateDescription vmstate_x86_cpu;
1502#endif
1503
1504
1505
1506
1507
1508void x86_cpu_do_interrupt(CPUState *cpu);
1509bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1510int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
1511
1512int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1513 int cpuid, void *opaque);
1514int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1515 int cpuid, void *opaque);
1516int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1517 void *opaque);
1518int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1519 void *opaque);
1520
1521void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1522 Error **errp);
1523
1524void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1525 int flags);
1526
1527hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1528
1529int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1530int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1531
1532void x86_cpu_exec_enter(CPUState *cpu);
1533void x86_cpu_exec_exit(CPUState *cpu);
1534
1535void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1536int cpu_x86_support_mca_broadcast(CPUX86State *env);
1537
1538int cpu_get_pic_interrupt(CPUX86State *s);
1539
1540void cpu_set_ferr(CPUX86State *s);
1541
1542void cpu_sync_bndcs_hflags(CPUX86State *env);
1543
1544
1545
1546static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1547 int seg_reg, unsigned int selector,
1548 target_ulong base,
1549 unsigned int limit,
1550 unsigned int flags)
1551{
1552 SegmentCache *sc;
1553 unsigned int new_hflags;
1554
1555 sc = &env->segs[seg_reg];
1556 sc->selector = selector;
1557 sc->base = base;
1558 sc->limit = limit;
1559 sc->flags = flags;
1560
1561
1562 {
1563 if (seg_reg == R_CS) {
1564#ifdef TARGET_X86_64
1565 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1566
1567 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1568 env->hflags &= ~(HF_ADDSEG_MASK);
1569 } else
1570#endif
1571 {
1572
1573 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1574 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1575 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1576 new_hflags;
1577 }
1578 }
1579 if (seg_reg == R_SS) {
1580 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1581#if HF_CPL_MASK != 3
1582#error HF_CPL_MASK is hardcoded
1583#endif
1584 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1585
1586 cpu_sync_bndcs_hflags(env);
1587 }
1588 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1589 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1590 if (env->hflags & HF_CS64_MASK) {
1591
1592 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1593 (env->eflags & VM_MASK) ||
1594 !(env->hflags & HF_CS32_MASK)) {
1595
1596
1597
1598
1599
1600 new_hflags |= HF_ADDSEG_MASK;
1601 } else {
1602 new_hflags |= ((env->segs[R_DS].base |
1603 env->segs[R_ES].base |
1604 env->segs[R_SS].base) != 0) <<
1605 HF_ADDSEG_SHIFT;
1606 }
1607 env->hflags = (env->hflags &
1608 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1609 }
1610}
1611
1612static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1613 uint8_t sipi_vector)
1614{
1615 CPUState *cs = CPU(cpu);
1616 CPUX86State *env = &cpu->env;
1617
1618 env->eip = 0;
1619 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1620 sipi_vector << 12,
1621 env->segs[R_CS].limit,
1622 env->segs[R_CS].flags);
1623 cs->halted = 0;
1624}
1625
1626int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1627 target_ulong *base, unsigned int *limit,
1628 unsigned int *flags);
1629
1630
1631
1632
1633
1634
1635
1636void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1637void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1638void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1639void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
1640void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
1641
1642
1643
1644
1645int cpu_x86_signal_handler(int host_signum, void *pinfo,
1646 void *puc);
1647
1648
1649void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1650 uint32_t *eax, uint32_t *ebx,
1651 uint32_t *ecx, uint32_t *edx);
1652void cpu_clear_apic_feature(CPUX86State *env);
1653void host_cpuid(uint32_t function, uint32_t count,
1654 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1655void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
1656
1657
1658int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size,
1659 int is_write, int mmu_idx);
1660void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1661
1662#ifndef CONFIG_USER_ONLY
1663static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
1664{
1665 return !!attrs.secure;
1666}
1667
1668static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
1669{
1670 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
1671}
1672
1673uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1674uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1675uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1676uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1677void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1678void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1679void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1680void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1681void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1682#endif
1683
1684void breakpoint_handler(CPUState *cs);
1685
1686
1687void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1688void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1689void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1690void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1691
1692
1693uint64_t cpu_get_tsc(CPUX86State *env);
1694
1695#define TARGET_PAGE_BITS 12
1696
1697#ifdef TARGET_X86_64
1698#define TARGET_PHYS_ADDR_SPACE_BITS 52
1699
1700
1701
1702#define TARGET_VIRT_ADDR_SPACE_BITS 47
1703#else
1704#define TARGET_PHYS_ADDR_SPACE_BITS 36
1705#define TARGET_VIRT_ADDR_SPACE_BITS 32
1706#endif
1707
1708
1709
1710# if defined(TARGET_X86_64)
1711# define TCG_PHYS_ADDR_BITS 40
1712# else
1713# define TCG_PHYS_ADDR_BITS 36
1714# endif
1715
1716#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1717
1718#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
1719#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
1720#define CPU_RESOLVING_TYPE TYPE_X86_CPU
1721
1722#ifdef TARGET_X86_64
1723#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
1724#else
1725#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
1726#endif
1727
1728#define cpu_signal_handler cpu_x86_signal_handler
1729#define cpu_list x86_cpu_list
1730
1731
1732#define MMU_MODE0_SUFFIX _ksmap
1733#define MMU_MODE1_SUFFIX _user
1734#define MMU_MODE2_SUFFIX _knosmap
1735#define MMU_KSMAP_IDX 0
1736#define MMU_USER_IDX 1
1737#define MMU_KNOSMAP_IDX 2
1738static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1739{
1740 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1741 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1742 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1743}
1744
1745static inline int cpu_mmu_index_kernel(CPUX86State *env)
1746{
1747 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1748 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1749 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1750}
1751
1752#define CC_DST (env->cc_dst)
1753#define CC_SRC (env->cc_src)
1754#define CC_SRC2 (env->cc_src2)
1755#define CC_OP (env->cc_op)
1756
1757
1758static inline target_long lshift(target_long x, int n)
1759{
1760 if (n >= 0) {
1761 return x << n;
1762 } else {
1763 return x >> (-n);
1764 }
1765}
1766
1767
1768#define FT0 (env->ft0)
1769#define ST0 (env->fpregs[env->fpstt].d)
1770#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1771#define ST1 ST(1)
1772
1773
1774void tcg_x86_init(void);
1775
1776#include "exec/cpu-all.h"
1777#include "svm.h"
1778
1779#if !defined(CONFIG_USER_ONLY)
1780#include "hw/i386/apic.h"
1781#endif
1782
1783static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1784 target_ulong *cs_base, uint32_t *flags)
1785{
1786 *cs_base = env->segs[R_CS].base;
1787 *pc = *cs_base + env->eip;
1788 *flags = env->hflags |
1789 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1790}
1791
1792void do_cpu_init(X86CPU *cpu);
1793void do_cpu_sipi(X86CPU *cpu);
1794
1795#define MCE_INJECT_BROADCAST 1
1796#define MCE_INJECT_UNCOND_AO 2
1797
1798void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1799 uint64_t status, uint64_t mcg_status, uint64_t addr,
1800 uint64_t misc, int flags);
1801
1802
1803void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1804void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
1805 uintptr_t retaddr);
1806void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1807 int error_code);
1808void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
1809 int error_code, uintptr_t retaddr);
1810void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1811 int error_code, int next_eip_addend);
1812
1813
1814extern const uint8_t parity_table[256];
1815uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1816
1817static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1818{
1819 uint32_t eflags = env->eflags;
1820 if (tcg_enabled()) {
1821 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1822 }
1823 return eflags;
1824}
1825
1826
1827
1828
1829static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1830 int update_mask)
1831{
1832 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1833 CC_OP = CC_OP_EFLAGS;
1834 env->df = 1 - (2 * ((eflags >> 10) & 1));
1835 env->eflags = (env->eflags & ~update_mask) |
1836 (eflags & update_mask) | 0x2;
1837}
1838
1839
1840
1841static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1842{
1843 env->efer = val;
1844 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1845 if (env->efer & MSR_EFER_LMA) {
1846 env->hflags |= HF_LMA_MASK;
1847 }
1848 if (env->efer & MSR_EFER_SVME) {
1849 env->hflags |= HF_SVME_MASK;
1850 }
1851}
1852
1853static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
1854{
1855 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
1856}
1857
1858static inline int32_t x86_get_a20_mask(CPUX86State *env)
1859{
1860 if (env->hflags & HF_SMM_MASK) {
1861 return -1;
1862 } else {
1863 return env->a20_mask;
1864 }
1865}
1866
1867
1868void update_fp_status(CPUX86State *env);
1869void update_mxcsr_status(CPUX86State *env);
1870
1871static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
1872{
1873 env->mxcsr = mxcsr;
1874 if (tcg_enabled()) {
1875 update_mxcsr_status(env);
1876 }
1877}
1878
1879static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
1880{
1881 env->fpuc = fpuc;
1882 if (tcg_enabled()) {
1883 update_fp_status(env);
1884 }
1885}
1886
1887
1888void helper_lock_init(void);
1889
1890
1891void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1892 uint64_t param, uintptr_t retaddr);
1893void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
1894 uint64_t exit_info_1, uintptr_t retaddr);
1895void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
1896
1897
1898void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1899
1900
1901void do_smm_enter(X86CPU *cpu);
1902
1903
1904void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1905void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
1906 TPRAccess access);
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917void x86_cpu_change_kvm_default(const char *prop, const char *value);
1918
1919
1920const char *get_register_name_32(unsigned int reg);
1921
1922void enable_compat_apic_id_mode(void);
1923
1924#define APIC_DEFAULT_ADDRESS 0xfee00000
1925#define APIC_SPACE_SIZE 0x100000
1926
1927void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f,
1928 fprintf_function cpu_fprintf, int flags);
1929
1930
1931bool cpu_is_bsp(X86CPU *cpu);
1932
1933void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
1934void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
1935void x86_update_hflags(CPUX86State* env);
1936
1937#endif
1938