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21#ifndef M68K_CPU_H
22#define M68K_CPU_H
23
24#define TARGET_LONG_BITS 32
25
26#define CPUArchState struct CPUM68KState
27
28#include "qemu-common.h"
29#include "exec/cpu-defs.h"
30#include "cpu-qom.h"
31
32#define OS_BYTE 0
33#define OS_WORD 1
34#define OS_LONG 2
35#define OS_SINGLE 3
36#define OS_DOUBLE 4
37#define OS_EXTENDED 5
38#define OS_PACKED 6
39#define OS_UNSIZED 7
40
41#define MAX_QREGS 32
42
43#define EXCP_ACCESS 2
44#define EXCP_ADDRESS 3
45#define EXCP_ILLEGAL 4
46#define EXCP_DIV0 5
47#define EXCP_CHK 6
48#define EXCP_TRAPCC 7
49#define EXCP_PRIVILEGE 8
50#define EXCP_TRACE 9
51#define EXCP_LINEA 10
52#define EXCP_LINEF 11
53#define EXCP_DEBUGNBP 12
54#define EXCP_DEBEGBP 13
55#define EXCP_FORMAT 14
56#define EXCP_UNINITIALIZED 15
57#define EXCP_SPURIOUS 24
58#define EXCP_INT_LEVEL_1 25
59#define EXCP_INT_LEVEL_7 31
60#define EXCP_TRAP0 32
61#define EXCP_TRAP15 47
62#define EXCP_FP_BSUN 48
63#define EXCP_FP_INEX 49
64#define EXCP_FP_DZ 50
65#define EXCP_FP_UNFL 51
66#define EXCP_FP_OPERR 52
67#define EXCP_FP_OVFL 53
68#define EXCP_FP_SNAN 54
69#define EXCP_FP_UNIMP 55
70#define EXCP_MMU_CONF 56
71#define EXCP_MMU_ILLEGAL 57
72#define EXCP_MMU_ACCESS 58
73
74#define EXCP_RTE 0x100
75#define EXCP_HALT_INSN 0x101
76
77#define M68K_DTTR0 0
78#define M68K_DTTR1 1
79#define M68K_ITTR0 2
80#define M68K_ITTR1 3
81
82#define M68K_MAX_TTR 2
83#define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
84
85#define NB_MMU_MODES 2
86#define TARGET_INSN_START_EXTRA_WORDS 1
87
88typedef CPU_LDoubleU FPReg;
89
90typedef struct CPUM68KState {
91 uint32_t dregs[8];
92 uint32_t aregs[8];
93 uint32_t pc;
94 uint32_t sr;
95
96
97 int current_sp;
98 uint32_t sp[3];
99
100
101 uint32_t cc_op;
102 uint32_t cc_x;
103 uint32_t cc_n;
104 uint32_t cc_v;
105 uint32_t cc_c;
106 uint32_t cc_z;
107
108 FPReg fregs[8];
109 FPReg fp_result;
110 uint32_t fpcr;
111 uint32_t fpsr;
112 float_status fp_status;
113
114 uint64_t mactmp;
115
116
117
118 uint64_t macc[4];
119 uint32_t macsr;
120 uint32_t mac_mask;
121
122
123 struct {
124 uint32_t ar;
125 uint32_t ssw;
126
127 uint16_t tcr;
128 uint32_t urp;
129 uint32_t srp;
130 bool fault;
131 uint32_t ttr[4];
132 uint32_t mmusr;
133 } mmu;
134
135
136 uint32_t vbr;
137 uint32_t mbar;
138 uint32_t rambar0;
139 uint32_t cacr;
140 uint32_t sfc;
141 uint32_t dfc;
142
143 int pending_vector;
144 int pending_level;
145
146 uint32_t qregs[MAX_QREGS];
147
148
149 struct {} end_reset_fields;
150
151 CPU_COMMON
152
153
154 uint32_t features;
155} CPUM68KState;
156
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161
162
163struct M68kCPU {
164
165 CPUState parent_obj;
166
167
168 CPUM68KState env;
169};
170
171static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
172{
173 return container_of(env, M68kCPU, env);
174}
175
176#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
177
178#define ENV_OFFSET offsetof(M68kCPU, env)
179
180void m68k_cpu_do_interrupt(CPUState *cpu);
181bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
182void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
183 int flags);
184hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
185int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
186int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
187
188void m68k_tcg_init(void);
189void m68k_cpu_init_gdb(M68kCPU *cpu);
190
191
192
193int cpu_m68k_signal_handler(int host_signum, void *pinfo,
194 void *puc);
195uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
196void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
197void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);
198void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);
199
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205
206
207
208typedef enum {
209
210 CC_OP_DYNAMIC,
211
212
213 CC_OP_FLAGS,
214
215
216 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
217 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
218
219
220 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
221
222
223 CC_OP_LOGIC,
224
225 CC_OP_NB
226} CCOp;
227
228#define CCF_C 0x01
229#define CCF_V 0x02
230#define CCF_Z 0x04
231#define CCF_N 0x08
232#define CCF_X 0x10
233
234#define SR_I_SHIFT 8
235#define SR_I 0x0700
236#define SR_M 0x1000
237#define SR_S 0x2000
238#define SR_T_SHIFT 14
239#define SR_T 0xc000
240
241#define M68K_SSP 0
242#define M68K_USP 1
243#define M68K_ISP 2
244
245
246#define M68K_CP_040 0x8000
247#define M68K_CU_040 0x4000
248#define M68K_CT_040 0x2000
249#define M68K_CM_040 0x1000
250#define M68K_MA_040 0x0800
251#define M68K_ATC_040 0x0400
252#define M68K_LK_040 0x0200
253#define M68K_RW_040 0x0100
254#define M68K_SIZ_040 0x0060
255#define M68K_TT_040 0x0018
256#define M68K_TM_040 0x0007
257
258#define M68K_TM_040_DATA 0x0001
259#define M68K_TM_040_CODE 0x0002
260#define M68K_TM_040_SUPER 0x0004
261
262
263#define M68K_WBV_040 0x80
264#define M68K_WBSIZ_040 0x60
265#define M68K_WBBYT_040 0x20
266#define M68K_WBWRD_040 0x40
267#define M68K_WBLNG_040 0x00
268#define M68K_WBTT_040 0x18
269#define M68K_WBTM_040 0x07
270
271
272#define M68K_BA_SIZE_MASK 0x60
273#define M68K_BA_SIZE_BYTE 0x20
274#define M68K_BA_SIZE_WORD 0x40
275#define M68K_BA_SIZE_LONG 0x00
276#define M68K_BA_SIZE_LINE 0x60
277
278
279#define M68K_BA_TT_MOVE16 0x08
280
281
282#define M68K_MMU_B_040 0x0800
283#define M68K_MMU_G_040 0x0400
284#define M68K_MMU_U1_040 0x0200
285#define M68K_MMU_U0_040 0x0100
286#define M68K_MMU_S_040 0x0080
287#define M68K_MMU_CM_040 0x0060
288#define M68K_MMU_M_040 0x0010
289#define M68K_MMU_WP_040 0x0004
290#define M68K_MMU_T_040 0x0002
291#define M68K_MMU_R_040 0x0001
292
293#define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \
294 M68K_MMU_U0_040 | M68K_MMU_S_040 | \
295 M68K_MMU_CM_040 | M68K_MMU_M_040 | \
296 M68K_MMU_WP_040)
297
298
299#define M68K_TCR_ENABLED 0x8000
300#define M68K_TCR_PAGE_8K 0x4000
301
302
303#define M68K_DESC_WRITEPROT 0x00000004
304#define M68K_DESC_USED 0x00000008
305#define M68K_DESC_MODIFIED 0x00000010
306#define M68K_DESC_CACHEMODE 0x00000060
307#define M68K_DESC_CM_WRTHRU 0x00000000
308#define M68K_DESC_CM_COPYBK 0x00000020
309#define M68K_DESC_CM_SERIAL 0x00000040
310#define M68K_DESC_CM_NCACHE 0x00000060
311#define M68K_DESC_SUPERONLY 0x00000080
312#define M68K_DESC_USERATTR 0x00000300
313#define M68K_DESC_USERATTR_SHIFT 8
314#define M68K_DESC_GLOBAL 0x00000400
315#define M68K_DESC_URESERVED 0x00000800
316
317#define M68K_ROOT_POINTER_ENTRIES 128
318#define M68K_4K_PAGE_MASK (~0xff)
319#define M68K_POINTER_BASE(entry) (entry & ~0x1ff)
320#define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc)
321#define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc)
322#define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK)
323#define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc)
324#define M68K_8K_PAGE_MASK (~0x7f)
325#define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK)
326#define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c)
327#define M68K_UDT_VALID(entry) (entry & 2)
328#define M68K_PDT_VALID(entry) (entry & 3)
329#define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2)
330#define M68K_INDIRECT_POINTER(addr) (addr & ~3)
331#define M68K_TTS_POINTER_SHIFT 18
332#define M68K_TTS_ROOT_SHIFT 25
333
334
335#define M68K_TTR_ADDR_BASE 0xff000000
336#define M68K_TTR_ADDR_MASK 0x00ff0000
337#define M68K_TTR_ADDR_MASK_SHIFT 8
338#define M68K_TTR_ENABLED 0x00008000
339#define M68K_TTR_SFIELD 0x00006000
340#define M68K_TTR_SFIELD_USER 0x0000
341#define M68K_TTR_SFIELD_SUPER 0x2000
342
343
344
345
346
347#define M68K_CR_ASID 0x003
348#define M68K_CR_ACR0 0x004
349#define M68K_CR_ACR1 0x005
350#define M68K_CR_ACR2 0x006
351#define M68K_CR_ACR3 0x007
352#define M68K_CR_MMUBAR 0x008
353
354
355#define M68K_CR_PC 0x80F
356
357
358#define M68K_CR_ROMBAR0 0xC00
359#define M68K_CR_ROMBAR1 0xC01
360#define M68K_CR_RAMBAR0 0xC04
361#define M68K_CR_RAMBAR1 0xC05
362#define M68K_CR_MPCR 0xC0C
363#define M68K_CR_EDRAMBAR 0xC0D
364#define M68K_CR_SECMBAR 0xC0E
365#define M68K_CR_MBAR 0xC0F
366
367
368#define M68K_CR_PCR1U0 0xD02
369#define M68K_CR_PCR1L0 0xD03
370#define M68K_CR_PCR2U0 0xD04
371#define M68K_CR_PCR2L0 0xD05
372#define M68K_CR_PCR3U0 0xD06
373#define M68K_CR_PCR3L0 0xD07
374#define M68K_CR_PCR1U1 0xD0A
375#define M68K_CR_PCR1L1 0xD0B
376#define M68K_CR_PCR2U1 0xD0C
377#define M68K_CR_PCR2L1 0xD0D
378#define M68K_CR_PCR3U1 0xD0E
379#define M68K_CR_PCR3L1 0xD0F
380
381
382
383#define M68K_CR_SFC 0x000
384#define M68K_CR_DFC 0x001
385#define M68K_CR_USP 0x800
386#define M68K_CR_VBR 0x801
387
388
389#define M68K_CR_CACR 0x002
390#define M68K_CR_CAAR 0x802
391#define M68K_CR_MSP 0x803
392#define M68K_CR_ISP 0x804
393
394
395#define M68K_CR_TC 0x003
396#define M68K_CR_ITT0 0x004
397#define M68K_CR_ITT1 0x005
398#define M68K_CR_DTT0 0x006
399#define M68K_CR_DTT1 0x007
400#define M68K_CR_MMUSR 0x805
401#define M68K_CR_URP 0x806
402#define M68K_CR_SRP 0x807
403
404
405#define M68K_CR_IACR0 0x004
406#define M68K_CR_IACR1 0x005
407#define M68K_CR_DACR0 0x006
408#define M68K_CR_DACR1 0x007
409
410#define M68K_FPIAR_SHIFT 0
411#define M68K_FPIAR (1 << M68K_FPIAR_SHIFT)
412#define M68K_FPSR_SHIFT 1
413#define M68K_FPSR (1 << M68K_FPSR_SHIFT)
414#define M68K_FPCR_SHIFT 2
415#define M68K_FPCR (1 << M68K_FPCR_SHIFT)
416
417
418
419
420#define FPSR_CC_MASK 0x0f000000
421#define FPSR_CC_A 0x01000000
422#define FPSR_CC_I 0x02000000
423#define FPSR_CC_Z 0x04000000
424#define FPSR_CC_N 0x08000000
425
426
427
428#define FPSR_QT_MASK 0x00ff0000
429#define FPSR_QT_SHIFT 16
430
431
432
433#define FPCR_RND_MASK 0x0030
434#define FPCR_RND_N 0x0000
435#define FPCR_RND_Z 0x0010
436#define FPCR_RND_M 0x0020
437#define FPCR_RND_P 0x0030
438
439
440#define FPCR_PREC_MASK 0x00c0
441#define FPCR_PREC_X 0x0000
442#define FPCR_PREC_S 0x0040
443#define FPCR_PREC_D 0x0080
444#define FPCR_PREC_U 0x00c0
445
446#define FPCR_EXCP_MASK 0xff00
447
448
449#define M68K_CACR_EUSP 0x10
450
451#define MACSR_PAV0 0x100
452#define MACSR_OMC 0x080
453#define MACSR_SU 0x040
454#define MACSR_FI 0x020
455#define MACSR_RT 0x010
456#define MACSR_N 0x008
457#define MACSR_Z 0x004
458#define MACSR_V 0x002
459#define MACSR_EV 0x001
460
461void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
462void m68k_switch_sp(CPUM68KState *env);
463
464void do_m68k_semihosting(CPUM68KState *env, int nr);
465
466
467
468
469
470enum m68k_features {
471 M68K_FEATURE_M68000,
472 M68K_FEATURE_CF_ISA_A,
473 M68K_FEATURE_CF_ISA_B,
474 M68K_FEATURE_CF_ISA_APLUSC,
475 M68K_FEATURE_BRAL,
476 M68K_FEATURE_CF_FPU,
477 M68K_FEATURE_CF_MAC,
478 M68K_FEATURE_CF_EMAC,
479 M68K_FEATURE_CF_EMAC_B,
480 M68K_FEATURE_USP,
481 M68K_FEATURE_EXT_FULL,
482 M68K_FEATURE_WORD_INDEX,
483 M68K_FEATURE_SCALED_INDEX,
484 M68K_FEATURE_LONG_MULDIV,
485 M68K_FEATURE_QUAD_MULDIV,
486 M68K_FEATURE_BCCL,
487 M68K_FEATURE_BITFIELD,
488 M68K_FEATURE_FPU,
489 M68K_FEATURE_CAS,
490 M68K_FEATURE_BKPT,
491 M68K_FEATURE_RTD,
492 M68K_FEATURE_CHK2,
493 M68K_FEATURE_M68040,
494 M68K_FEATURE_MOVEP,
495};
496
497static inline int m68k_feature(CPUM68KState *env, int feature)
498{
499 return (env->features & (1u << feature)) != 0;
500}
501
502void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
503
504void register_m68k_insns (CPUM68KState *env);
505
506
507
508
509
510#define TARGET_PAGE_BITS 12
511
512enum {
513
514 ACCESS_SUPER = 0x01,
515
516 ACCESS_STORE = 0x02,
517
518 ACCESS_DEBUG = 0x04,
519
520 ACCESS_PTEST = 0x08,
521
522 ACCESS_CODE = 0x10,
523 ACCESS_DATA = 0x20,
524};
525
526#define TARGET_PHYS_ADDR_SPACE_BITS 32
527#define TARGET_VIRT_ADDR_SPACE_BITS 32
528
529#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
530#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
531#define CPU_RESOLVING_TYPE TYPE_M68K_CPU
532
533#define cpu_signal_handler cpu_m68k_signal_handler
534#define cpu_list m68k_cpu_list
535
536
537#define MMU_MODE0_SUFFIX _kernel
538#define MMU_MODE1_SUFFIX _user
539#define MMU_KERNEL_IDX 0
540#define MMU_USER_IDX 1
541static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
542{
543 return (env->sr & SR_S) == 0 ? 1 : 0;
544}
545
546int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
547 int mmu_idx);
548void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr,
549 bool is_write, bool is_exec, int is_asi,
550 unsigned size);
551
552#include "exec/cpu-all.h"
553
554
555#define TB_FLAGS_MACSR 0x0f
556#define TB_FLAGS_MSR_S_BIT 13
557#define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT)
558#define TB_FLAGS_SFC_S_BIT 14
559#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT)
560#define TB_FLAGS_DFC_S_BIT 15
561#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT)
562
563static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
564 target_ulong *cs_base, uint32_t *flags)
565{
566 *pc = env->pc;
567 *cs_base = 0;
568 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
569 if (env->sr & SR_S) {
570 *flags |= TB_FLAGS_MSR_S;
571 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
572 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
573 }
574}
575
576void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUM68KState *env);
577#endif
578