LXR qemu/target/microblaze/cpu.h

   1/*
   2 *  MicroBlaze virtual CPU header
   3 *
   4 *  Copyright (c) 2009 Edgar E. Iglesias
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef MICROBLAZE_CPU_H
  21#define MICROBLAZE_CPU_H
  22
  23#include "qemu-common.h"
  24#include "cpu-qom.h"
  25
  26#define TARGET_LONG_BITS 64
  27
  28#define CPUArchState struct CPUMBState
  29
  30#include "exec/cpu-defs.h"
  31#include "fpu/softfloat-types.h"
  32struct CPUMBState;
  33typedef struct CPUMBState CPUMBState;
  34#if !defined(CONFIG_USER_ONLY)
  35#include "mmu.h"
  36#endif
  37
  38#define EXCP_MMU        1
  39#define EXCP_IRQ        2
  40#define EXCP_BREAK      3
  41#define EXCP_HW_BREAK   4
  42#define EXCP_HW_EXCP    5
  43
  44/* MicroBlaze-specific interrupt pending bits.  */
  45#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
  46
  47/* Meanings of the MBCPU object's two inbound GPIO lines */
  48#define MB_CPU_IRQ 0
  49#define MB_CPU_FIR 1
  50
  51/* Register aliases. R0 - R15 */
  52#define R_SP     1
  53#define SR_PC    0
  54#define SR_MSR   1
  55#define SR_EAR   3
  56#define SR_ESR   5
  57#define SR_FSR   7
  58#define SR_BTR   0xb
  59#define SR_EDR   0xd
  60
  61/* MSR flags.  */
  62#define MSR_BE  (1<<0) /* 0x001 */
  63#define MSR_IE  (1<<1) /* 0x002 */
  64#define MSR_C   (1<<2) /* 0x004 */
  65#define MSR_BIP (1<<3) /* 0x008 */
  66#define MSR_FSL (1<<4) /* 0x010 */
  67#define MSR_ICE (1<<5) /* 0x020 */
  68#define MSR_DZ  (1<<6) /* 0x040 */
  69#define MSR_DCE (1<<7) /* 0x080 */
  70#define MSR_EE  (1<<8) /* 0x100 */
  71#define MSR_EIP (1<<9) /* 0x200 */
  72#define MSR_PVR (1<<10) /* 0x400 */
  73#define MSR_CC  (1<<31)
  74
  75/* Machine State Register (MSR) Fields */
  76#define MSR_UM (1<<11) /* User Mode */
  77#define MSR_UMS        (1<<12) /* User Mode Save */
  78#define MSR_VM (1<<13) /* Virtual Mode */
  79#define MSR_VMS        (1<<14) /* Virtual Mode Save */
  80
  81#define MSR_KERNEL      MSR_EE|MSR_VM
  82//#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
  83#define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
  84//#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
  85
  86/* Exception State Register (ESR) Fields */
  87#define          ESR_DIZ       (1<<11) /* Zone Protection */
  88#define          ESR_S         (1<<10) /* Store instruction */
  89
  90#define          ESR_ESS_FSL_OFFSET     5
  91
  92#define          ESR_EC_FSL             0
  93#define          ESR_EC_UNALIGNED_DATA  1
  94#define          ESR_EC_ILLEGAL_OP      2
  95#define          ESR_EC_INSN_BUS        3
  96#define          ESR_EC_DATA_BUS        4
  97#define          ESR_EC_DIVZERO         5
  98#define          ESR_EC_FPU             6
  99#define          ESR_EC_PRIVINSN        7
 100#define          ESR_EC_STACKPROT       7  /* Same as PRIVINSN.  */
 101#define          ESR_EC_DATA_STORAGE    8
 102#define          ESR_EC_INSN_STORAGE    9
 103#define          ESR_EC_DATA_TLB        10
 104#define          ESR_EC_INSN_TLB        11
 105#define          ESR_EC_MASK            31
 106
 107/* Floating Point Status Register (FSR) Bits */
 108#define FSR_IO          (1<<4) /* Invalid operation */
 109#define FSR_DZ          (1<<3) /* Divide-by-zero */
 110#define FSR_OF          (1<<2) /* Overflow */
 111#define FSR_UF          (1<<1) /* Underflow */
 112#define FSR_DO          (1<<0) /* Denormalized operand error */
 113
 114/* Version reg.  */
 115/* Basic PVR mask */
 116#define PVR0_PVR_FULL_MASK              0x80000000
 117#define PVR0_USE_BARREL_MASK            0x40000000
 118#define PVR0_USE_DIV_MASK               0x20000000
 119#define PVR0_USE_HW_MUL_MASK            0x10000000
 120#define PVR0_USE_FPU_MASK               0x08000000
 121#define PVR0_USE_EXC_MASK               0x04000000
 122#define PVR0_USE_ICACHE_MASK            0x02000000
 123#define PVR0_USE_DCACHE_MASK            0x01000000
 124#define PVR0_USE_MMU_MASK               0x00800000
 125#define PVR0_USE_BTC                    0x00400000
 126#define PVR0_ENDI_MASK                  0x00200000
 127#define PVR0_FAULT                      0x00100000
 128#define PVR0_VERSION_MASK               0x0000FF00
 129#define PVR0_USER1_MASK                 0x000000FF
 130#define PVR0_SPROT_MASK                 0x00000001
 131
 132#define PVR0_VERSION_SHIFT              8
 133
 134/* User 2 PVR mask */
 135#define PVR1_USER2_MASK                 0xFFFFFFFF
 136
 137/* Configuration PVR masks */
 138#define PVR2_D_OPB_MASK                 0x80000000
 139#define PVR2_D_LMB_MASK                 0x40000000
 140#define PVR2_I_OPB_MASK                 0x20000000
 141#define PVR2_I_LMB_MASK                 0x10000000
 142#define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
 143#define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
 144#define PVR2_D_PLB_MASK                 0x02000000      /* new */
 145#define PVR2_I_PLB_MASK                 0x01000000      /* new */
 146#define PVR2_INTERCONNECT               0x00800000      /* new */
 147#define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
 148#define PVR2_USE_FSL_EXC                0x00040000      /* new */
 149#define PVR2_USE_MSR_INSTR              0x00020000
 150#define PVR2_USE_PCMP_INSTR             0x00010000
 151#define PVR2_AREA_OPTIMISED             0x00008000
 152#define PVR2_USE_BARREL_MASK            0x00004000
 153#define PVR2_USE_DIV_MASK               0x00002000
 154#define PVR2_USE_HW_MUL_MASK            0x00001000
 155#define PVR2_USE_FPU_MASK               0x00000800
 156#define PVR2_USE_MUL64_MASK             0x00000400
 157#define PVR2_USE_FPU2_MASK              0x00000200      /* new */
 158#define PVR2_USE_IPLBEXC                0x00000100
 159#define PVR2_USE_DPLBEXC                0x00000080
 160#define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
 161#define PVR2_UNALIGNED_EXC_MASK         0x00000020
 162#define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
 163#define PVR2_IOPB_BUS_EXC_MASK          0x00000008
 164#define PVR2_DOPB_BUS_EXC_MASK          0x00000004
 165#define PVR2_DIV_ZERO_EXC_MASK          0x00000002
 166#define PVR2_FPU_EXC_MASK               0x00000001
 167
 168/* Debug and exception PVR masks */
 169#define PVR3_DEBUG_ENABLED_MASK         0x80000000
 170#define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
 171#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
 172#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
 173#define PVR3_FSL_LINKS_MASK             0x00000380
 174
 175/* ICache config PVR masks */
 176#define PVR4_USE_ICACHE_MASK            0x80000000
 177#define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
 178#define PVR4_ICACHE_USE_FSL_MASK        0x02000000
 179#define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
 180#define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
 181#define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000
 182
 183/* DCache config PVR masks */
 184#define PVR5_USE_DCACHE_MASK            0x80000000
 185#define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
 186#define PVR5_DCACHE_USE_FSL_MASK        0x02000000
 187#define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
 188#define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
 189#define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
 190#define PVR5_DCACHE_WRITEBACK_MASK      0x00004000
 191
 192/* ICache base address PVR mask */
 193#define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF
 194
 195/* ICache high address PVR mask */
 196#define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF
 197
 198/* DCache base address PVR mask */
 199#define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF
 200
 201/* DCache high address PVR mask */
 202#define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF
 203
 204/* Target family PVR mask */
 205#define PVR10_TARGET_FAMILY_MASK        0xFF000000
 206#define PVR10_ASIZE_SHIFT               18
 207
 208/* MMU descrtiption */
 209#define PVR11_USE_MMU                   0xC0000000
 210#define PVR11_MMU_ITLB_SIZE             0x38000000
 211#define PVR11_MMU_DTLB_SIZE             0x07000000
 212#define PVR11_MMU_TLB_ACCESS            0x00C00000
 213#define PVR11_MMU_ZONES                 0x003E0000
 214/* MSR Reset value PVR mask */
 215#define PVR11_MSR_RESET_VALUE_MASK      0x000007FF
 216
 217#define C_PVR_NONE                      0
 218#define C_PVR_BASIC                     1
 219#define C_PVR_FULL                      2
 220
 221/* CPU flags.  */
 222
 223/* Condition codes.  */
 224#define CC_GE  5
 225#define CC_GT  4
 226#define CC_LE  3
 227#define CC_LT  2
 228#define CC_NE  1
 229#define CC_EQ  0
 230
 231#define NB_MMU_MODES    3
 232
 233#define STREAM_EXCEPTION (1 << 0)
 234#define STREAM_ATOMIC    (1 << 1)
 235#define STREAM_TEST      (1 << 2)
 236#define STREAM_CONTROL   (1 << 3)
 237#define STREAM_NONBLOCK  (1 << 4)
 238
 239struct CPUMBState {
 240    uint32_t debug;
 241    uint32_t btaken;
 242    uint64_t btarget;
 243    uint32_t bimm;
 244
 245    uint32_t imm;
 246    uint32_t regs[32];
 247    uint64_t sregs[14];
 248    float_status fp_status;
 249    /* Stack protectors. Yes, it's a hw feature.  */
 250    uint32_t slr, shr;
 251
 252    /* lwx/swx reserved address */
 253#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
 254    target_ulong res_addr;
 255    uint32_t res_val;
 256
 257    /* Internal flags.  */
 258#define IMM_FLAG        4
 259#define MSR_EE_FLAG     (1 << 8)
 260#define DRTI_FLAG       (1 << 16)
 261#define DRTE_FLAG       (1 << 17)
 262#define DRTB_FLAG       (1 << 18)
 263#define D_FLAG          (1 << 19)  /* Bit in ESR.  */
 264/* TB dependent CPUMBState.  */
 265#define IFLAGS_TB_MASK  (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
 266    uint32_t iflags;
 267
 268#if !defined(CONFIG_USER_ONLY)
 269    /* Unified MMU.  */
 270    struct microblaze_mmu mmu;
 271#endif
 272
 273    /* Fields up to this point are cleared by a CPU reset */
 274    struct {} end_reset_fields;
 275
 276    CPU_COMMON
 277
 278    /* These fields are preserved on reset.  */
 279
 280    struct {
 281        uint32_t regs[13];
 282    } pvr;
 283};
 284
 285/**
 286 * MicroBlazeCPU:
 287 * @env: #CPUMBState
 288 *
 289 * A MicroBlaze CPU.
 290 */
 291struct MicroBlazeCPU {
 292    /*< private >*/
 293    CPUState parent_obj;
 294
 295    /*< public >*/
 296
 297    /* Microblaze Configuration Settings */
 298    struct {
 299        bool stackprot;
 300        uint32_t base_vectors;
 301        uint8_t addr_size;
 302        uint8_t use_fpu;
 303        uint8_t use_hw_mul;
 304        bool use_barrel;
 305        bool use_div;
 306        bool use_msr_instr;
 307        bool use_pcmp_instr;
 308        bool use_mmu;
 309        bool dcache_writeback;
 310        bool endi;
 311        bool dopb_bus_exception;
 312        bool iopb_bus_exception;
 313        char *version;
 314        uint8_t pvr;
 315    } cfg;
 316
 317    CPUMBState env;
 318};
 319
 320static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
 321{
 322    return container_of(env, MicroBlazeCPU, env);
 323}
 324
 325#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))
 326
 327#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
 328
 329void mb_cpu_do_interrupt(CPUState *cs);
 330bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
 331void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 332                       int flags);
 333hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 334int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 335int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 336
 337void mb_tcg_init(void);
 338/* you can call this signal handler from your SIGBUS and SIGSEGV
 339   signal handlers to inform the virtual CPU of exceptions. non zero
 340   is returned if the signal was handled by the virtual CPU.  */
 341int cpu_mb_signal_handler(int host_signum, void *pinfo,
 342                          void *puc);
 343
 344/* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
 345#define TARGET_PAGE_BITS 12
 346
 347#define TARGET_PHYS_ADDR_SPACE_BITS 64
 348#define TARGET_VIRT_ADDR_SPACE_BITS 64
 349
 350#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU
 351
 352#define cpu_signal_handler cpu_mb_signal_handler
 353
 354/* MMU modes definitions */
 355#define MMU_MODE0_SUFFIX _nommu
 356#define MMU_MODE1_SUFFIX _kernel
 357#define MMU_MODE2_SUFFIX _user
 358#define MMU_NOMMU_IDX   0
 359#define MMU_KERNEL_IDX  1
 360#define MMU_USER_IDX    2
 361/* See NB_MMU_MODES further up the file.  */
 362
 363static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
 364{
 365    MicroBlazeCPU *cpu = mb_env_get_cpu(env);
 366
 367    /* Are we in nommu mode?.  */
 368    if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) {
 369        return MMU_NOMMU_IDX;
 370    }
 371
 372    if (env->sregs[SR_MSR] & MSR_UM) {
 373        return MMU_USER_IDX;
 374    }
 375    return MMU_KERNEL_IDX;
 376}
 377
 378int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
 379                            int mmu_idx);
 380
 381#include "exec/cpu-all.h"
 382
 383static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
 384                                        target_ulong *cs_base, uint32_t *flags)
 385{
 386    *pc = env->sregs[SR_PC];
 387    *cs_base = 0;
 388    *flags = (env->iflags & IFLAGS_TB_MASK) |
 389                 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
 390}
 391
 392#if !defined(CONFIG_USER_ONLY)
 393void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
 394                               unsigned size, MMUAccessType access_type,
 395                               int mmu_idx, MemTxAttrs attrs,
 396                               MemTxResult response, uintptr_t retaddr);
 397#endif
 398
 399#endif
 400