1#ifndef MIPS_CPU_H
2#define MIPS_CPU_H
3
4#define ALIGNED_ONLY
5
6#define CPUArchState struct CPUMIPSState
7
8#include "qemu-common.h"
9#include "cpu-qom.h"
10#include "mips-defs.h"
11#include "exec/cpu-defs.h"
12#include "fpu/softfloat.h"
13
14#define TCG_GUEST_DEFAULT_MO (0)
15
16struct CPUMIPSState;
17
18typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
19
20
21#define MSA_WRLEN (128)
22
23typedef union wr_t wr_t;
24union wr_t {
25 int8_t b[MSA_WRLEN/8];
26 int16_t h[MSA_WRLEN/16];
27 int32_t w[MSA_WRLEN/32];
28 int64_t d[MSA_WRLEN/64];
29};
30
31typedef union fpr_t fpr_t;
32union fpr_t {
33 float64 fd;
34 float32 fs[2];
35 uint64_t d;
36 uint32_t w[2];
37
38 wr_t wr;
39};
40
41
42
43#if defined(HOST_WORDS_BIGENDIAN)
44# define FP_ENDIAN_IDX 1
45#else
46# define FP_ENDIAN_IDX 0
47#endif
48
49typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
50struct CPUMIPSFPUContext {
51
52 fpr_t fpr[32];
53 float_status fp_status;
54
55 uint32_t fcr0;
56#define FCR0_FREP 29
57#define FCR0_UFRP 28
58#define FCR0_HAS2008 23
59#define FCR0_F64 22
60#define FCR0_L 21
61#define FCR0_W 20
62#define FCR0_3D 19
63#define FCR0_PS 18
64#define FCR0_D 17
65#define FCR0_S 16
66#define FCR0_PRID 8
67#define FCR0_REV 0
68
69 uint32_t fcr31_rw_bitmask;
70 uint32_t fcr31;
71#define FCR31_FS 24
72#define FCR31_ABS2008 19
73#define FCR31_NAN2008 18
74#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
75#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
76#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
77#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
78#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
79#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
80#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
81#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
82#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
83#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
84#define FP_INEXACT 1
85#define FP_UNDERFLOW 2
86#define FP_OVERFLOW 4
87#define FP_DIV0 8
88#define FP_INVALID 16
89#define FP_UNIMPLEMENTED 32
90};
91
92#define NB_MMU_MODES 4
93#define TARGET_INSN_START_EXTRA_WORDS 2
94
95typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
96struct CPUMIPSMVPContext {
97 int32_t CP0_MVPControl;
98#define CP0MVPCo_CPA 3
99#define CP0MVPCo_STLB 2
100#define CP0MVPCo_VPC 1
101#define CP0MVPCo_EVP 0
102 int32_t CP0_MVPConf0;
103#define CP0MVPC0_M 31
104#define CP0MVPC0_TLBS 29
105#define CP0MVPC0_GS 28
106#define CP0MVPC0_PCP 27
107#define CP0MVPC0_PTLBE 16
108#define CP0MVPC0_TCA 15
109#define CP0MVPC0_PVPE 10
110#define CP0MVPC0_PTC 0
111 int32_t CP0_MVPConf1;
112#define CP0MVPC1_CIM 31
113#define CP0MVPC1_CIF 30
114#define CP0MVPC1_PCX 20
115#define CP0MVPC1_PCP2 10
116#define CP0MVPC1_PCP1 0
117};
118
119typedef struct mips_def_t mips_def_t;
120
121#define MIPS_SHADOW_SET_MAX 16
122#define MIPS_TC_MAX 5
123#define MIPS_FPU_MAX 1
124#define MIPS_DSP_ACC 4
125#define MIPS_KSCRATCH_NUM 6
126#define MIPS_MAAR_MAX 16
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238#define CP0_REGISTER_00 0
239#define CP0_REGISTER_01 1
240#define CP0_REGISTER_02 2
241#define CP0_REGISTER_03 3
242#define CP0_REGISTER_04 4
243#define CP0_REGISTER_05 5
244#define CP0_REGISTER_06 6
245#define CP0_REGISTER_07 7
246#define CP0_REGISTER_08 8
247#define CP0_REGISTER_09 9
248#define CP0_REGISTER_10 10
249#define CP0_REGISTER_11 11
250#define CP0_REGISTER_12 12
251#define CP0_REGISTER_13 13
252#define CP0_REGISTER_14 14
253#define CP0_REGISTER_15 15
254#define CP0_REGISTER_16 16
255#define CP0_REGISTER_17 17
256#define CP0_REGISTER_18 18
257#define CP0_REGISTER_19 19
258#define CP0_REGISTER_20 20
259#define CP0_REGISTER_21 21
260#define CP0_REGISTER_22 22
261#define CP0_REGISTER_23 23
262#define CP0_REGISTER_24 24
263#define CP0_REGISTER_25 25
264#define CP0_REGISTER_26 26
265#define CP0_REGISTER_27 27
266#define CP0_REGISTER_28 28
267#define CP0_REGISTER_29 29
268#define CP0_REGISTER_30 30
269#define CP0_REGISTER_31 31
270
271
272
273#define CP0_REG00__INDEX 0
274#define CP0_REG00__VPCONTROL 4
275
276
277#define CP0_REG02__ENTRYLO0 0
278
279#define CP0_REG03__ENTRYLO1 0
280#define CP0_REG03__GLOBALNUM 1
281
282#define CP0_REG04__CONTEXT 0
283#define CP0_REG04__USERLOCAL 2
284#define CP0_REG04__DBGCONTEXTID 4
285#define CP0_REG00__MMID 5
286
287#define CP0_REG05__PAGEMASK 0
288#define CP0_REG05__PAGEGRAIN 1
289
290#define CP0_REG06__WIRED 0
291
292#define CP0_REG07__HWRENA 0
293
294#define CP0_REG08__BADVADDR 0
295#define CP0_REG08__BADINSTR 1
296#define CP0_REG08__BADINSTRP 2
297
298#define CP0_REG09__COUNT 0
299#define CP0_REG09__SAARI 6
300#define CP0_REG09__SAAR 7
301
302#define CP0_REG10__ENTRYHI 0
303#define CP0_REG10__GUESTCTL1 4
304#define CP0_REG10__GUESTCTL2 5
305
306#define CP0_REG11__COMPARE 0
307#define CP0_REG11__GUESTCTL0EXT 4
308
309#define CP0_REG12__STATUS 0
310#define CP0_REG12__INTCTL 1
311#define CP0_REG12__SRSCTL 2
312#define CP0_REG12__GUESTCTL0 6
313#define CP0_REG12__GTOFFSET 7
314
315#define CP0_REG13__CAUSE 0
316
317#define CP0_REG14__EPC 0
318
319#define CP0_REG15__PRID 0
320#define CP0_REG15__EBASE 1
321#define CP0_REG15__CDMMBASE 2
322#define CP0_REG15__CMGCRBASE 3
323
324#define CP0_REG16__CONFIG 0
325#define CP0_REG16__CONFIG1 1
326#define CP0_REG16__CONFIG2 2
327#define CP0_REG16__CONFIG3 3
328#define CP0_REG16__CONFIG4 4
329#define CP0_REG16__CONFIG5 5
330#define CP0_REG00__CONFIG7 7
331
332#define CP0_REG17__LLADDR 0
333#define CP0_REG17__MAAR 1
334#define CP0_REG17__MAARI 2
335
336#define CP0_REG18__WATCHLO0 0
337#define CP0_REG18__WATCHLO1 1
338#define CP0_REG18__WATCHLO2 2
339#define CP0_REG18__WATCHLO3 3
340
341#define CP0_REG19__WATCHHI0 0
342#define CP0_REG19__WATCHHI1 1
343#define CP0_REG19__WATCHHI2 2
344#define CP0_REG19__WATCHHI3 3
345
346#define CP0_REG20__XCONTEXT 0
347
348
349
350#define CP0_REG23__DEBUG 0
351
352#define CP0_REG24__DEPC 0
353
354#define CP0_REG25__PERFCTL0 0
355#define CP0_REG25__PERFCNT0 1
356#define CP0_REG25__PERFCTL1 2
357#define CP0_REG25__PERFCNT1 3
358#define CP0_REG25__PERFCTL2 4
359#define CP0_REG25__PERFCNT2 5
360#define CP0_REG25__PERFCTL3 6
361#define CP0_REG25__PERFCNT3 7
362
363#define CP0_REG00__ERRCTL 0
364
365#define CP0_REG27__CACHERR 0
366
367#define CP0_REG28__ITAGLO 0
368#define CP0_REG28__IDATALO 1
369#define CP0_REG28__DTAGLO 2
370#define CP0_REG28__DDATALO 3
371
372#define CP0_REG29__IDATAHI 1
373#define CP0_REG29__DDATAHI 3
374
375#define CP0_REG30__ERROREPC 0
376
377#define CP0_REG31__DESAVE 0
378#define CP0_REG31__KSCRATCH1 2
379#define CP0_REG31__KSCRATCH2 3
380#define CP0_REG31__KSCRATCH3 4
381#define CP0_REG31__KSCRATCH4 5
382#define CP0_REG31__KSCRATCH5 6
383#define CP0_REG31__KSCRATCH6 7
384
385
386typedef struct TCState TCState;
387struct TCState {
388 target_ulong gpr[32];
389 target_ulong PC;
390 target_ulong HI[MIPS_DSP_ACC];
391 target_ulong LO[MIPS_DSP_ACC];
392 target_ulong ACX[MIPS_DSP_ACC];
393 target_ulong DSPControl;
394 int32_t CP0_TCStatus;
395#define CP0TCSt_TCU3 31
396#define CP0TCSt_TCU2 30
397#define CP0TCSt_TCU1 29
398#define CP0TCSt_TCU0 28
399#define CP0TCSt_TMX 27
400#define CP0TCSt_RNST 23
401#define CP0TCSt_TDS 21
402#define CP0TCSt_DT 20
403#define CP0TCSt_DA 15
404#define CP0TCSt_A 13
405#define CP0TCSt_TKSU 11
406#define CP0TCSt_IXMT 10
407#define CP0TCSt_TASID 0
408 int32_t CP0_TCBind;
409#define CP0TCBd_CurTC 21
410#define CP0TCBd_TBE 17
411#define CP0TCBd_CurVPE 0
412 target_ulong CP0_TCHalt;
413 target_ulong CP0_TCContext;
414 target_ulong CP0_TCSchedule;
415 target_ulong CP0_TCScheFBack;
416 int32_t CP0_Debug_tcstatus;
417 target_ulong CP0_UserLocal;
418
419 int32_t msacsr;
420
421#define MSACSR_FS 24
422#define MSACSR_FS_MASK (1 << MSACSR_FS)
423#define MSACSR_NX 18
424#define MSACSR_NX_MASK (1 << MSACSR_NX)
425#define MSACSR_CEF 2
426#define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
427#define MSACSR_RM 0
428#define MSACSR_RM_MASK (0x3 << MSACSR_RM)
429#define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
430 MSACSR_FS_MASK)
431
432 float_status msa_fp_status;
433
434
435 uint64_t mmr[32];
436
437#define NUMBER_OF_MXU_REGISTERS 16
438 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
439 target_ulong mxu_cr;
440#define MXU_CR_LC 31
441#define MXU_CR_RC 30
442#define MXU_CR_BIAS 2
443#define MXU_CR_RD_EN 1
444#define MXU_CR_MXU_EN 0
445
446};
447
448struct MIPSITUState;
449typedef struct CPUMIPSState CPUMIPSState;
450struct CPUMIPSState {
451 TCState active_tc;
452 CPUMIPSFPUContext active_fpu;
453
454 uint32_t current_tc;
455 uint32_t current_fpu;
456
457 uint32_t SEGBITS;
458 uint32_t PABITS;
459#if defined(TARGET_MIPS64)
460# define PABITS_BASE 36
461#else
462# define PABITS_BASE 32
463#endif
464 target_ulong SEGMask;
465 uint64_t PAMask;
466#define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
467
468 int32_t msair;
469#define MSAIR_ProcID 8
470#define MSAIR_Rev 0
471
472
473
474
475 int32_t CP0_Index;
476
477 int32_t CP0_VPControl;
478#define CP0VPCtl_DIS 0
479
480
481
482 int32_t CP0_Random;
483 int32_t CP0_VPEControl;
484#define CP0VPECo_YSI 21
485#define CP0VPECo_GSI 20
486#define CP0VPECo_EXCPT 16
487#define CP0VPECo_TE 15
488#define CP0VPECo_TargTC 0
489 int32_t CP0_VPEConf0;
490#define CP0VPEC0_M 31
491#define CP0VPEC0_XTC 21
492#define CP0VPEC0_TCS 19
493#define CP0VPEC0_SCS 18
494#define CP0VPEC0_DSC 17
495#define CP0VPEC0_ICS 16
496#define CP0VPEC0_MVP 1
497#define CP0VPEC0_VPA 0
498 int32_t CP0_VPEConf1;
499#define CP0VPEC1_NCX 20
500#define CP0VPEC1_NCP2 10
501#define CP0VPEC1_NCP1 0
502 target_ulong CP0_YQMask;
503 target_ulong CP0_VPESchedule;
504 target_ulong CP0_VPEScheFBack;
505 int32_t CP0_VPEOpt;
506#define CP0VPEOpt_IWX7 15
507#define CP0VPEOpt_IWX6 14
508#define CP0VPEOpt_IWX5 13
509#define CP0VPEOpt_IWX4 12
510#define CP0VPEOpt_IWX3 11
511#define CP0VPEOpt_IWX2 10
512#define CP0VPEOpt_IWX1 9
513#define CP0VPEOpt_IWX0 8
514#define CP0VPEOpt_DWX7 7
515#define CP0VPEOpt_DWX6 6
516#define CP0VPEOpt_DWX5 5
517#define CP0VPEOpt_DWX4 4
518#define CP0VPEOpt_DWX3 3
519#define CP0VPEOpt_DWX2 2
520#define CP0VPEOpt_DWX1 1
521#define CP0VPEOpt_DWX0 0
522
523
524
525 uint64_t CP0_EntryLo0;
526
527
528
529 uint64_t CP0_EntryLo1;
530#if defined(TARGET_MIPS64)
531# define CP0EnLo_RI 63
532# define CP0EnLo_XI 62
533#else
534# define CP0EnLo_RI 31
535# define CP0EnLo_XI 30
536#endif
537 int32_t CP0_GlobalNumber;
538#define CP0GN_VPId 0
539
540
541
542 target_ulong CP0_Context;
543 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
544 int32_t CP0_MemoryMapID;
545
546
547
548 int32_t CP0_PageMask;
549 int32_t CP0_PageGrain_rw_bitmask;
550 int32_t CP0_PageGrain;
551#define CP0PG_RIE 31
552#define CP0PG_XIE 30
553#define CP0PG_ELPA 29
554#define CP0PG_IEC 27
555 target_ulong CP0_SegCtl0;
556 target_ulong CP0_SegCtl1;
557 target_ulong CP0_SegCtl2;
558#define CP0SC_PA 9
559#define CP0SC_PA_MASK (0x7FULL << CP0SC_PA)
560#define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
561#define CP0SC_AM 4
562#define CP0SC_AM_MASK (0x7ULL << CP0SC_AM)
563#define CP0SC_AM_UK 0ULL
564#define CP0SC_AM_MK 1ULL
565#define CP0SC_AM_MSK 2ULL
566#define CP0SC_AM_MUSK 3ULL
567#define CP0SC_AM_MUSUK 4ULL
568#define CP0SC_AM_USK 5ULL
569#define CP0SC_AM_UUSK 7ULL
570#define CP0SC_EU 3
571#define CP0SC_EU_MASK (1ULL << CP0SC_EU)
572#define CP0SC_C 0
573#define CP0SC_C_MASK (0x7ULL << CP0SC_C)
574#define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
575 CP0SC_PA_MASK)
576#define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
577 CP0SC_PA_1GMASK)
578#define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16))
579#define CP0SC1_XAM 59
580#define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
581#define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
582#define CP0SC2_XR 56
583#define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
584#define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
585 target_ulong CP0_PWBase;
586 target_ulong CP0_PWField;
587#if defined(TARGET_MIPS64)
588#define CP0PF_BDI 32
589#define CP0PF_GDI 24
590#define CP0PF_UDI 18
591#define CP0PF_MDI 12
592#define CP0PF_PTI 6
593#define CP0PF_PTEI 0
594#else
595#define CP0PF_GDW 24
596#define CP0PF_UDW 18
597#define CP0PF_MDW 12
598#define CP0PF_PTW 6
599#define CP0PF_PTEW 0
600#endif
601 target_ulong CP0_PWSize;
602#if defined(TARGET_MIPS64)
603#define CP0PS_BDW 32
604#endif
605#define CP0PS_PS 30
606#define CP0PS_GDW 24
607#define CP0PS_UDW 18
608#define CP0PS_MDW 12
609#define CP0PS_PTW 6
610#define CP0PS_PTEW 0
611
612
613
614 int32_t CP0_Wired;
615 int32_t CP0_PWCtl;
616#define CP0PC_PWEN 31
617#if defined(TARGET_MIPS64)
618#define CP0PC_PWDIREXT 30
619#define CP0PC_XK 28
620#define CP0PC_XS 27
621#define CP0PC_XU 26
622#endif
623#define CP0PC_DPH 7
624#define CP0PC_HUGEPG 6
625#define CP0PC_PSN 0
626 int32_t CP0_SRSConf0_rw_bitmask;
627 int32_t CP0_SRSConf0;
628#define CP0SRSC0_M 31
629#define CP0SRSC0_SRS3 20
630#define CP0SRSC0_SRS2 10
631#define CP0SRSC0_SRS1 0
632 int32_t CP0_SRSConf1_rw_bitmask;
633 int32_t CP0_SRSConf1;
634#define CP0SRSC1_M 31
635#define CP0SRSC1_SRS6 20
636#define CP0SRSC1_SRS5 10
637#define CP0SRSC1_SRS4 0
638 int32_t CP0_SRSConf2_rw_bitmask;
639 int32_t CP0_SRSConf2;
640#define CP0SRSC2_M 31
641#define CP0SRSC2_SRS9 20
642#define CP0SRSC2_SRS8 10
643#define CP0SRSC2_SRS7 0
644 int32_t CP0_SRSConf3_rw_bitmask;
645 int32_t CP0_SRSConf3;
646#define CP0SRSC3_M 31
647#define CP0SRSC3_SRS12 20
648#define CP0SRSC3_SRS11 10
649#define CP0SRSC3_SRS10 0
650 int32_t CP0_SRSConf4_rw_bitmask;
651 int32_t CP0_SRSConf4;
652#define CP0SRSC4_SRS15 20
653#define CP0SRSC4_SRS14 10
654#define CP0SRSC4_SRS13 0
655
656
657
658 int32_t CP0_HWREna;
659
660
661
662 target_ulong CP0_BadVAddr;
663 uint32_t CP0_BadInstr;
664 uint32_t CP0_BadInstrP;
665 uint32_t CP0_BadInstrX;
666
667
668
669 int32_t CP0_Count;
670 uint32_t CP0_SAARI;
671#define CP0SAARI_TARGET 0
672 uint64_t CP0_SAAR[2];
673#define CP0SAAR_BASE 12
674#define CP0SAAR_SIZE 1
675#define CP0SAAR_EN 0
676
677
678
679 target_ulong CP0_EntryHi;
680#define CP0EnHi_EHINV 10
681 target_ulong CP0_EntryHi_ASID_mask;
682
683
684
685 int32_t CP0_Compare;
686
687
688
689 int32_t CP0_Status;
690#define CP0St_CU3 31
691#define CP0St_CU2 30
692#define CP0St_CU1 29
693#define CP0St_CU0 28
694#define CP0St_RP 27
695#define CP0St_FR 26
696#define CP0St_RE 25
697#define CP0St_MX 24
698#define CP0St_PX 23
699#define CP0St_BEV 22
700#define CP0St_TS 21
701#define CP0St_SR 20
702#define CP0St_NMI 19
703#define CP0St_IM 8
704#define CP0St_KX 7
705#define CP0St_SX 6
706#define CP0St_UX 5
707#define CP0St_KSU 3
708#define CP0St_ERL 2
709#define CP0St_EXL 1
710#define CP0St_IE 0
711 int32_t CP0_IntCtl;
712#define CP0IntCtl_IPTI 29
713#define CP0IntCtl_IPPCI 26
714#define CP0IntCtl_VS 5
715 int32_t CP0_SRSCtl;
716#define CP0SRSCtl_HSS 26
717#define CP0SRSCtl_EICSS 18
718#define CP0SRSCtl_ESS 12
719#define CP0SRSCtl_PSS 6
720#define CP0SRSCtl_CSS 0
721 int32_t CP0_SRSMap;
722#define CP0SRSMap_SSV7 28
723#define CP0SRSMap_SSV6 24
724#define CP0SRSMap_SSV5 20
725#define CP0SRSMap_SSV4 16
726#define CP0SRSMap_SSV3 12
727#define CP0SRSMap_SSV2 8
728#define CP0SRSMap_SSV1 4
729#define CP0SRSMap_SSV0 0
730
731
732
733 int32_t CP0_Cause;
734#define CP0Ca_BD 31
735#define CP0Ca_TI 30
736#define CP0Ca_CE 28
737#define CP0Ca_DC 27
738#define CP0Ca_PCI 26
739#define CP0Ca_IV 23
740#define CP0Ca_WP 22
741#define CP0Ca_IP 8
742#define CP0Ca_IP_mask 0x0000FF00
743#define CP0Ca_EC 2
744
745
746
747 target_ulong CP0_EPC;
748
749
750
751 int32_t CP0_PRid;
752 target_ulong CP0_EBase;
753 target_ulong CP0_EBaseWG_rw_bitmask;
754#define CP0EBase_WG 11
755 target_ulong CP0_CMGCRBase;
756
757
758
759 int32_t CP0_Config0;
760#define CP0C0_M 31
761#define CP0C0_K23 28
762#define CP0C0_KU 25
763#define CP0C0_MDU 20
764#define CP0C0_MM 18
765#define CP0C0_BM 16
766#define CP0C0_Impl 16
767#define CP0C0_BE 15
768#define CP0C0_AT 13
769#define CP0C0_AR 10
770#define CP0C0_MT 7
771#define CP0C0_VI 3
772#define CP0C0_K0 0
773 int32_t CP0_Config1;
774#define CP0C1_M 31
775#define CP0C1_MMU 25
776#define CP0C1_IS 22
777#define CP0C1_IL 19
778#define CP0C1_IA 16
779#define CP0C1_DS 13
780#define CP0C1_DL 10
781#define CP0C1_DA 7
782#define CP0C1_C2 6
783#define CP0C1_MD 5
784#define CP0C1_PC 4
785#define CP0C1_WR 3
786#define CP0C1_CA 2
787#define CP0C1_EP 1
788#define CP0C1_FP 0
789 int32_t CP0_Config2;
790#define CP0C2_M 31
791#define CP0C2_TU 28
792#define CP0C2_TS 24
793#define CP0C2_TL 20
794#define CP0C2_TA 16
795#define CP0C2_SU 12
796#define CP0C2_SS 8
797#define CP0C2_SL 4
798#define CP0C2_SA 0
799 int32_t CP0_Config3;
800#define CP0C3_M 31
801#define CP0C3_BPG 30
802#define CP0C3_CMGCR 29
803#define CP0C3_MSAP 28
804#define CP0C3_BP 27
805#define CP0C3_BI 26
806#define CP0C3_SC 25
807#define CP0C3_PW 24
808#define CP0C3_VZ 23
809#define CP0C3_IPLV 21
810#define CP0C3_MMAR 18
811#define CP0C3_MCU 17
812#define CP0C3_ISA_ON_EXC 16
813#define CP0C3_ISA 14
814#define CP0C3_ULRI 13
815#define CP0C3_RXI 12
816#define CP0C3_DSP2P 11
817#define CP0C3_DSPP 10
818#define CP0C3_CTXTC 9
819#define CP0C3_ITL 8
820#define CP0C3_LPA 7
821#define CP0C3_VEIC 6
822#define CP0C3_VInt 5
823#define CP0C3_SP 4
824#define CP0C3_CDMM 3
825#define CP0C3_MT 2
826#define CP0C3_SM 1
827#define CP0C3_TL 0
828 int32_t CP0_Config4;
829 int32_t CP0_Config4_rw_bitmask;
830#define CP0C4_M 31
831#define CP0C4_IE 29
832#define CP0C4_AE 28
833#define CP0C4_VTLBSizeExt 24
834#define CP0C4_KScrExist 16
835#define CP0C4_MMUExtDef 14
836#define CP0C4_FTLBPageSize 8
837
838#define CP0C4_MMUSizeExt 0
839
840#define CP0C4_FTLBWays 4
841#define CP0C4_FTLBSets 0
842 int32_t CP0_Config5;
843 int32_t CP0_Config5_rw_bitmask;
844#define CP0C5_M 31
845#define CP0C5_K 30
846#define CP0C5_CV 29
847#define CP0C5_EVA 28
848#define CP0C5_MSAEn 27
849#define CP0C5_PMJ 23
850#define CP0C5_WR2 22
851#define CP0C5_NMS 21
852#define CP0C5_ULS 20
853#define CP0C5_XPA 19
854#define CP0C5_CRCP 18
855#define CP0C5_MI 17
856#define CP0C5_GI 15
857#define CP0C5_CA2 14
858#define CP0C5_XNP 13
859#define CP0C5_DEC 11
860#define CP0C5_L2C 10
861#define CP0C5_UFE 9
862#define CP0C5_FRE 8
863#define CP0C5_VP 7
864#define CP0C5_SBRI 6
865#define CP0C5_MVH 5
866#define CP0C5_LLB 4
867#define CP0C5_MRP 3
868#define CP0C5_UFR 2
869#define CP0C5_NFExists 0
870 int32_t CP0_Config6;
871 int32_t CP0_Config7;
872 uint64_t CP0_LLAddr;
873 uint64_t CP0_MAAR[MIPS_MAAR_MAX];
874 int32_t CP0_MAARI;
875
876
877
878
879 target_ulong lladdr;
880 target_ulong llval;
881 uint64_t llval_wp;
882 uint32_t llnewval_wp;
883 uint64_t CP0_LLAddr_rw_bitmask;
884 int CP0_LLAddr_shift;
885
886
887
888 target_ulong CP0_WatchLo[8];
889
890
891
892 int32_t CP0_WatchHi[8];
893#define CP0WH_ASID 16
894
895
896
897 target_ulong CP0_XContext;
898 int32_t CP0_Framemask;
899
900
901
902 int32_t CP0_Debug;
903#define CP0DB_DBD 31
904#define CP0DB_DM 30
905#define CP0DB_LSNM 28
906#define CP0DB_Doze 27
907#define CP0DB_Halt 26
908#define CP0DB_CNT 25
909#define CP0DB_IBEP 24
910#define CP0DB_DBEP 21
911#define CP0DB_IEXI 20
912#define CP0DB_VER 15
913#define CP0DB_DEC 10
914#define CP0DB_SSt 8
915#define CP0DB_DINT 5
916#define CP0DB_DIB 4
917#define CP0DB_DDBS 3
918#define CP0DB_DDBL 2
919#define CP0DB_DBp 1
920#define CP0DB_DSS 0
921
922
923
924 target_ulong CP0_DEPC;
925
926
927
928 int32_t CP0_Performance0;
929
930
931
932 int32_t CP0_ErrCtl;
933#define CP0EC_WST 29
934#define CP0EC_SPR 28
935#define CP0EC_ITC 26
936
937
938
939 uint64_t CP0_TagLo;
940 int32_t CP0_DataLo;
941
942
943
944 int32_t CP0_TagHi;
945 int32_t CP0_DataHi;
946
947
948
949 target_ulong CP0_ErrorEPC;
950
951
952
953 int32_t CP0_DESAVE;
954
955
956 TCState tcs[MIPS_SHADOW_SET_MAX];
957 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
958
959 int error_code;
960#define EXCP_TLB_NOMATCH 0x1
961#define EXCP_INST_NOTAVAIL 0x2
962 uint32_t hflags;
963
964#define MIPS_HFLAG_TMASK 0x1F5807FF
965#define MIPS_HFLAG_MODE 0x00007
966
967
968
969#define MIPS_HFLAG_KSU 0x00003
970#define MIPS_HFLAG_UM 0x00002
971#define MIPS_HFLAG_SM 0x00001
972#define MIPS_HFLAG_KM 0x00000
973#define MIPS_HFLAG_DM 0x00004
974#define MIPS_HFLAG_64 0x00008
975#define MIPS_HFLAG_CP0 0x00010
976#define MIPS_HFLAG_FPU 0x00020
977#define MIPS_HFLAG_F64 0x00040
978
979
980
981#define MIPS_HFLAG_COP1X 0x00080
982#define MIPS_HFLAG_RE 0x00100
983#define MIPS_HFLAG_AWRAP 0x00200
984#define MIPS_HFLAG_M16 0x00400
985#define MIPS_HFLAG_M16_SHIFT 10
986
987
988
989
990#define MIPS_HFLAG_BMASK_BASE 0x803800
991#define MIPS_HFLAG_B 0x00800
992#define MIPS_HFLAG_BC 0x01000
993#define MIPS_HFLAG_BL 0x01800
994#define MIPS_HFLAG_BR 0x02000
995
996#define MIPS_HFLAG_BMASK_EXT 0x7C000
997#define MIPS_HFLAG_B16 0x04000
998#define MIPS_HFLAG_BDS16 0x08000
999#define MIPS_HFLAG_BDS32 0x10000
1000#define MIPS_HFLAG_BDS_STRICT 0x20000
1001#define MIPS_HFLAG_BX 0x40000
1002#define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
1003
1004#define MIPS_HFLAG_DSP 0x080000
1005#define MIPS_HFLAG_DSP_R2 0x100000
1006#define MIPS_HFLAG_DSP_R3 0x20000000
1007
1008#define MIPS_HFLAG_HWRENA_ULR 0x200000
1009#define MIPS_HFLAG_SBRI 0x400000
1010#define MIPS_HFLAG_FBNSLOT 0x800000
1011#define MIPS_HFLAG_MSA 0x1000000
1012#define MIPS_HFLAG_FRE 0x2000000
1013#define MIPS_HFLAG_ELPA 0x4000000
1014#define MIPS_HFLAG_ITC_CACHE 0x8000000
1015#define MIPS_HFLAG_ERL 0x10000000
1016 target_ulong btarget;
1017 target_ulong bcond;
1018
1019 int SYNCI_Step;
1020 int CCRes;
1021 uint32_t CP0_Status_rw_bitmask;
1022 uint32_t CP0_TCStatus_rw_bitmask;
1023 uint64_t insn_flags;
1024 int saarp;
1025
1026
1027 struct {} end_reset_fields;
1028
1029 CPU_COMMON
1030
1031
1032 CPUMIPSMVPContext *mvp;
1033#if !defined(CONFIG_USER_ONLY)
1034 CPUMIPSTLBContext *tlb;
1035#endif
1036
1037 const mips_def_t *cpu_model;
1038 void *irq[8];
1039 QEMUTimer *timer;
1040 struct MIPSITUState *itu;
1041 MemoryRegion *itc_tag;
1042 target_ulong exception_base;
1043};
1044
1045
1046
1047
1048
1049
1050
1051struct MIPSCPU {
1052
1053 CPUState parent_obj;
1054
1055
1056 CPUMIPSState env;
1057};
1058
1059static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
1060{
1061 return container_of(env, MIPSCPU, env);
1062}
1063
1064#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
1065
1066#define ENV_OFFSET offsetof(MIPSCPU, env)
1067
1068void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1069
1070#define cpu_signal_handler cpu_mips_signal_handler
1071#define cpu_list mips_cpu_list
1072
1073extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
1074extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
1075
1076
1077
1078#define MMU_MODE0_SUFFIX _kernel
1079#define MMU_MODE1_SUFFIX _super
1080#define MMU_MODE2_SUFFIX _user
1081#define MMU_MODE3_SUFFIX _error
1082#define MMU_USER_IDX 2
1083
1084static inline int hflags_mmu_index(uint32_t hflags)
1085{
1086 if (hflags & MIPS_HFLAG_ERL) {
1087 return 3;
1088 } else {
1089 return hflags & MIPS_HFLAG_KSU;
1090 }
1091}
1092
1093static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
1094{
1095 return hflags_mmu_index(env->hflags);
1096}
1097
1098#include "exec/cpu-all.h"
1099
1100
1101
1102
1103enum {
1104
1105 ACCESS_USER = 0x00,
1106 ACCESS_SUPER = 0x01,
1107
1108 ACCESS_STORE = 0x02,
1109
1110 ACCESS_CODE = 0x10,
1111 ACCESS_INT = 0x20,
1112 ACCESS_FLOAT = 0x30,
1113};
1114
1115
1116enum {
1117 EXCP_NONE = -1,
1118 EXCP_RESET = 0,
1119 EXCP_SRESET,
1120 EXCP_DSS,
1121 EXCP_DINT,
1122 EXCP_DDBL,
1123 EXCP_DDBS,
1124 EXCP_NMI,
1125 EXCP_MCHECK,
1126 EXCP_EXT_INTERRUPT,
1127 EXCP_DFWATCH,
1128 EXCP_DIB,
1129 EXCP_IWATCH,
1130 EXCP_AdEL,
1131 EXCP_AdES,
1132 EXCP_TLBF,
1133 EXCP_IBE,
1134 EXCP_DBp,
1135 EXCP_SYSCALL,
1136 EXCP_BREAK,
1137 EXCP_CpU,
1138 EXCP_RI,
1139 EXCP_OVERFLOW,
1140 EXCP_TRAP,
1141 EXCP_FPE,
1142 EXCP_DWATCH,
1143 EXCP_LTLBL,
1144 EXCP_TLBL,
1145 EXCP_TLBS,
1146 EXCP_DBE,
1147 EXCP_THREAD,
1148 EXCP_MDMX,
1149 EXCP_C2E,
1150 EXCP_CACHE,
1151 EXCP_DSPDIS,
1152 EXCP_MSADIS,
1153 EXCP_MSAFPE,
1154 EXCP_TLBXI,
1155 EXCP_TLBRI,
1156
1157 EXCP_LAST = EXCP_TLBRI,
1158};
1159
1160
1161
1162
1163
1164
1165
1166#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
1167
1168int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
1169
1170#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
1171#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
1172#define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1173
1174bool cpu_supports_cps_smp(const char *cpu_type);
1175bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
1176void cpu_set_exception_base(int vp_index, target_ulong address);
1177
1178
1179void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
1180
1181
1182void itc_reconfigure(struct MIPSITUState *tag);
1183
1184
1185target_ulong exception_resume_pc (CPUMIPSState *env);
1186
1187static inline void restore_snan_bit_mode(CPUMIPSState *env)
1188{
1189 set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
1190 &env->active_fpu.fp_status);
1191}
1192
1193static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
1194 target_ulong *cs_base, uint32_t *flags)
1195{
1196 *pc = env->active_tc.PC;
1197 *cs_base = 0;
1198 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
1199 MIPS_HFLAG_HWRENA_ULR);
1200}
1201
1202#endif
1203