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20#include "qemu/osdep.h"
21#include "cpu.h"
22#include "exec/exec-all.h"
23#include "exec/helper-proto.h"
24#include "qemu/error-report.h"
25#include "sysemu/kvm.h"
26#include "kvm_ppc.h"
27#include "exec/log.h"
28#include "mmu-radix64.h"
29#include "mmu-book3s-v3.h"
30
31static bool ppc_radix64_get_fully_qualified_addr(CPUPPCState *env, vaddr eaddr,
32 uint64_t *lpid, uint64_t *pid)
33{
34 if (msr_hv) {
35 switch (eaddr & R_EADDR_QUADRANT) {
36 case R_EADDR_QUADRANT0:
37 *lpid = 0;
38 *pid = env->spr[SPR_BOOKS_PID];
39 break;
40 case R_EADDR_QUADRANT1:
41 *lpid = env->spr[SPR_LPIDR];
42 *pid = env->spr[SPR_BOOKS_PID];
43 break;
44 case R_EADDR_QUADRANT2:
45 *lpid = env->spr[SPR_LPIDR];
46 *pid = 0;
47 break;
48 case R_EADDR_QUADRANT3:
49 *lpid = 0;
50 *pid = 0;
51 break;
52 }
53 } else {
54 switch (eaddr & R_EADDR_QUADRANT) {
55 case R_EADDR_QUADRANT0:
56 *lpid = env->spr[SPR_LPIDR];
57 *pid = env->spr[SPR_BOOKS_PID];
58 break;
59 case R_EADDR_QUADRANT1:
60 case R_EADDR_QUADRANT2:
61 return false;
62 case R_EADDR_QUADRANT3:
63 *lpid = env->spr[SPR_LPIDR];
64 *pid = 0;
65 break;
66 }
67 }
68
69 return true;
70}
71
72static void ppc_radix64_raise_segi(PowerPCCPU *cpu, int rwx, vaddr eaddr)
73{
74 CPUState *cs = CPU(cpu);
75 CPUPPCState *env = &cpu->env;
76
77 if (rwx == 2) {
78 cs->exception_index = POWERPC_EXCP_ISEG;
79 } else {
80 cs->exception_index = POWERPC_EXCP_DSEG;
81 env->spr[SPR_DAR] = eaddr;
82 }
83 env->error_code = 0;
84}
85
86static void ppc_radix64_raise_si(PowerPCCPU *cpu, int rwx, vaddr eaddr,
87 uint32_t cause)
88{
89 CPUState *cs = CPU(cpu);
90 CPUPPCState *env = &cpu->env;
91
92 if (rwx == 2) {
93 cs->exception_index = POWERPC_EXCP_ISI;
94 env->error_code = cause;
95 } else {
96 cs->exception_index = POWERPC_EXCP_DSI;
97 if (rwx == 1) {
98 cause |= DSISR_ISSTORE;
99 }
100 env->spr[SPR_DSISR] = cause;
101 env->spr[SPR_DAR] = eaddr;
102 env->error_code = 0;
103 }
104}
105
106
107static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
108 int *fault_cause, int *prot)
109{
110 CPUPPCState *env = &cpu->env;
111 const int need_prot[] = { PAGE_READ, PAGE_WRITE, PAGE_EXEC };
112
113
114 if (((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO) && (rwx == 2)) {
115
116
117
118
119 *fault_cause |= SRR1_NOEXEC_GUARD;
120 return true;
121 }
122
123
124 if ((pte & R_PTE_EAA_PRIV) && msr_pr) {
125 *prot = 0;
126 } else if (msr_pr || (pte & R_PTE_EAA_PRIV)) {
127 *prot = ppc_radix64_get_prot_eaa(pte);
128 } else {
129 *prot = ppc_radix64_get_prot_eaa(pte);
130 *prot &= ppc_radix64_get_prot_amr(cpu);
131 }
132
133
134 if (need_prot[rwx] & ~(*prot)) {
135 *fault_cause |= DSISR_PROTFAULT;
136 return true;
137 }
138
139 return false;
140}
141
142static void ppc_radix64_set_rc(PowerPCCPU *cpu, int rwx, uint64_t pte,
143 hwaddr pte_addr, int *prot)
144{
145 CPUState *cs = CPU(cpu);
146 uint64_t npte;
147
148 npte = pte | R_PTE_R;
149
150 if (rwx == 1) {
151 npte |= R_PTE_C;
152 } else {
153
154
155
156
157 *prot &= ~PAGE_WRITE;
158 }
159
160 if (pte ^ npte) {
161 stq_phys(cs->as, pte_addr, npte);
162 }
163}
164
165static uint64_t ppc_radix64_walk_tree(PowerPCCPU *cpu, vaddr eaddr,
166 uint64_t base_addr, uint64_t nls,
167 hwaddr *raddr, int *psize,
168 int *fault_cause, hwaddr *pte_addr)
169{
170 CPUState *cs = CPU(cpu);
171 uint64_t index, pde;
172
173 if (nls < 5) {
174 *fault_cause |= DSISR_R_BADCONFIG;
175 return 0;
176 }
177
178
179 index = eaddr >> (*psize - nls);
180 index &= ((1UL << nls) - 1);
181 pde = ldq_phys(cs->as, base_addr + (index * sizeof(pde)));
182 if (!(pde & R_PTE_VALID)) {
183 *fault_cause |= DSISR_NOPTE;
184 return 0;
185 }
186
187 *psize -= nls;
188
189
190 if (pde & R_PTE_LEAF) {
191 uint64_t rpn = pde & R_PTE_RPN;
192 uint64_t mask = (1UL << *psize) - 1;
193
194
195 *raddr = (rpn & ~mask) | (eaddr & mask);
196 *pte_addr = base_addr + (index * sizeof(pde));
197 return pde;
198 }
199
200
201 return ppc_radix64_walk_tree(cpu, eaddr, pde & R_PDE_NLB, pde & R_PDE_NLS,
202 raddr, psize, fault_cause, pte_addr);
203}
204
205static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
206{
207 CPUPPCState *env = &cpu->env;
208
209 if (!(pate->dw0 & PATE0_HR)) {
210 return false;
211 }
212 if (lpid == 0 && !msr_hv) {
213 return false;
214 }
215
216 return true;
217}
218
219int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
220 int mmu_idx)
221{
222 CPUState *cs = CPU(cpu);
223 CPUPPCState *env = &cpu->env;
224 PPCVirtualHypervisorClass *vhc;
225 hwaddr raddr, pte_addr;
226 uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
227 int page_size, prot, fault_cause = 0;
228 ppc_v3_pate_t pate;
229
230 assert((rwx == 0) || (rwx == 1) || (rwx == 2));
231 assert(ppc64_use_proc_tbl(cpu));
232
233
234 if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
235
236 raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
237
238 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
239 PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
240 TARGET_PAGE_SIZE);
241 return 0;
242 }
243
244
245 if (!ppc_radix64_get_fully_qualified_addr(env, eaddr, &lpid, &pid)) {
246 ppc_radix64_raise_segi(cpu, rwx, eaddr);
247 return 1;
248 }
249
250
251 if (cpu->vhyp) {
252 vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
253 vhc->get_pate(cpu->vhyp, &pate);
254 } else {
255 if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
256 ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
257 return 1;
258 }
259 if (!validate_pate(cpu, lpid, &pate)) {
260 ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG);
261 }
262
263 if (lpid != 0) {
264 error_report("PowerNV guest support Unimplemented");
265 exit(1);
266 }
267 }
268
269
270 offset = pid * sizeof(struct prtb_entry);
271 size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
272 if (offset >= size) {
273
274 ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
275 return 1;
276 }
277 prtbe0 = ldq_phys(cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
278
279
280 page_size = PRTBE_R_GET_RTS(prtbe0);
281 pte = ppc_radix64_walk_tree(cpu, eaddr & R_EADDR_MASK,
282 prtbe0 & PRTBE_R_RPDB, prtbe0 & PRTBE_R_RPDS,
283 &raddr, &page_size, &fault_cause, &pte_addr);
284 if (!pte || ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, &prot)) {
285
286 ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
287 return 1;
288 }
289
290
291 ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, &prot);
292
293 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
294 prot, mmu_idx, 1UL << page_size);
295 return 0;
296}
297
298hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
299{
300 CPUState *cs = CPU(cpu);
301 CPUPPCState *env = &cpu->env;
302 PPCVirtualHypervisorClass *vhc;
303 hwaddr raddr, pte_addr;
304 uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
305 int page_size, fault_cause = 0;
306 ppc_v3_pate_t pate;
307
308
309 if (msr_dr == 0) {
310
311 return eaddr & 0x0FFFFFFFFFFFFFFFULL;
312 }
313
314
315 if (!ppc_radix64_get_fully_qualified_addr(env, eaddr, &lpid, &pid)) {
316 return -1;
317 }
318
319
320 if (cpu->vhyp) {
321 vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
322 vhc->get_pate(cpu->vhyp, &pate);
323 } else {
324 if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
325 return -1;
326 }
327 if (!validate_pate(cpu, lpid, &pate)) {
328 return -1;
329 }
330
331 if (lpid != 0) {
332 error_report("PowerNV guest support Unimplemented");
333 exit(1);
334 }
335 }
336
337
338 offset = pid * sizeof(struct prtb_entry);
339 size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
340 if (offset >= size) {
341
342 return -1;
343 }
344 prtbe0 = ldq_phys(cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
345
346
347 page_size = PRTBE_R_GET_RTS(prtbe0);
348 pte = ppc_radix64_walk_tree(cpu, eaddr & R_EADDR_MASK,
349 prtbe0 & PRTBE_R_RPDB, prtbe0 & PRTBE_R_RPDS,
350 &raddr, &page_size, &fault_cause, &pte_addr);
351 if (!pte) {
352 return -1;
353 }
354
355 return raddr & TARGET_PAGE_MASK;
356}
357