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18#include "qemu/osdep.h"
19#include "qemu/error-report.h"
20#include "exec/address-spaces.h"
21#include "cpu.h"
22#include "internal.h"
23#include "kvm_s390x.h"
24#include "sysemu/kvm.h"
25#include "exec/exec-all.h"
26#include "trace.h"
27#include "hw/s390x/storage-keys.h"
28
29
30
31
32
33#ifdef DEBUG_S390
34#ifdef DEBUG_S390_STDOUT
35#define DPRINTF(fmt, ...) \
36 do { fprintf(stderr, fmt, ## __VA_ARGS__); \
37 if (qemu_log_separate()) qemu_log(fmt, ##__VA_ARGS__); } while (0)
38#else
39#define DPRINTF(fmt, ...) \
40 do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
41#endif
42#else
43#define DPRINTF(fmt, ...) \
44 do { } while (0)
45#endif
46
47#ifdef DEBUG_S390_PTE
48#define PTE_DPRINTF DPRINTF
49#else
50#define PTE_DPRINTF(fmt, ...) \
51 do { } while (0)
52#endif
53
54
55#define FS_READ 0x800
56#define FS_WRITE 0x400
57
58static void trigger_access_exception(CPUS390XState *env, uint32_t type,
59 uint32_t ilen, uint64_t tec)
60{
61 S390CPU *cpu = s390_env_get_cpu(env);
62
63 if (kvm_enabled()) {
64 kvm_s390_access_exception(cpu, type, tec);
65 } else {
66 CPUState *cs = CPU(cpu);
67 if (type != PGM_ADDRESSING) {
68 stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
69 }
70 trigger_pgm_exception(env, type, ilen);
71 }
72}
73
74static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
75 uint64_t asc, int rw, bool exc)
76{
77 uint64_t tec;
78
79 tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | 4 | asc >> 46;
80
81 DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
82
83 if (!exc) {
84 return;
85 }
86
87 trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec);
88}
89
90static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
91 uint32_t type, uint64_t asc, int rw, bool exc)
92{
93 int ilen = ILEN_AUTO;
94 uint64_t tec;
95
96 tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | asc >> 46;
97
98 DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
99
100 if (!exc) {
101 return;
102 }
103
104
105 if (rw == MMU_INST_FETCH) {
106 ilen = 2;
107 }
108
109 trigger_access_exception(env, type, ilen, tec);
110}
111
112
113static bool is_low_address(uint64_t addr)
114{
115 return addr <= 511 || (addr >= 4096 && addr <= 4607);
116}
117
118
119static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc)
120{
121 if (!(env->cregs[0] & CR0_LOWPROT)) {
122 return false;
123 }
124 if (!(env->psw.mask & PSW_MASK_DAT)) {
125 return true;
126 }
127
128
129 switch (asc) {
130 case PSW_ASC_PRIMARY:
131 return !(env->cregs[1] & ASCE_PRIVATE_SPACE);
132 case PSW_ASC_SECONDARY:
133 return !(env->cregs[7] & ASCE_PRIVATE_SPACE);
134 case PSW_ASC_HOME:
135 return !(env->cregs[13] & ASCE_PRIVATE_SPACE);
136 default:
137
138 error_report("unsupported addressing mode");
139 exit(1);
140 }
141}
142
143
144
145
146
147target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
148{
149 if (raddr < 0x2000) {
150 return raddr + env->psa;
151 } else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
152 return raddr - env->psa;
153 }
154 return raddr;
155}
156
157
158static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
159 uint64_t asc, uint64_t pt_entry,
160 target_ulong *raddr, int *flags, int rw, bool exc)
161{
162 if (pt_entry & PAGE_INVALID) {
163 DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, pt_entry);
164 trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw, exc);
165 return -1;
166 }
167 if (pt_entry & PAGE_RES0) {
168 trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
169 return -1;
170 }
171 if (pt_entry & PAGE_RO) {
172 *flags &= ~PAGE_WRITE;
173 }
174
175 *raddr = pt_entry & ASCE_ORIGIN;
176
177 PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, pt_entry);
178
179 return 0;
180}
181
182
183static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
184 uint64_t asc, uint64_t st_entry,
185 target_ulong *raddr, int *flags, int rw,
186 bool exc)
187{
188 CPUState *cs = CPU(s390_env_get_cpu(env));
189 uint64_t origin, offs, pt_entry;
190
191 if (st_entry & SEGMENT_ENTRY_RO) {
192 *flags &= ~PAGE_WRITE;
193 }
194
195 if ((st_entry & SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
196
197 *raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);
198 PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry);
199 return 0;
200 }
201
202
203 origin = st_entry & SEGMENT_ENTRY_ORIGIN;
204 offs = (vaddr & VADDR_PX) >> 9;
205 pt_entry = ldq_phys(cs->as, origin + offs);
206 PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
207 __func__, origin, offs, pt_entry);
208 return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc);
209}
210
211
212static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
213 uint64_t asc, uint64_t entry, int level,
214 target_ulong *raddr, int *flags, int rw,
215 bool exc)
216{
217 CPUState *cs = CPU(s390_env_get_cpu(env));
218 uint64_t origin, offs, new_entry;
219 const int pchks[4] = {
220 PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
221 PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS
222 };
223
224 PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry);
225
226 origin = entry & REGION_ENTRY_ORIGIN;
227 offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
228
229 new_entry = ldq_phys(cs->as, origin + offs);
230 PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
231 __func__, origin, offs, new_entry);
232
233 if ((new_entry & REGION_ENTRY_INV) != 0) {
234 DPRINTF("%s: invalid region\n", __func__);
235 trigger_page_fault(env, vaddr, pchks[level / 4], asc, rw, exc);
236 return -1;
237 }
238
239 if ((new_entry & REGION_ENTRY_TYPE_MASK) != level) {
240 trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
241 return -1;
242 }
243
244 if (level == ASCE_TYPE_SEGMENT) {
245 return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags,
246 rw, exc);
247 }
248
249
250 offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3;
251 if (offs < ((new_entry & REGION_ENTRY_TF) >> 6)
252 || offs > (new_entry & REGION_ENTRY_LENGTH)) {
253 DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry);
254 trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw, exc);
255 return -1;
256 }
257
258 if ((env->cregs[0] & CR0_EDAT) && (new_entry & REGION_ENTRY_RO)) {
259 *flags &= ~PAGE_WRITE;
260 }
261
262
263 return mmu_translate_region(env, vaddr, asc, new_entry, level - 4,
264 raddr, flags, rw, exc);
265}
266
267static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
268 uint64_t asc, uint64_t asce, target_ulong *raddr,
269 int *flags, int rw, bool exc)
270{
271 int level;
272 int r;
273
274 if (asce & ASCE_REAL_SPACE) {
275
276 *raddr = vaddr;
277 return 0;
278 }
279
280 level = asce & ASCE_TYPE_MASK;
281 switch (level) {
282 case ASCE_TYPE_REGION1:
283 if ((vaddr >> 62) > (asce & ASCE_TABLE_LENGTH)) {
284 trigger_page_fault(env, vaddr, PGM_REG_FIRST_TRANS, asc, rw, exc);
285 return -1;
286 }
287 break;
288 case ASCE_TYPE_REGION2:
289 if (vaddr & 0xffe0000000000000ULL) {
290 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
291 " 0xffe0000000000000ULL\n", __func__, vaddr);
292 trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
293 return -1;
294 }
295 if ((vaddr >> 51 & 3) > (asce & ASCE_TABLE_LENGTH)) {
296 trigger_page_fault(env, vaddr, PGM_REG_SEC_TRANS, asc, rw, exc);
297 return -1;
298 }
299 break;
300 case ASCE_TYPE_REGION3:
301 if (vaddr & 0xfffffc0000000000ULL) {
302 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
303 " 0xfffffc0000000000ULL\n", __func__, vaddr);
304 trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
305 return -1;
306 }
307 if ((vaddr >> 40 & 3) > (asce & ASCE_TABLE_LENGTH)) {
308 trigger_page_fault(env, vaddr, PGM_REG_THIRD_TRANS, asc, rw, exc);
309 return -1;
310 }
311 break;
312 case ASCE_TYPE_SEGMENT:
313 if (vaddr & 0xffffffff80000000ULL) {
314 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
315 " 0xffffffff80000000ULL\n", __func__, vaddr);
316 trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
317 return -1;
318 }
319 if ((vaddr >> 29 & 3) > (asce & ASCE_TABLE_LENGTH)) {
320 trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc);
321 return -1;
322 }
323 break;
324 }
325
326 r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw,
327 exc);
328 if (!r && rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE)) {
329 trigger_prot_fault(env, vaddr, asc, rw, exc);
330 return -1;
331 }
332
333 return r;
334}
335
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345
346int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
347 target_ulong *raddr, int *flags, bool exc)
348{
349 static S390SKeysState *ss;
350 static S390SKeysClass *skeyclass;
351 int r = -1;
352 uint8_t key;
353
354 if (unlikely(!ss)) {
355 ss = s390_get_skeys_device();
356 skeyclass = S390_SKEYS_GET_CLASS(ss);
357 }
358
359 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
360 if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) {
361
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363
364
365
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367
368
369 *flags |= PAGE_WRITE_INV;
370 if (is_low_address(vaddr) && rw == MMU_DATA_STORE) {
371 if (exc) {
372 trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);
373 }
374 return -EACCES;
375 }
376 }
377
378 vaddr &= TARGET_PAGE_MASK;
379
380 if (!(env->psw.mask & PSW_MASK_DAT)) {
381 *raddr = vaddr;
382 r = 0;
383 goto out;
384 }
385
386 switch (asc) {
387 case PSW_ASC_PRIMARY:
388 PTE_DPRINTF("%s: asc=primary\n", __func__);
389 r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,
390 rw, exc);
391 break;
392 case PSW_ASC_HOME:
393 PTE_DPRINTF("%s: asc=home\n", __func__);
394 r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,
395 rw, exc);
396 break;
397 case PSW_ASC_SECONDARY:
398 PTE_DPRINTF("%s: asc=secondary\n", __func__);
399
400
401
402
403 if (rw == MMU_INST_FETCH) {
404 r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
405 raddr, flags, rw, exc);
406 *flags &= ~(PAGE_READ | PAGE_WRITE);
407 } else {
408 r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7],
409 raddr, flags, rw, exc);
410 *flags &= ~(PAGE_EXEC);
411 }
412 break;
413 case PSW_ASC_ACCREG:
414 default:
415 hw_error("guest switched to unknown asc mode\n");
416 break;
417 }
418
419 out:
420
421 *raddr = mmu_real2abs(env, *raddr);
422
423 if (r == 0 && *raddr < ram_size) {
424 if (skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) {
425 trace_get_skeys_nonzero(r);
426 return 0;
427 }
428
429 if (*flags & PAGE_READ) {
430 key |= SK_R;
431 }
432
433 if (*flags & PAGE_WRITE) {
434 key |= SK_C;
435 }
436
437 if (skeyclass->set_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) {
438 trace_set_skeys_nonzero(r);
439 return 0;
440 }
441 }
442
443 return r;
444}
445
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449
450
451static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
452 target_ulong *pages, bool is_write)
453{
454 uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
455 CPUS390XState *env = &cpu->env;
456 int ret, i, pflags;
457
458 for (i = 0; i < nr_pages; i++) {
459 ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, true);
460 if (ret) {
461 return ret;
462 }
463 if (!address_space_access_valid(&address_space_memory, pages[i],
464 TARGET_PAGE_SIZE, is_write,
465 MEMTXATTRS_UNSPECIFIED)) {
466 trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
467 return -EFAULT;
468 }
469 addr += TARGET_PAGE_SIZE;
470 }
471
472 return 0;
473}
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489
490int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
491 int len, bool is_write)
492{
493 int currlen, nr_pages, i;
494 target_ulong *pages;
495 int ret;
496
497 if (kvm_enabled()) {
498 ret = kvm_s390_mem_op(cpu, laddr, ar, hostbuf, len, is_write);
499 if (ret >= 0) {
500 return ret;
501 }
502 }
503
504 nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS)
505 + 1;
506 pages = g_malloc(nr_pages * sizeof(*pages));
507
508 ret = translate_pages(cpu, laddr, nr_pages, pages, is_write);
509 if (ret == 0 && hostbuf != NULL) {
510
511 for (i = 0; i < nr_pages; i++) {
512 currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE));
513 cpu_physical_memory_rw(pages[i] | (laddr & ~TARGET_PAGE_MASK),
514 hostbuf, currlen, is_write);
515 laddr += currlen;
516 hostbuf += currlen;
517 len -= currlen;
518 }
519 }
520
521 g_free(pages);
522 return ret;
523}
524
525void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra)
526{
527
528#ifdef CONFIG_TCG
529 if (tcg_enabled()) {
530 cpu_loop_exit_restore(CPU(cpu), ra);
531 }
532#endif
533}
534
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537
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540
541
542
543int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
544 target_ulong *addr, int *flags)
545{
546 const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT;
547
548 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
549 if (is_low_address(raddr & TARGET_PAGE_MASK) && lowprot_enabled) {
550
551 *flags |= PAGE_WRITE_INV;
552 if (is_low_address(raddr) && rw == MMU_DATA_STORE) {
553 trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);
554 return -EACCES;
555 }
556 }
557
558 *addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK);
559
560
561 return 0;
562}
563